TMF Hg

comment cleanup default tip

  • Wed, 18 Aug 2010 14:17:42 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Wed, 18 Aug 2010 14:17:42 +0100] rev 19
  • comment cleanup

move all user parameters into top of module

  • Wed, 18 Aug 2010 14:14:38 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Wed, 18 Aug 2010 14:14:38 +0100] rev 18
  • move all user parameters into top of module

parameterise data and addr. buses, tidy up

  • Wed, 18 Aug 2010 14:10:48 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Wed, 18 Aug 2010 14:10:48 +0100] rev 17
  • parameterise data and addr. buses, tidy up

    Parameterised the width of the data and address buses, and the number of
    COLUMN, ROW and BANK address bits.

    Tidied up code to (hopefully!) work when bus widths are changed.

[wb_sdram] add nice comments to explain sdram timings

  • Wed, 11 Aug 2010 01:19:03 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Wed, 11 Aug 2010 01:19:03 +0100] rev 16
  • [wb_sdram] add nice comments to explain sdram timings

fully parameterise CLOCK_RATE and SDRAM timing

  • Wed, 11 Aug 2010 01:15:20 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Wed, 11 Aug 2010 01:15:20 +0100] rev 15
  • fully parameterise CLOCK_RATE and SDRAM timing

[wb_sdram] code tidy up

  • Tue, 10 Aug 2010 23:11:10 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 23:11:10 +0100] rev 14
  • [wb_sdram] code tidy up

[wb_sdram] add note re. CL=3 testing

  • Tue, 10 Aug 2010 22:51:47 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 22:51:47 +0100] rev 13
  • [wb_sdram] add note re. CL=3 testing

[wb_sdram] tidy up refresh time parameterisation

  • Tue, 10 Aug 2010 22:49:21 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 22:49:21 +0100] rev 12
  • [wb_sdram] tidy up refresh time parameterisation

[wb_sdram] lock debug pins low

  • Tue, 10 Aug 2010 22:14:22 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 22:14:22 +0100] rev 11
  • [wb_sdram] lock debug pins low

[wb_sdram] parameterise timing and CAS latency

  • Tue, 10 Aug 2010 22:11:51 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Tue, 10 Aug 2010 22:11:51 +0100] rev 10
  • [wb_sdram] parameterise timing and CAS latency