src/memory.c

Wed, 09 Feb 2011 16:35:49 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Wed, 09 Feb 2011 16:35:49 +0000
changeset 84
0d903718da81
parent 79
674226015c8a
child 93
09e3ddeb869a
permissions
-rw-r--r--

major work on keyboard driver

philpem@40 1 #include <stdio.h>
philpem@40 2 #include <stdlib.h>
philpem@40 3 #include <stdint.h>
philpem@40 4 #include <stdbool.h>
philpem@59 5 #include <assert.h>
philpem@40 6 #include "musashi/m68k.h"
philpem@40 7 #include "state.h"
philpem@40 8 #include "memory.h"
philpem@40 9
philpem@40 10 /******************
philpem@40 11 * Memory mapping
philpem@40 12 ******************/
philpem@40 13
philpem@40 14 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
philpem@40 15
philpem@59 16 uint32_t mapAddr(uint32_t addr, bool writing)/*{{{*/
philpem@40 17 {
philpem@40 18 if (addr < 0x400000) {
philpem@40 19 // RAM access. Check against the Map RAM
philpem@40 20 // Start by getting the original page address
philpem@40 21 uint16_t page = (addr >> 12) & 0x3FF;
philpem@40 22
philpem@40 23 // Look it up in the map RAM and get the physical page address
philpem@40 24 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@40 25
philpem@40 26 // Update the Page Status bits
philpem@40 27 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
philpem@40 28 if (pagebits != 0) {
philpem@40 29 if (writing)
philpem@40 30 state.map[page*2] |= 0x60; // Page written to (dirty)
philpem@40 31 else
philpem@40 32 state.map[page*2] |= 0x40; // Page accessed but not written
philpem@40 33 }
philpem@40 34
philpem@40 35 // Return the address with the new physical page spliced in
philpem@40 36 return (new_page_addr << 12) + (addr & 0xFFF);
philpem@40 37 } else {
philpem@40 38 // I/O, VRAM or MapRAM space; no mapping is performed or required
philpem@40 39 // TODO: assert here?
philpem@40 40 return addr;
philpem@40 41 }
philpem@59 42 }/*}}}*/
philpem@40 43
philpem@59 44 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)/*{{{*/
philpem@40 45 {
philpem@40 46 // Are we in Supervisor mode?
philpem@40 47 if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
philpem@40 48 // Yes. We can do anything we like.
philpem@40 49 return MEM_ALLOWED;
philpem@40 50
philpem@40 51 // If we're here, then we must be in User mode.
philpem@40 52 // Check that the user didn't access memory outside of the RAM area
philpem@40 53 if (addr >= 0x400000)
philpem@40 54 return MEM_UIE;
philpem@40 55
philpem@40 56 // This leaves us with Page Fault checking. Get the page bits for this page.
philpem@40 57 uint16_t page = (addr >> 12) & 0x3FF;
philpem@40 58 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
philpem@40 59
philpem@40 60 // Check page is present
philpem@40 61 if ((pagebits & 0x03) == 0)
philpem@40 62 return MEM_PAGEFAULT;
philpem@40 63
philpem@40 64 // User attempt to access the kernel
philpem@40 65 // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
philpem@40 66 if (((addr >> 19) & 0x0F) == 0)
philpem@40 67 return MEM_KERNEL;
philpem@40 68
philpem@40 69 // Check page is write enabled
philpem@68 70 if (writing && ((pagebits & 0x04) == 0))
philpem@40 71 return MEM_PAGE_NO_WE;
philpem@40 72
philpem@40 73 // Page access allowed.
philpem@40 74 return MEM_ALLOWED;
philpem@59 75 }/*}}}*/
philpem@40 76
philpem@40 77 #undef MAPRAM
philpem@40 78
philpem@40 79
philpem@40 80 /********************************************************
philpem@40 81 * m68k memory read/write support functions for Musashi
philpem@40 82 ********************************************************/
philpem@40 83
philpem@40 84 /**
philpem@40 85 * @brief Check memory access permissions for a write operation.
philpem@40 86 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
philpem@40 87 * gcc throws warnings when you have a return-with-value in a void
philpem@40 88 * function, even if the return-with-value is completely unreachable.
philpem@40 89 * Similarly it doesn't like it if you have a return without a value
philpem@40 90 * in a non-void function, even if it's impossible to ever reach the
philpem@40 91 * return-with-no-value. UGH!
philpem@40 92 */
philpem@59 93 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
philpem@59 94 #define ACCESS_CHECK_WR(address, bits) \
philpem@59 95 do { \
philpem@40 96 bool fault = false; \
philpem@40 97 /* MEM_STATUS st; */ \
philpem@40 98 switch (checkMemoryAccess(address, true)) { \
philpem@40 99 case MEM_ALLOWED: \
philpem@40 100 /* Access allowed */ \
philpem@40 101 break; \
philpem@40 102 case MEM_PAGEFAULT: \
philpem@40 103 /* Page fault */ \
philpem@44 104 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0); \
philpem@40 105 fault = true; \
philpem@40 106 break; \
philpem@40 107 case MEM_UIE: \
philpem@40 108 /* User access to memory above 4MB */ \
philpem@44 109 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0); \
philpem@40 110 fault = true; \
philpem@40 111 break; \
philpem@40 112 case MEM_KERNEL: \
philpem@40 113 case MEM_PAGE_NO_WE: \
philpem@40 114 /* kernel access or page not write enabled */ \
philpem@68 115 /* FIXME: which regs need setting? */ \
philpem@40 116 fault = true; \
philpem@40 117 break; \
philpem@40 118 } \
philpem@40 119 \
philpem@40 120 if (fault) { \
philpem@40 121 if (bits >= 16) \
philpem@68 122 state.bsr0 = 0x7C00; \
philpem@40 123 else \
philpem@40 124 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
philpem@40 125 state.bsr0 |= (address >> 16); \
philpem@40 126 state.bsr1 = address & 0xffff; \
philpem@40 127 printf("ERR: BusError WR\n"); \
philpem@40 128 m68k_pulse_bus_error(); \
philpem@40 129 return; \
philpem@40 130 } \
philpem@70 131 } while (0)
philpem@59 132 /*}}}*/
philpem@40 133
philpem@40 134 /**
philpem@40 135 * @brief Check memory access permissions for a read operation.
philpem@40 136 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
philpem@40 137 * gcc throws warnings when you have a return-with-value in a void
philpem@40 138 * function, even if the return-with-value is completely unreachable.
philpem@40 139 * Similarly it doesn't like it if you have a return without a value
philpem@40 140 * in a non-void function, even if it's impossible to ever reach the
philpem@40 141 * return-with-no-value. UGH!
philpem@40 142 */
philpem@59 143 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
philpem@59 144 #define ACCESS_CHECK_RD(address, bits) \
philpem@59 145 do { \
philpem@40 146 bool fault = false; \
philpem@40 147 /* MEM_STATUS st; */ \
philpem@40 148 switch (checkMemoryAccess(address, false)) { \
philpem@40 149 case MEM_ALLOWED: \
philpem@40 150 /* Access allowed */ \
philpem@40 151 break; \
philpem@40 152 case MEM_PAGEFAULT: \
philpem@40 153 /* Page fault */ \
philpem@44 154 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0); \
philpem@40 155 fault = true; \
philpem@40 156 break; \
philpem@40 157 case MEM_UIE: \
philpem@40 158 /* User access to memory above 4MB */ \
philpem@44 159 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0); \
philpem@40 160 fault = true; \
philpem@40 161 break; \
philpem@40 162 case MEM_KERNEL: \
philpem@40 163 case MEM_PAGE_NO_WE: \
philpem@40 164 /* kernel access or page not write enabled */ \
philpem@68 165 /* FIXME: which regs need setting? */ \
philpem@40 166 fault = true; \
philpem@40 167 break; \
philpem@40 168 } \
philpem@40 169 \
philpem@40 170 if (fault) { \
philpem@40 171 if (bits >= 16) \
philpem@68 172 state.bsr0 = 0x7C00; \
philpem@40 173 else \
philpem@40 174 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
philpem@40 175 state.bsr0 |= (address >> 16); \
philpem@40 176 state.bsr1 = address & 0xffff; \
philpem@40 177 printf("ERR: BusError RD\n"); \
philpem@40 178 m68k_pulse_bus_error(); \
philpem@40 179 return 0xFFFFFFFF; \
philpem@40 180 } \
philpem@70 181 } while (0)
philpem@59 182 /*}}}*/
philpem@40 183
philpem@40 184 // Logging macros
philpem@59 185 #define LOG_NOT_HANDLED_R(bits) \
philpem@64 186 if (!handled) printf("unhandled read%02d, addr=0x%08X\n", bits, address);
philpem@40 187
philpem@59 188 #define LOG_NOT_HANDLED_W(bits) \
philpem@64 189 if (!handled) printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
philpem@59 190
philpem@59 191 /********************************************************
philpem@59 192 * I/O read/write functions
philpem@59 193 ********************************************************/
philpem@40 194
philpem@40 195 /**
philpem@59 196 * Issue a warning if a read operation is made with an invalid size
philpem@40 197 */
philpem@66 198 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
philpem@40 199 {
philpem@59 200 assert((bits == 8) || (bits == 16) || (bits == 32));
philpem@59 201 if ((bits & allowed) == 0) {
philpem@66 202 printf("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
philpem@59 203 }
philpem@59 204 }
philpem@59 205
philpem@66 206 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
philpem@40 207 {
philpem@66 208 ENFORCE_SIZE(bits, address, true, allowed, regname);
philpem@66 209 }
philpem@66 210
philpem@66 211 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
philpem@66 212 {
philpem@66 213 ENFORCE_SIZE(bits, address, false, allowed, regname);
philpem@66 214 }
philpem@66 215
philpem@59 216 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
philpem@59 217 {
philpem@40 218 bool handled = false;
philpem@40 219
philpem@59 220 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 221 // I/O register space, zone A
philpem@40 222 switch (address & 0x0F0000) {
philpem@40 223 case 0x010000: // General Status Register
philpem@59 224 if (bits == 16)
philpem@59 225 state.genstat = (data & 0xffff);
philpem@59 226 else if (bits == 8) {
philpem@59 227 if (address & 0)
philpem@59 228 state.genstat = data;
philpem@59 229 else
philpem@59 230 state.genstat = data << 8;
philpem@59 231 }
philpem@40 232 handled = true;
philpem@40 233 break;
philpem@40 234 case 0x030000: // Bus Status Register 0
philpem@40 235 break;
philpem@40 236 case 0x040000: // Bus Status Register 1
philpem@40 237 break;
philpem@40 238 case 0x050000: // Phone status
philpem@40 239 break;
philpem@40 240 case 0x060000: // DMA Count
philpem@66 241 ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
philpem@59 242 state.dma_count = (data & 0x3FFF);
philpem@59 243 state.idmarw = ((data & 0x4000) == 0x4000);
philpem@59 244 state.dmaen = ((data & 0x8000) == 0x8000);
philpem@59 245 // This handles the "dummy DMA transfer" mentioned in the docs
philpem@59 246 // TODO: access check, peripheral access
philpem@59 247 if (!state.idmarw)
philpem@60 248 WR32(state.base_ram, mapAddr(address, true), state.base_ram_size - 1, 0xDEAD);
philpem@59 249 state.dma_count++;
philpem@53 250 handled = true;
philpem@40 251 break;
philpem@40 252 case 0x070000: // Line Printer Status Register
philpem@40 253 break;
philpem@40 254 case 0x080000: // Real Time Clock
philpem@40 255 break;
philpem@40 256 case 0x090000: // Phone registers
philpem@40 257 switch (address & 0x0FF000) {
philpem@40 258 case 0x090000: // Handset relay
philpem@40 259 case 0x098000:
philpem@40 260 break;
philpem@40 261 case 0x091000: // Line select 2
philpem@40 262 case 0x099000:
philpem@40 263 break;
philpem@40 264 case 0x092000: // Hook relay 1
philpem@40 265 case 0x09A000:
philpem@40 266 break;
philpem@40 267 case 0x093000: // Hook relay 2
philpem@40 268 case 0x09B000:
philpem@40 269 break;
philpem@40 270 case 0x094000: // Line 1 hold
philpem@40 271 case 0x09C000:
philpem@40 272 break;
philpem@40 273 case 0x095000: // Line 2 hold
philpem@40 274 case 0x09D000:
philpem@40 275 break;
philpem@40 276 case 0x096000: // Line 1 A-lead
philpem@40 277 case 0x09E000:
philpem@40 278 break;
philpem@40 279 case 0x097000: // Line 2 A-lead
philpem@40 280 case 0x09F000:
philpem@40 281 break;
philpem@40 282 }
philpem@40 283 break;
philpem@59 284 case 0x0A0000: // Miscellaneous Control Register
philpem@66 285 ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
philpem@59 286 // TODO: handle the ctrl bits properly
philpem@59 287 // TODO: &0x8000 --> dismiss 60hz intr
philpem@59 288 state.dma_reading = (data & 0x4000);
philpem@72 289 if (state.leds != ((~data & 0xF00) >> 8)) {
philpem@72 290 state.leds = (~data & 0xF00) >> 8;
philpem@72 291 printf("LEDs: %s %s %s %s\n",
philpem@72 292 (state.leds & 8) ? "R" : "-",
philpem@72 293 (state.leds & 4) ? "G" : "-",
philpem@72 294 (state.leds & 2) ? "Y" : "-",
philpem@72 295 (state.leds & 1) ? "R" : "-");
philpem@72 296 }
philpem@46 297 handled = true;
philpem@40 298 break;
philpem@40 299 case 0x0B0000: // TM/DIALWR
philpem@40 300 break;
philpem@59 301 case 0x0C0000: // Clear Status Register
philpem@59 302 state.genstat = 0xFFFF;
philpem@59 303 state.bsr0 = 0xFFFF;
philpem@59 304 state.bsr1 = 0xFFFF;
philpem@43 305 handled = true;
philpem@40 306 break;
philpem@40 307 case 0x0D0000: // DMA Address Register
philpem@59 308 if (address & 0x004000) {
philpem@59 309 // A14 high -- set most significant bits
philpem@59 310 state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
philpem@59 311 } else {
philpem@59 312 // A14 low -- set least significant bits
philpem@59 313 state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
philpem@59 314 }
philpem@59 315 handled = true;
philpem@40 316 break;
philpem@40 317 case 0x0E0000: // Disk Control Register
philpem@66 318 ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
philpem@59 319 // B7 = FDD controller reset
philpem@59 320 if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
philpem@59 321 // B6 = drive 0 select -- TODO
philpem@59 322 // B5 = motor enable -- TODO
philpem@59 323 // B4 = HDD controller reset -- TODO
philpem@59 324 // B3 = HDD0 select -- TODO
philpem@59 325 // B2,1,0 = HDD0 head select
philpem@59 326 handled = true;
philpem@40 327 break;
philpem@40 328 case 0x0F0000: // Line Printer Data Register
philpem@40 329 break;
philpem@40 330 }
philpem@40 331 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 332 // I/O register space, zone B
philpem@40 333 switch (address & 0xF00000) {
philpem@40 334 case 0xC00000: // Expansion slots
philpem@40 335 case 0xD00000:
philpem@40 336 switch (address & 0xFC0000) {
philpem@40 337 case 0xC00000: // Expansion slot 0
philpem@40 338 case 0xC40000: // Expansion slot 1
philpem@40 339 case 0xC80000: // Expansion slot 2
philpem@40 340 case 0xCC0000: // Expansion slot 3
philpem@40 341 case 0xD00000: // Expansion slot 4
philpem@40 342 case 0xD40000: // Expansion slot 5
philpem@40 343 case 0xD80000: // Expansion slot 6
philpem@40 344 case 0xDC0000: // Expansion slot 7
philpem@59 345 fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
philpem@59 346 handled = true;
philpem@40 347 break;
philpem@40 348 }
philpem@40 349 break;
philpem@40 350 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 351 case 0xF00000:
philpem@40 352 switch (address & 0x070000) {
philpem@40 353 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@40 354 break;
philpem@40 355 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@66 356 ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");
philpem@59 357 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
philpem@52 358 handled = true;
philpem@40 359 break;
philpem@40 360 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 361 break;
philpem@40 362 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 363 break;
philpem@40 364 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 365 switch (address & 0x077000) {
philpem@40 366 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@59 367 break;
philpem@44 368 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@66 369 ENFORCE_SIZE_W(bits, address, 16, "PIE");
philpem@59 370 state.pie = ((data & 0x8000) == 0x8000);
philpem@59 371 handled = true;
philpem@59 372 break;
philpem@40 373 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@59 374 break;
philpem@40 375 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@66 376 ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
philpem@59 377 state.romlmap = ((data & 0x8000) == 0x8000);
philpem@44 378 handled = true;
philpem@40 379 break;
philpem@59 380 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@66 381 ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
philpem@59 382 break;
philpem@59 383 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@66 384 ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
philpem@59 385 break;
philpem@59 386 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@66 387 ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
philpem@59 388 break;
philpem@59 389 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@66 390 ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
philpem@40 391 break;
philpem@40 392 }
philpem@40 393 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 394 break;
philpem@40 395 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 396 switch (address & 0x07F000) {
philpem@40 397 default:
philpem@40 398 break;
philpem@40 399 }
philpem@40 400 break;
philpem@40 401 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@84 402 // TODO: figure out which sizes are valid (probably just 8 and 16)
philpem@84 403 // ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER");
philpem@84 404 printf("KBD WR %02X => %04X\n", (address >> 1) & 3, data >> 8);
philpem@84 405 keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8);
philpem@84 406 handled = true;
philpem@40 407 break;
philpem@40 408 }
philpem@40 409 }
philpem@40 410 }
philpem@40 411
philpem@64 412 LOG_NOT_HANDLED_W(bits);
philpem@59 413 }/*}}}*/
philpem@40 414
philpem@59 415 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
philpem@59 416 {
philpem@59 417 bool handled = false;
philpem@59 418 uint32_t data = 0xFFFFFFFF;
philpem@40 419
philpem@59 420 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 421 // I/O register space, zone A
philpem@40 422 switch (address & 0x0F0000) {
philpem@40 423 case 0x010000: // General Status Register
philpem@66 424 ENFORCE_SIZE_R(bits, address, 16, "GENSTAT");
philpem@59 425 return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
philpem@40 426 break;
philpem@40 427 case 0x030000: // Bus Status Register 0
philpem@66 428 ENFORCE_SIZE_R(bits, address, 16, "BSR0");
philpem@59 429 return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
philpem@40 430 break;
philpem@40 431 case 0x040000: // Bus Status Register 1
philpem@66 432 ENFORCE_SIZE_R(bits, address, 16, "BSR1");
philpem@59 433 return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
philpem@40 434 break;
philpem@40 435 case 0x050000: // Phone status
philpem@66 436 ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
philpem@40 437 break;
philpem@40 438 case 0x060000: // DMA Count
philpem@55 439 // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
philpem@55 440 // Bit 14 is always unused, so leave it set
philpem@66 441 ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
philpem@59 442 return (state.dma_count & 0x3fff) | 0xC000;
philpem@40 443 break;
philpem@40 444 case 0x070000: // Line Printer Status Register
philpem@53 445 data = 0x00120012; // no parity error, no line printer error, no irqs from FDD or HDD
philpem@78 446 data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0;
philpem@59 447 return data;
philpem@40 448 break;
philpem@40 449 case 0x080000: // Real Time Clock
philpem@59 450 printf("READ NOTIMP: Realtime Clock\n");
philpem@40 451 break;
philpem@40 452 case 0x090000: // Phone registers
philpem@40 453 switch (address & 0x0FF000) {
philpem@40 454 case 0x090000: // Handset relay
philpem@40 455 case 0x098000:
philpem@40 456 break;
philpem@40 457 case 0x091000: // Line select 2
philpem@40 458 case 0x099000:
philpem@40 459 break;
philpem@40 460 case 0x092000: // Hook relay 1
philpem@40 461 case 0x09A000:
philpem@40 462 break;
philpem@40 463 case 0x093000: // Hook relay 2
philpem@40 464 case 0x09B000:
philpem@40 465 break;
philpem@40 466 case 0x094000: // Line 1 hold
philpem@40 467 case 0x09C000:
philpem@40 468 break;
philpem@40 469 case 0x095000: // Line 2 hold
philpem@40 470 case 0x09D000:
philpem@40 471 break;
philpem@40 472 case 0x096000: // Line 1 A-lead
philpem@40 473 case 0x09E000:
philpem@40 474 break;
philpem@40 475 case 0x097000: // Line 2 A-lead
philpem@40 476 case 0x09F000:
philpem@40 477 break;
philpem@40 478 }
philpem@40 479 break;
philpem@46 480 case 0x0A0000: // Miscellaneous Control Register -- write only!
philpem@46 481 handled = true;
philpem@40 482 break;
philpem@40 483 case 0x0B0000: // TM/DIALWR
philpem@40 484 break;
philpem@46 485 case 0x0C0000: // Clear Status Register -- write only!
philpem@43 486 handled = true;
philpem@40 487 break;
philpem@40 488 case 0x0D0000: // DMA Address Register
philpem@40 489 break;
philpem@40 490 case 0x0E0000: // Disk Control Register
philpem@40 491 break;
philpem@40 492 case 0x0F0000: // Line Printer Data Register
philpem@40 493 break;
philpem@40 494 }
philpem@40 495 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 496 // I/O register space, zone B
philpem@40 497 switch (address & 0xF00000) {
philpem@40 498 case 0xC00000: // Expansion slots
philpem@40 499 case 0xD00000:
philpem@40 500 switch (address & 0xFC0000) {
philpem@40 501 case 0xC00000: // Expansion slot 0
philpem@40 502 case 0xC40000: // Expansion slot 1
philpem@40 503 case 0xC80000: // Expansion slot 2
philpem@40 504 case 0xCC0000: // Expansion slot 3
philpem@40 505 case 0xD00000: // Expansion slot 4
philpem@40 506 case 0xD40000: // Expansion slot 5
philpem@40 507 case 0xD80000: // Expansion slot 6
philpem@40 508 case 0xDC0000: // Expansion slot 7
philpem@65 509 fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
philpem@65 510 handled = true;
philpem@40 511 break;
philpem@40 512 }
philpem@40 513 break;
philpem@40 514 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 515 case 0xF00000:
philpem@40 516 switch (address & 0x070000) {
philpem@40 517 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@40 518 break;
philpem@40 519 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@66 520 ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");
philpem@59 521 return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
philpem@40 522 break;
philpem@40 523 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 524 break;
philpem@40 525 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 526 break;
philpem@40 527 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 528 switch (address & 0x077000) {
philpem@40 529 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@44 530 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@40 531 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 532 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@40 533 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@40 534 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@40 535 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@44 536 // All write-only registers... TODO: bus error?
philpem@44 537 handled = true;
philpem@40 538 break;
philpem@44 539 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
philpem@40 540 break;
philpem@40 541 }
philpem@40 542 break;
philpem@40 543 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 544 break;
philpem@40 545 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 546 switch (address & 0x07F000) {
philpem@40 547 default:
philpem@40 548 break;
philpem@40 549 }
philpem@40 550 break;
philpem@40 551 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@84 552 // TODO: figure out which sizes are valid (probably just 8 and 16)
philpem@84 553 //ENFORCE_SIZE_R(bits, address, 16, "KEYBOARD CONTROLLER");
philpem@84 554 {
philpem@84 555 uint16_t data = keyboard_read(&state.kbd, (address >> 1) & 3);
philpem@84 556 data = (data << 8) + data;
philpem@84 557 //printf("KBD RD %02X => %04X\n", (address >> 1) & 3, data);
philpem@84 558 return data;
philpem@84 559 }
philpem@40 560 break;
philpem@40 561 }
philpem@40 562 }
philpem@40 563 }
philpem@40 564
philpem@64 565 LOG_NOT_HANDLED_R(bits);
philpem@64 566
philpem@59 567 return data;
philpem@59 568 }/*}}}*/
philpem@40 569
philpem@59 570
philpem@59 571 /********************************************************
philpem@59 572 * m68k memory read/write support functions for Musashi
philpem@59 573 ********************************************************/
philpem@59 574
philpem@59 575 /**
philpem@59 576 * @brief Read M68K memory, 32-bit
philpem@59 577 */
philpem@59 578 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
philpem@59 579 {
philpem@59 580 uint32_t data = 0xFFFFFFFF;
philpem@59 581
philpem@59 582 // If ROMLMAP is set, force system to access ROM
philpem@59 583 if (!state.romlmap)
philpem@59 584 address |= 0x800000;
philpem@59 585
philpem@59 586 // Check access permissions
philpem@59 587 ACCESS_CHECK_RD(address, 32);
philpem@59 588
philpem@59 589 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@59 590 // ROM access
philpem@60 591 return RD32(state.rom, address, ROM_SIZE - 1);
philpem@60 592 } else if (address <= 0x3fffff) {
philpem@59 593 // RAM access
philpem@60 594 uint32_t newAddr = mapAddr(address, false);
philpem@63 595 if (newAddr <= 0x1fffff) {
philpem@60 596 return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 597 } else {
philpem@63 598 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
philpem@63 599 return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 600 else
philpem@63 601 return 0xffffffff;
philpem@63 602 }
philpem@59 603 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@59 604 // I/O register space, zone A
philpem@59 605 switch (address & 0x0F0000) {
philpem@59 606 case 0x000000: // Map RAM access
philpem@59 607 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
philpem@60 608 return RD32(state.map, address, 0x7FF);
philpem@59 609 break;
philpem@59 610 case 0x020000: // Video RAM
philpem@59 611 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@60 612 return RD32(state.vram, address, 0x7FFF);
philpem@59 613 break;
philpem@59 614 default:
philpem@60 615 return IoRead(address, 32);
philpem@59 616 }
philpem@59 617 } else {
philpem@60 618 return IoRead(address, 32);
philpem@59 619 }
philpem@59 620
philpem@40 621 return data;
philpem@59 622 }/*}}}*/
philpem@40 623
philpem@40 624 /**
philpem@40 625 * @brief Read M68K memory, 16-bit
philpem@40 626 */
philpem@59 627 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
philpem@40 628 {
philpem@40 629 uint16_t data = 0xFFFF;
philpem@40 630
philpem@40 631 // If ROMLMAP is set, force system to access ROM
philpem@40 632 if (!state.romlmap)
philpem@40 633 address |= 0x800000;
philpem@40 634
philpem@40 635 // Check access permissions
philpem@40 636 ACCESS_CHECK_RD(address, 16);
philpem@40 637
philpem@40 638 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 639 // ROM access
philpem@40 640 data = RD16(state.rom, address, ROM_SIZE - 1);
philpem@60 641 } else if (address <= 0x3fffff) {
philpem@40 642 // RAM access
philpem@60 643 uint32_t newAddr = mapAddr(address, false);
philpem@63 644 if (newAddr <= 0x1fffff) {
philpem@60 645 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 646 } else {
philpem@63 647 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
philpem@63 648 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 649 else
philpem@63 650 return 0xffff;
philpem@63 651 }
philpem@40 652 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 653 // I/O register space, zone A
philpem@40 654 switch (address & 0x0F0000) {
philpem@40 655 case 0x000000: // Map RAM access
philpem@40 656 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 657 data = RD16(state.map, address, 0x7FF);
philpem@40 658 break;
philpem@40 659 case 0x020000: // Video RAM
philpem@40 660 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 661 data = RD16(state.vram, address, 0x7FFF);
philpem@40 662 break;
philpem@59 663 default:
philpem@59 664 data = IoRead(address, 16);
philpem@40 665 }
philpem@59 666 } else {
philpem@59 667 data = IoRead(address, 16);
philpem@40 668 }
philpem@40 669
philpem@40 670 return data;
philpem@59 671 }/*}}}*/
philpem@40 672
philpem@40 673 /**
philpem@40 674 * @brief Read M68K memory, 8-bit
philpem@40 675 */
philpem@59 676 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
philpem@40 677 {
philpem@40 678 uint8_t data = 0xFF;
philpem@40 679
philpem@40 680 // If ROMLMAP is set, force system to access ROM
philpem@40 681 if (!state.romlmap)
philpem@40 682 address |= 0x800000;
philpem@40 683
philpem@40 684 // Check access permissions
philpem@40 685 ACCESS_CHECK_RD(address, 8);
philpem@40 686
philpem@40 687 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 688 // ROM access
philpem@40 689 data = RD8(state.rom, address, ROM_SIZE - 1);
philpem@60 690 } else if (address <= 0x3fffff) {
philpem@40 691 // RAM access
philpem@60 692 uint32_t newAddr = mapAddr(address, false);
philpem@63 693 if (newAddr <= 0x1fffff) {
philpem@60 694 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 695 } else {
philpem@63 696 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
philpem@63 697 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 698 else
philpem@63 699 return 0xff;
philpem@63 700 }
philpem@40 701 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 702 // I/O register space, zone A
philpem@40 703 switch (address & 0x0F0000) {
philpem@40 704 case 0x000000: // Map RAM access
philpem@40 705 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 706 data = RD8(state.map, address, 0x7FF);
philpem@40 707 break;
philpem@40 708 case 0x020000: // Video RAM
philpem@40 709 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 710 data = RD8(state.vram, address, 0x7FFF);
philpem@40 711 break;
philpem@59 712 default:
philpem@59 713 data = IoRead(address, 8);
philpem@40 714 }
philpem@59 715 } else {
philpem@59 716 data = IoRead(address, 8);
philpem@40 717 }
philpem@40 718
philpem@40 719 return data;
philpem@59 720 }/*}}}*/
philpem@40 721
philpem@40 722 /**
philpem@40 723 * @brief Write M68K memory, 32-bit
philpem@40 724 */
philpem@59 725 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
philpem@40 726 {
philpem@40 727 // If ROMLMAP is set, force system to access ROM
philpem@40 728 if (!state.romlmap)
philpem@40 729 address |= 0x800000;
philpem@40 730
philpem@40 731 // Check access permissions
philpem@40 732 ACCESS_CHECK_WR(address, 32);
philpem@40 733
philpem@40 734 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 735 // ROM access
philpem@60 736 } else if (address <= 0x3FFFFF) {
philpem@40 737 // RAM access
philpem@60 738 uint32_t newAddr = mapAddr(address, true);
philpem@70 739 if (newAddr <= 0x1fffff)
philpem@60 740 WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@70 741 else
philpem@65 742 WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@40 743 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 744 // I/O register space, zone A
philpem@40 745 switch (address & 0x0F0000) {
philpem@40 746 case 0x000000: // Map RAM access
philpem@59 747 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 748 WR32(state.map, address, 0x7FF, value);
philpem@40 749 break;
philpem@40 750 case 0x020000: // Video RAM
philpem@59 751 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 752 WR32(state.vram, address, 0x7FFF, value);
philpem@40 753 break;
philpem@59 754 default:
philpem@59 755 IoWrite(address, value, 32);
philpem@40 756 }
philpem@59 757 } else {
philpem@59 758 IoWrite(address, value, 32);
philpem@40 759 }
philpem@59 760 }/*}}}*/
philpem@40 761
philpem@40 762 /**
philpem@40 763 * @brief Write M68K memory, 16-bit
philpem@40 764 */
philpem@59 765 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
philpem@40 766 {
philpem@40 767 // If ROMLMAP is set, force system to access ROM
philpem@40 768 if (!state.romlmap)
philpem@40 769 address |= 0x800000;
philpem@40 770
philpem@40 771 // Check access permissions
philpem@40 772 ACCESS_CHECK_WR(address, 16);
philpem@40 773
philpem@40 774 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 775 // ROM access
philpem@60 776 } else if (address <= 0x3FFFFF) {
philpem@40 777 // RAM access
philpem@60 778 uint32_t newAddr = mapAddr(address, true);
philpem@70 779 if (newAddr <= 0x1fffff)
philpem@60 780 WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@70 781 else
philpem@65 782 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@40 783 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 784 // I/O register space, zone A
philpem@40 785 switch (address & 0x0F0000) {
philpem@40 786 case 0x000000: // Map RAM access
philpem@40 787 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 788 WR16(state.map, address, 0x7FF, value);
philpem@40 789 break;
philpem@40 790 case 0x020000: // Video RAM
philpem@40 791 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 792 WR16(state.vram, address, 0x7FFF, value);
philpem@40 793 break;
philpem@59 794 default:
philpem@59 795 IoWrite(address, value, 16);
philpem@40 796 }
philpem@59 797 } else {
philpem@59 798 IoWrite(address, value, 16);
philpem@40 799 }
philpem@59 800 }/*}}}*/
philpem@40 801
philpem@40 802 /**
philpem@40 803 * @brief Write M68K memory, 8-bit
philpem@40 804 */
philpem@59 805 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
philpem@40 806 {
philpem@40 807 // If ROMLMAP is set, force system to access ROM
philpem@40 808 if (!state.romlmap)
philpem@40 809 address |= 0x800000;
philpem@40 810
philpem@40 811 // Check access permissions
philpem@40 812 ACCESS_CHECK_WR(address, 8);
philpem@40 813
philpem@40 814 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 815 // ROM access (read only!)
philpem@60 816 } else if (address <= 0x3FFFFF) {
philpem@40 817 // RAM access
philpem@60 818 uint32_t newAddr = mapAddr(address, true);
philpem@70 819 if (newAddr <= 0x1fffff)
philpem@60 820 WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@70 821 else
philpem@65 822 WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@40 823 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 824 // I/O register space, zone A
philpem@40 825 switch (address & 0x0F0000) {
philpem@40 826 case 0x000000: // Map RAM access
philpem@59 827 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 828 WR8(state.map, address, 0x7FF, value);
philpem@40 829 break;
philpem@40 830 case 0x020000: // Video RAM
philpem@59 831 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 832 WR8(state.vram, address, 0x7FFF, value);
philpem@40 833 break;
philpem@59 834 default:
philpem@59 835 IoWrite(address, value, 8);
philpem@40 836 }
philpem@59 837 } else {
philpem@59 838 IoWrite(address, value, 8);
philpem@40 839 }
philpem@59 840 }/*}}}*/
philpem@40 841
philpem@40 842
philpem@40 843 // for the disassembler
philpem@40 844 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
philpem@40 845 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
philpem@40 846 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }
philpem@40 847