src/memory.c

Fri, 12 Apr 2013 12:34:32 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Fri, 12 Apr 2013 12:34:32 +0100
branch
experimental_memory_mapper_v2
changeset 140
1e4c45b144c4
parent 133
84ed5ec1d1e0
child 141
8460d432606f
permissions
-rw-r--r--

Fix read-after-write logic

In some cases (notably reading from a page after having written to it), the
mapper may change the pagestate from "accessed and written" ("dirty"; PS0,PS1)
to "accessed but not written" (clean; PS1,!PS0). This should never, ever, EVER
happen. Once a page is dirty, it remains so until the 68k clears the DIRTY
bit.

Once again, this wonderful bit of logic was missing from the TRM.

philpem@40 1 #include <stdio.h>
philpem@40 2 #include <stdlib.h>
philpem@40 3 #include <stdint.h>
philpem@40 4 #include <stdbool.h>
philpem@59 5 #include <assert.h>
philpem@40 6 #include "musashi/m68k.h"
philpem@40 7 #include "state.h"
philpem@100 8 #include "utils.h"
philpem@40 9 #include "memory.h"
philpem@40 10
philpem@119 11 // The value which will be returned if the CPU attempts to read from empty memory
philpem@119 12 // TODO (FIXME?) - need to figure out if R/W ops wrap around. This seems to appease the UNIX kernel and P4TEST.
philpem@119 13 #define EMPTY 0xFFFFFFFFUL
philpem@129 14 //#define EMPTY 0x55555555UL
philpem@129 15 //#define EMPTY 0x00000000UL
philpem@119 16
philpem@40 17 /******************
philpem@40 18 * Memory mapping
philpem@40 19 ******************/
philpem@40 20
philpem@128 21 /// Set a page bit
philpem@133 22 #define MAP_SET_PAGEBIT(addr, bit) state.map[(MAP_ADDR_TO_PAGE(addr))*2] |= ((uint8_t)bit << 2)
philpem@128 23 /// Clear a page bit
philpem@133 24 #define MAP_CLR_PAGEBIT(addr, bit) state.map[(MAP_ADDR_TO_PAGE(addr))*2] &= ~((uint8_t)bit << 2)
philpem@40 25
philpem@40 26
philpem@40 27 /********************************************************
philpem@40 28 * m68k memory read/write support functions for Musashi
philpem@40 29 ********************************************************/
philpem@40 30
philpem@40 31 /**
philpem@40 32 * @brief Check memory access permissions for a write operation.
philpem@40 33 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
philpem@40 34 * gcc throws warnings when you have a return-with-value in a void
philpem@40 35 * function, even if the return-with-value is completely unreachable.
philpem@40 36 * Similarly it doesn't like it if you have a return without a value
philpem@40 37 * in a non-void function, even if it's impossible to ever reach the
philpem@40 38 * return-with-no-value. UGH!
philpem@40 39 */
philpem@59 40 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
philpem@59 41 #define ACCESS_CHECK_WR(address, bits) \
philpem@59 42 do { \
philpem@128 43 if (access_check_cpu(address, bits, true)) { \
philpem@40 44 return; \
philpem@40 45 } \
philpem@70 46 } while (0)
philpem@59 47 /*}}}*/
philpem@40 48
philpem@40 49 /**
philpem@40 50 * @brief Check memory access permissions for a read operation.
philpem@40 51 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
philpem@40 52 * gcc throws warnings when you have a return-with-value in a void
philpem@40 53 * function, even if the return-with-value is completely unreachable.
philpem@40 54 * Similarly it doesn't like it if you have a return without a value
philpem@40 55 * in a non-void function, even if it's impossible to ever reach the
philpem@40 56 * return-with-no-value. UGH!
philpem@40 57 */
philpem@59 58 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
philpem@59 59 #define ACCESS_CHECK_RD(address, bits) \
philpem@59 60 do { \
philpem@128 61 if (access_check_cpu(address, bits, false)) { \
philpem@128 62 if (bits == 32) \
philpem@128 63 return EMPTY & 0xFFFFFFFF; \
philpem@40 64 else \
philpem@128 65 return EMPTY & ((1UL << bits)-1); \
philpem@40 66 } \
philpem@70 67 } while (0)
philpem@59 68 /*}}}*/
philpem@40 69
philpem@128 70
philpem@128 71 /**
philpem@128 72 * Update the page bits for a given memory address
philpem@128 73 *
philpem@128 74 * @param addr Memory address being accessed
philpem@128 75 * @param l7intr Set to <i>true</i> if a level-seven interrupt has been
philpem@128 76 * signalled (even if <b>ENABLE ERROR</b> isn't set).
philpem@128 77 * @param write Set to <i>true</i> if the address is being written to.
philpem@128 78 */
philpem@128 79 static void update_page_bits(uint32_t addr, bool l7intr, bool write)
philpem@112 80 {
philpem@128 81 bool ps0_state = false;
philpem@128 82
philpem@128 83 // Don't try and update pagebits for non-RAM addresses
philpem@128 84 if (addr > 0x3FFFFF)
philpem@128 85 return;
philpem@128 86
philpem@128 87 if (l7intr) {
philpem@128 88 // if (!(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
philpem@128 89 // FIXME FUCKUP The ruddy TRM is wrong AGAIN! If above line is uncommented, Really Bad Things Happen.
philpem@128 90 if ((MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
philpem@128 91 // Level 7 interrupt, PS0 clear, PS1 don't-care. Set PS0.
philpem@128 92 ps0_state = true;
philpem@128 93 }
philpem@128 94 } else {
philpem@128 95 // No L7 interrupt
philpem@128 96 if ((write && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && (MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) ||
philpem@140 97 (write && (MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) ||
philpem@140 98 ( (MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && (MAP_PAGEBITS(addr) & PAGE_BIT_PS0))) /* NOTE -- Once again, this case was missing from the PAL equations in the TRM... */
philpem@128 99 {
philpem@128 100 // No L7 interrupt, PS[1:0] = 0b01, write
philpem@128 101 // No L7 interrupt, PS[1:0] = 0b10, write
philpem@128 102 ps0_state = true;
philpem@128 103 }
philpem@128 104 }
philpem@112 105
philpem@128 106 #ifdef MAPRAM_BIT_TEST
philpem@128 107 LOG("Starting Mapram Bit Test");
philpem@128 108 state.map[0] = state.map[1] = 0;
philpem@128 109 LOG("Start = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 110 MAP_SET_PAGEBIT(0, PAGE_BIT_WE);
philpem@128 111 LOG("Set WE = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 112 MAP_SET_PAGEBIT(0, PAGE_BIT_PS1);
philpem@128 113 LOG("Set PS1 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 114 MAP_SET_PAGEBIT(0, PAGE_BIT_PS0);
philpem@128 115 LOG("Set PS0 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 116
philpem@128 117 MAP_CLR_PAGEBIT(0, PAGE_BIT_WE);
philpem@128 118 LOG("Clr WE = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 119 MAP_CLR_PAGEBIT(0, PAGE_BIT_PS1);
philpem@128 120 LOG("Clr PS1 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 121 MAP_CLR_PAGEBIT(0, PAGE_BIT_PS0);
philpem@128 122 LOG("Clr PS0 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 123 exit(-1);
philpem@128 124 #endif
philpem@128 125
philpem@128 126 uint16_t old_pagebits = MAP_PAGEBITS(addr);
philpem@112 127
philpem@128 128 // PS1 is always set on access
philpem@128 129 MAP_SET_PAGEBIT(addr, PAGE_BIT_PS1);
philpem@128 130
philpem@128 131 uint16_t new_pagebit1 = MAP_PAGEBITS(addr);
philpem@128 132
philpem@128 133 // Update PS0
philpem@128 134 if (ps0_state) {
philpem@128 135 MAP_SET_PAGEBIT(addr, PAGE_BIT_PS0);
philpem@128 136 } else {
philpem@128 137 MAP_CLR_PAGEBIT(addr, PAGE_BIT_PS0);
philpem@128 138 }
philpem@112 139
philpem@128 140 uint16_t new_pagebit2 = MAP_PAGEBITS(addr);
philpem@128 141 switch (addr) {
philpem@128 142 case 0x000000:
philpem@128 143 case 0x001000:
philpem@128 144 case 0x002000:
philpem@128 145 case 0x003000:
philpem@128 146 case 0x004000:
philpem@128 147 case 0x033000:
philpem@128 148 case 0x034000:
philpem@128 149 case 0x035000:
philpem@128 150 LOG("Addr %08X MapNew %04X Pagebit update -- ps0 %d, %02X => %02X => %02X", addr, MAPRAM_ADDR(addr), ps0_state, old_pagebits, new_pagebit1, new_pagebit2);
philpem@128 151 default:
philpem@112 152 break;
philpem@112 153 }
philpem@128 154 }
philpem@128 155
philpem@128 156 bool access_check_dma(void)
philpem@128 157 {
philpem@128 158 // TODO FIXME BUGBUG Sanity check - Make sure DMAC is only accessing RAM addresses
philpem@128 159
philpem@128 160 // DMA access check -- make sure the page is mapped in
philpem@128 161 if (!(MAP_PAGEBITS(state.dma_address) & PAGE_BIT_PS0) && !(MAP_PAGEBITS(state.dma_address) & PAGE_BIT_PS1)) {
philpem@128 162 // DMA access to page which is not mapped in.
philpem@128 163 // Level 7 interrupt, page fault, DMA invoked
philpem@128 164 state.genstat = 0xABFF
philpem@128 165 | (state.dma_reading ? 0x4000 : 0)
philpem@128 166 | (state.pie ? 0x0400 : 0);
philpem@128 167
philpem@128 168 // XXX: Check all this stuff.
philpem@112 169 state.bsr0 = 0x3C00;
philpem@112 170 state.bsr0 |= (state.dma_address >> 16);
philpem@112 171 state.bsr1 = state.dma_address & 0xffff;
philpem@128 172
philpem@128 173 // Update page bits for this transfer
philpem@128 174 update_page_bits(state.dma_address, true, !state.dma_reading);
philpem@128 175
philpem@128 176 // XXX: is this right?
philpem@128 177 // Fire a Level 7 interrupt
philpem@128 178 /*if (state.ee)*/ m68k_set_irq(7);
philpem@128 179
philpem@128 180 LOG("BUS ERROR FROM DMA: genstat=%04X, bsr0=%04X, bsr1=%04X\n", state.genstat, state.bsr0, state.bsr1);
philpem@128 181 return false;
philpem@128 182 } else {
philpem@128 183 // No errors. Just update the page bits.
philpem@128 184 update_page_bits(state.dma_address, false, !state.dma_reading);
philpem@128 185 return true;
philpem@112 186 }
philpem@128 187 }
philpem@128 188
philpem@128 189 /**
philpem@128 190 * Check memory access permissions for a CPU memory access.
philpem@128 191 *
philpem@128 192 * @param addr Virtual memory address being accessed (from CPU address bus).
philpem@128 193 * @param bits Word size of this transfer (8, 16 or 32 bits).
philpem@128 194 * @param write <i>true</i> if this is a write operation, <i>false</i> if it is a read operation.
philpem@128 195 * @return <i>true</i> if the access was denied and a level-7 interrupt and/or bus error raised.
philpem@128 196 * <i>false</i> if the access was allowed.
philpem@128 197 */
philpem@128 198 bool access_check_cpu(uint32_t addr, int bits, bool write)
philpem@128 199 {
philpem@128 200 bool supervisor = (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000);
philpem@128 201 bool fault = false;
philpem@128 202
philpem@128 203 // TODO FIXME BUGBUG? Do we need to check for supervisor access here?
philpem@128 204 if ((addr >= 0x000000) && (addr <= 0x3FFFFF) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
philpem@128 205 // (A) Page Fault -- user access to page which is not mapped in
philpem@128 206 // Level 7 Interrupt, Bus Error, regs=PAGEFAULT
philpem@128 207 if (write) {
philpem@128 208 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0);
philpem@128 209 } else {
philpem@128 210 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0);
philpem@128 211 }
philpem@128 212 fault = true;
philpem@128 213 } else if (!supervisor && (addr >= 0x000000) && (addr <= 0x07FFFF)) {
philpem@128 214 // (B) User attempted to access the kernel
philpem@128 215 // Level 7 Interrupt, Bus Error, regs=KERNEL
philpem@128 216 if (write) {
philpem@128 217 // XXX: BUGBUG? Is this correct?
philpem@128 218 state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0);
philpem@128 219 } else {
philpem@128 220 state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0);
philpem@128 221 }
philpem@128 222 fault = true;
philpem@128 223 } else if (!supervisor && write && (addr >= 0x000000) && (addr <= 0x3FFFFF) && !(MAP_PAGEBITS(addr) & PAGE_BIT_WE)) {
philpem@128 224 // (C) User attempted to write to a page which is not write enabled
philpem@128 225 // Level 7 Interrupt, Bus Error, regs=WRITE_EN
philpem@128 226 if (write) {
philpem@128 227 // XXX: BUGBUG? Is this correct?
philpem@128 228 state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0);
philpem@128 229 } else {
philpem@128 230 state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0);
philpem@128 231 }
philpem@128 232 fault = true;
philpem@128 233 } else if (!supervisor && (addr >= 0x400000) && (addr <= 0xFFFFFF)) {
philpem@128 234 // (D) UIE - user I/O exception
philpem@128 235 // Bus Error only, regs=UIE
philpem@128 236 if (write) {
philpem@128 237 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0);
philpem@128 238 } else {
philpem@128 239 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0);
philpem@128 240 }
philpem@128 241 fault = true;
philpem@128 242 }
philpem@128 243
philpem@128 244 // Update the page bits first
philpem@128 245 update_page_bits(addr, fault, write);
philpem@128 246
philpem@128 247 if (fault) {
philpem@128 248 if (bits >= 16)
philpem@128 249 state.bsr0 = 0x7C00;
philpem@128 250 else
philpem@128 251 state.bsr0 = (addr & 1) ? 0x7E00 : 0x7D00;
philpem@128 252 // FIXME? Physical or virtual address here?
philpem@128 253 state.bsr0 |= (addr >> 16);
philpem@128 254 state.bsr1 = addr & 0xffff;
philpem@128 255
philpem@128 256 LOG("CPU Bus Error or L7Intr while %s, vaddr %08X, map %08X, pagebits 0x%02X bsr0=%04X bsr1=%04X genstat=%04X",
philpem@128 257 write ? "writing" : "reading", addr,
philpem@128 258 MAPRAM_ADDR(addr & 0x3fffff),
philpem@128 259 MAP_PAGEBITS(addr & 0x3fffff),
philpem@128 260 state.bsr0, state.bsr1, state.genstat);
philpem@128 261
philpem@128 262 // FIXME? BUGBUG? Does EE disable one or both of these?
philpem@128 263 // /*if (state.ee)*/ m68k_set_irq(7);
philpem@128 264 /*if (state.ee)*/ m68k_pulse_bus_error();
philpem@128 265 }
philpem@128 266
philpem@128 267 return fault;
philpem@112 268 }
philpem@112 269
philpem@40 270 // Logging macros
philpem@59 271 #define LOG_NOT_HANDLED_R(bits) \
philpem@128 272 if (!handled) fprintf(stderr, "unhandled read%02d, addr=0x%08X\n", bits, address);
philpem@40 273
philpem@59 274 #define LOG_NOT_HANDLED_W(bits) \
philpem@128 275 if (!handled) fprintf(stderr, "unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
philpem@59 276
philpem@59 277 /********************************************************
philpem@59 278 * I/O read/write functions
philpem@59 279 ********************************************************/
philpem@40 280
philpem@40 281 /**
philpem@59 282 * Issue a warning if a read operation is made with an invalid size
philpem@40 283 */
philpem@66 284 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
philpem@40 285 {
philpem@59 286 assert((bits == 8) || (bits == 16) || (bits == 32));
philpem@59 287 if ((bits & allowed) == 0) {
philpem@128 288 LOG("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
philpem@59 289 }
philpem@59 290 }
philpem@59 291
philpem@66 292 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
philpem@40 293 {
philpem@66 294 ENFORCE_SIZE(bits, address, true, allowed, regname);
philpem@66 295 }
philpem@66 296
philpem@66 297 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
philpem@66 298 {
philpem@66 299 ENFORCE_SIZE(bits, address, false, allowed, regname);
philpem@66 300 }
philpem@66 301
philpem@59 302 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
philpem@59 303 {
philpem@40 304 bool handled = false;
philpem@40 305
philpem@59 306 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 307 // I/O register space, zone A
philpem@40 308 switch (address & 0x0F0000) {
philpem@40 309 case 0x010000: // General Status Register
philpem@59 310 if (bits == 16)
philpem@59 311 state.genstat = (data & 0xffff);
philpem@59 312 else if (bits == 8) {
philpem@59 313 if (address & 0)
philpem@59 314 state.genstat = data;
philpem@59 315 else
philpem@59 316 state.genstat = data << 8;
philpem@59 317 }
philpem@40 318 handled = true;
philpem@40 319 break;
philpem@40 320 case 0x030000: // Bus Status Register 0
philpem@40 321 break;
philpem@40 322 case 0x040000: // Bus Status Register 1
philpem@40 323 break;
philpem@40 324 case 0x050000: // Phone status
philpem@40 325 break;
philpem@40 326 case 0x060000: // DMA Count
philpem@66 327 ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
philpem@59 328 state.dma_count = (data & 0x3FFF);
philpem@59 329 state.idmarw = ((data & 0x4000) == 0x4000);
philpem@59 330 state.dmaen = ((data & 0x8000) == 0x8000);
philpem@59 331 // This handles the "dummy DMA transfer" mentioned in the docs
philpem@112 332 // disabled because it causes the floppy test to fail
philpem@112 333 #if 0
philpem@112 334 if (!state.idmarw){
philpem@112 335 if (access_check_dma(true)){
philpem@112 336 uint32_t newAddr = mapAddr(state.dma_address, true);
philpem@112 337 // RAM access
philpem@112 338 if (newAddr <= 0x1fffff)
philpem@112 339 WR16(state.base_ram, newAddr, state.base_ram_size - 1, 0xFF);
philpem@112 340 else if (address <= 0x3FFFFF)
philpem@112 341 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, 0xFF);
philpem@112 342 }
philpem@112 343 }
philpem@112 344 #endif
philpem@59 345 state.dma_count++;
philpem@53 346 handled = true;
philpem@40 347 break;
philpem@40 348 case 0x070000: // Line Printer Status Register
philpem@40 349 break;
philpem@40 350 case 0x080000: // Real Time Clock
philpem@128 351 LOGS("REAL TIME CLOCK WRITE");
philpem@40 352 break;
philpem@40 353 case 0x090000: // Phone registers
philpem@40 354 switch (address & 0x0FF000) {
philpem@40 355 case 0x090000: // Handset relay
philpem@40 356 case 0x098000:
philpem@40 357 break;
philpem@40 358 case 0x091000: // Line select 2
philpem@40 359 case 0x099000:
philpem@40 360 break;
philpem@40 361 case 0x092000: // Hook relay 1
philpem@40 362 case 0x09A000:
philpem@40 363 break;
philpem@40 364 case 0x093000: // Hook relay 2
philpem@40 365 case 0x09B000:
philpem@40 366 break;
philpem@40 367 case 0x094000: // Line 1 hold
philpem@40 368 case 0x09C000:
philpem@40 369 break;
philpem@40 370 case 0x095000: // Line 2 hold
philpem@40 371 case 0x09D000:
philpem@40 372 break;
philpem@40 373 case 0x096000: // Line 1 A-lead
philpem@40 374 case 0x09E000:
philpem@40 375 break;
philpem@40 376 case 0x097000: // Line 2 A-lead
philpem@40 377 case 0x09F000:
philpem@40 378 break;
philpem@40 379 }
philpem@40 380 break;
philpem@59 381 case 0x0A0000: // Miscellaneous Control Register
philpem@66 382 ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
philpem@59 383 // TODO: handle the ctrl bits properly
philpem@97 384 if (data & 0x8000){
philpem@97 385 state.timer_enabled = 1;
philpem@97 386 }else{
philpem@97 387 state.timer_enabled = 0;
philpem@97 388 state.timer_asserted = 0;
philpem@97 389 }
philpem@59 390 state.dma_reading = (data & 0x4000);
philpem@72 391 if (state.leds != ((~data & 0xF00) >> 8)) {
philpem@72 392 state.leds = (~data & 0xF00) >> 8;
philpem@117 393 #ifdef SHOW_LEDS
philpem@72 394 printf("LEDs: %s %s %s %s\n",
philpem@72 395 (state.leds & 8) ? "R" : "-",
philpem@72 396 (state.leds & 4) ? "G" : "-",
philpem@72 397 (state.leds & 2) ? "Y" : "-",
philpem@72 398 (state.leds & 1) ? "R" : "-");
philpem@117 399 #endif
philpem@72 400 }
philpem@46 401 handled = true;
philpem@40 402 break;
philpem@40 403 case 0x0B0000: // TM/DIALWR
philpem@40 404 break;
philpem@59 405 case 0x0C0000: // Clear Status Register
philpem@59 406 state.genstat = 0xFFFF;
philpem@59 407 state.bsr0 = 0xFFFF;
philpem@59 408 state.bsr1 = 0xFFFF;
philpem@43 409 handled = true;
philpem@40 410 break;
philpem@40 411 case 0x0D0000: // DMA Address Register
philpem@59 412 if (address & 0x004000) {
philpem@59 413 // A14 high -- set most significant bits
philpem@59 414 state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
philpem@59 415 } else {
philpem@59 416 // A14 low -- set least significant bits
philpem@59 417 state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
philpem@59 418 }
philpem@59 419 handled = true;
philpem@40 420 break;
philpem@40 421 case 0x0E0000: // Disk Control Register
philpem@112 422 {
philpem@112 423 bool fd_selected;
philpem@112 424 bool hd_selected;
philpem@112 425 ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
philpem@112 426 // B7 = FDD controller reset
philpem@112 427 if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
philpem@112 428 // B6 = drive 0 select
philpem@112 429 fd_selected = (data & 0x40) != 0;
philpem@112 430 // B5 = motor enable -- TODO
philpem@112 431 // B4 = HDD controller reset
philpem@112 432 if ((data & 0x10) == 0) wd2010_reset(&state.hdc_ctx);
philpem@112 433 // B3 = HDD0 select
philpem@112 434 hd_selected = (data & 0x08) != 0;
philpem@112 435 // B2,1,0 = HDD0 head select -- TODO?
philpem@112 436 if (hd_selected && !state.hd_selected){
philpem@112 437 state.fd_selected = false;
philpem@112 438 state.hd_selected = true;
philpem@112 439 }else if (fd_selected && !state.fd_selected){
philpem@112 440 state.hd_selected = false;
philpem@112 441 state.fd_selected = true;
philpem@112 442 }
philpem@112 443 handled = true;
philpem@112 444 break;
philpem@112 445 }
philpem@40 446 case 0x0F0000: // Line Printer Data Register
philpem@40 447 break;
philpem@40 448 }
philpem@40 449 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 450 // I/O register space, zone B
philpem@40 451 switch (address & 0xF00000) {
philpem@40 452 case 0xC00000: // Expansion slots
philpem@40 453 case 0xD00000:
philpem@40 454 switch (address & 0xFC0000) {
philpem@40 455 case 0xC00000: // Expansion slot 0
philpem@40 456 case 0xC40000: // Expansion slot 1
philpem@40 457 case 0xC80000: // Expansion slot 2
philpem@40 458 case 0xCC0000: // Expansion slot 3
philpem@40 459 case 0xD00000: // Expansion slot 4
philpem@40 460 case 0xD40000: // Expansion slot 5
philpem@40 461 case 0xD80000: // Expansion slot 6
philpem@40 462 case 0xDC0000: // Expansion slot 7
philpem@59 463 fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
philpem@59 464 handled = true;
philpem@40 465 break;
philpem@40 466 }
philpem@40 467 break;
philpem@40 468 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 469 case 0xF00000:
philpem@40 470 switch (address & 0x070000) {
philpem@112 471 case 0x000000: // [ef][08]xxxx ==> WD2010 hard disc controller
philpem@112 472 wd2010_write_reg(&state.hdc_ctx, (address >> 1) & 7, data);
philpem@112 473 handled = true;
philpem@40 474 break;
philpem@40 475 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@112 476 /*ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");*/
philpem@59 477 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
philpem@52 478 handled = true;
philpem@40 479 break;
philpem@40 480 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@116 481 // MCR2 - UNIX PC Rev. P5.1 HDD head select b3 and potential HDD#2 select
philpem@116 482 wd2010_write_reg(&state.hdc_ctx, UNIXPC_REG_MCR2, data);
philpem@116 483 handled = true;
philpem@40 484 break;
philpem@40 485 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@128 486 LOGS("REAL TIME CLOCK DATA WRITE");
philpem@40 487 break;
philpem@40 488 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 489 switch (address & 0x077000) {
philpem@40 490 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@102 491 // Error Enable. If =0, Level7 intrs and bus errors are masked.
philpem@102 492 ENFORCE_SIZE_W(bits, address, 16, "EE");
philpem@102 493 state.ee = ((data & 0x8000) == 0x8000);
philpem@102 494 handled = true;
philpem@59 495 break;
philpem@44 496 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@66 497 ENFORCE_SIZE_W(bits, address, 16, "PIE");
philpem@59 498 state.pie = ((data & 0x8000) == 0x8000);
philpem@59 499 handled = true;
philpem@59 500 break;
philpem@40 501 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@59 502 break;
philpem@40 503 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@66 504 ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
philpem@59 505 state.romlmap = ((data & 0x8000) == 0x8000);
philpem@44 506 handled = true;
philpem@40 507 break;
philpem@59 508 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@66 509 ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
philpem@59 510 break;
philpem@59 511 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@66 512 ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
philpem@59 513 break;
philpem@59 514 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@66 515 ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
philpem@59 516 break;
philpem@59 517 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@66 518 ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
philpem@40 519 break;
philpem@40 520 }
philpem@40 521 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 522 break;
philpem@40 523 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 524 switch (address & 0x07F000) {
philpem@40 525 default:
philpem@40 526 break;
philpem@40 527 }
philpem@40 528 break;
philpem@40 529 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@84 530 // TODO: figure out which sizes are valid (probably just 8 and 16)
philpem@84 531 // ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER");
philpem@93 532 if (bits == 8) {
philpem@128 533 #ifdef LOG_KEYBOARD_WRITES
philpem@128 534 LOG("KBD WR %02X => %02X\n", (address >> 1) & 3, data);
philpem@128 535 #endif
philpem@93 536 keyboard_write(&state.kbd, (address >> 1) & 3, data);
philpem@93 537 handled = true;
philpem@93 538 } else if (bits == 16) {
philpem@128 539 #ifdef LOG_KEYBOARD_WRITES
philpem@128 540 LOG("KBD WR %02X => %04X\n", (address >> 1) & 3, data);
philpem@128 541 #endif
philpem@93 542 keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8);
philpem@93 543 handled = true;
philpem@93 544 }
philpem@40 545 break;
philpem@40 546 }
philpem@40 547 }
philpem@40 548 }
philpem@40 549
philpem@64 550 LOG_NOT_HANDLED_W(bits);
philpem@59 551 }/*}}}*/
philpem@40 552
philpem@59 553 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
philpem@59 554 {
philpem@59 555 bool handled = false;
philpem@119 556 uint32_t data = EMPTY & 0xFFFFFFFF;
philpem@40 557
philpem@59 558 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 559 // I/O register space, zone A
philpem@40 560 switch (address & 0x0F0000) {
philpem@40 561 case 0x010000: // General Status Register
philpem@116 562 /* ENFORCE_SIZE_R(bits, address, 16, "GENSTAT"); */
philpem@116 563 if (bits == 32) {
philpem@116 564 return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
philpem@116 565 } else if (bits == 16) {
philpem@116 566 return (uint16_t)state.genstat;
philpem@116 567 } else {
philpem@116 568 return (uint8_t)(state.genstat & 0xff);
philpem@116 569 }
philpem@40 570 break;
philpem@40 571 case 0x030000: // Bus Status Register 0
philpem@66 572 ENFORCE_SIZE_R(bits, address, 16, "BSR0");
philpem@59 573 return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
philpem@40 574 break;
philpem@40 575 case 0x040000: // Bus Status Register 1
philpem@66 576 ENFORCE_SIZE_R(bits, address, 16, "BSR1");
philpem@59 577 return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
philpem@40 578 break;
philpem@40 579 case 0x050000: // Phone status
philpem@66 580 ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
philpem@40 581 break;
philpem@40 582 case 0x060000: // DMA Count
philpem@55 583 // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
philpem@55 584 // Bit 14 is always unused, so leave it set
philpem@66 585 ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
philpem@59 586 return (state.dma_count & 0x3fff) | 0xC000;
philpem@40 587 break;
philpem@40 588 case 0x070000: // Line Printer Status Register
philpem@53 589 data = 0x00120012; // no parity error, no line printer error, no irqs from FDD or HDD
philpem@78 590 data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0;
philpem@112 591 data |= wd2010_get_irq(&state.hdc_ctx) ? 0x00040004 : 0;
philpem@59 592 return data;
philpem@40 593 break;
philpem@40 594 case 0x080000: // Real Time Clock
philpem@128 595 LOGS("REAL TIME CLOCK READ");
philpem@40 596 break;
philpem@40 597 case 0x090000: // Phone registers
philpem@40 598 switch (address & 0x0FF000) {
philpem@40 599 case 0x090000: // Handset relay
philpem@40 600 case 0x098000:
philpem@40 601 break;
philpem@40 602 case 0x091000: // Line select 2
philpem@40 603 case 0x099000:
philpem@40 604 break;
philpem@40 605 case 0x092000: // Hook relay 1
philpem@40 606 case 0x09A000:
philpem@40 607 break;
philpem@40 608 case 0x093000: // Hook relay 2
philpem@40 609 case 0x09B000:
philpem@40 610 break;
philpem@40 611 case 0x094000: // Line 1 hold
philpem@40 612 case 0x09C000:
philpem@40 613 break;
philpem@40 614 case 0x095000: // Line 2 hold
philpem@40 615 case 0x09D000:
philpem@40 616 break;
philpem@40 617 case 0x096000: // Line 1 A-lead
philpem@40 618 case 0x09E000:
philpem@40 619 break;
philpem@40 620 case 0x097000: // Line 2 A-lead
philpem@40 621 case 0x09F000:
philpem@40 622 break;
philpem@40 623 }
philpem@40 624 break;
philpem@46 625 case 0x0A0000: // Miscellaneous Control Register -- write only!
philpem@46 626 handled = true;
philpem@40 627 break;
philpem@40 628 case 0x0B0000: // TM/DIALWR
philpem@40 629 break;
philpem@46 630 case 0x0C0000: // Clear Status Register -- write only!
philpem@43 631 handled = true;
philpem@40 632 break;
philpem@40 633 case 0x0D0000: // DMA Address Register
philpem@40 634 break;
philpem@40 635 case 0x0E0000: // Disk Control Register
philpem@40 636 break;
philpem@40 637 case 0x0F0000: // Line Printer Data Register
philpem@40 638 break;
philpem@40 639 }
philpem@40 640 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 641 // I/O register space, zone B
philpem@40 642 switch (address & 0xF00000) {
philpem@40 643 case 0xC00000: // Expansion slots
philpem@40 644 case 0xD00000:
philpem@40 645 switch (address & 0xFC0000) {
philpem@40 646 case 0xC00000: // Expansion slot 0
philpem@40 647 case 0xC40000: // Expansion slot 1
philpem@40 648 case 0xC80000: // Expansion slot 2
philpem@40 649 case 0xCC0000: // Expansion slot 3
philpem@40 650 case 0xD00000: // Expansion slot 4
philpem@40 651 case 0xD40000: // Expansion slot 5
philpem@40 652 case 0xD80000: // Expansion slot 6
philpem@40 653 case 0xDC0000: // Expansion slot 7
philpem@65 654 fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
philpem@65 655 handled = true;
philpem@40 656 break;
philpem@40 657 }
philpem@40 658 break;
philpem@40 659 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 660 case 0xF00000:
philpem@40 661 switch (address & 0x070000) {
philpem@40 662 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@112 663 return (wd2010_read_reg(&state.hdc_ctx, (address >> 1) & 7));
philpem@112 664
philpem@40 665 break;
philpem@40 666 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@112 667 /*ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");*/
philpem@59 668 return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
philpem@40 669 break;
philpem@40 670 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 671 break;
philpem@40 672 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@128 673 LOGS("REAL TIME CLOCK DATA READ");
philpem@40 674 break;
philpem@40 675 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 676 switch (address & 0x077000) {
philpem@40 677 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@44 678 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@40 679 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 680 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@40 681 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@40 682 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@40 683 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@44 684 // All write-only registers... TODO: bus error?
philpem@44 685 handled = true;
philpem@40 686 break;
philpem@44 687 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
philpem@40 688 break;
philpem@40 689 }
philpem@40 690 break;
philpem@40 691 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 692 break;
philpem@40 693 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 694 switch (address & 0x07F000) {
philpem@40 695 default:
philpem@40 696 break;
philpem@40 697 }
philpem@40 698 break;
philpem@40 699 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@84 700 // TODO: figure out which sizes are valid (probably just 8 and 16)
philpem@84 701 //ENFORCE_SIZE_R(bits, address, 16, "KEYBOARD CONTROLLER");
philpem@84 702 {
philpem@93 703 if (bits == 8) {
philpem@93 704 return keyboard_read(&state.kbd, (address >> 1) & 3);
philpem@93 705 } else {
philpem@93 706 return keyboard_read(&state.kbd, (address >> 1) & 3) << 8;
philpem@93 707 }
philpem@84 708 return data;
philpem@84 709 }
philpem@40 710 break;
philpem@40 711 }
philpem@40 712 }
philpem@40 713 }
philpem@40 714
philpem@64 715 LOG_NOT_HANDLED_R(bits);
philpem@64 716
philpem@59 717 return data;
philpem@59 718 }/*}}}*/
philpem@40 719
philpem@59 720
philpem@59 721 /********************************************************
philpem@59 722 * m68k memory read/write support functions for Musashi
philpem@59 723 ********************************************************/
philpem@59 724
philpem@59 725 /**
philpem@59 726 * @brief Read M68K memory, 32-bit
philpem@59 727 */
philpem@59 728 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
philpem@59 729 {
philpem@119 730 uint32_t data = EMPTY & 0xFFFFFFFF;
philpem@59 731
philpem@59 732 // If ROMLMAP is set, force system to access ROM
philpem@59 733 if (!state.romlmap)
philpem@59 734 address |= 0x800000;
philpem@59 735
philpem@59 736 // Check access permissions
philpem@59 737 ACCESS_CHECK_RD(address, 32);
philpem@59 738
philpem@59 739 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@59 740 // ROM access
philpem@60 741 return RD32(state.rom, address, ROM_SIZE - 1);
philpem@60 742 } else if (address <= 0x3fffff) {
philpem@59 743 // RAM access
philpem@128 744 uint32_t newAddr = MAP_ADDR(address);
philpem@128 745
philpem@63 746 if (newAddr <= 0x1fffff) {
philpem@129 747 // Base memory wraps around
philpem@129 748 return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 749 } else {
philpem@119 750 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@63 751 return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 752 else
philpem@119 753 return EMPTY & 0xffffffff;
philpem@63 754 }
philpem@59 755 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@59 756 // I/O register space, zone A
philpem@59 757 switch (address & 0x0F0000) {
philpem@59 758 case 0x000000: // Map RAM access
philpem@59 759 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
philpem@60 760 return RD32(state.map, address, 0x7FF);
philpem@59 761 break;
philpem@59 762 case 0x020000: // Video RAM
philpem@59 763 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@60 764 return RD32(state.vram, address, 0x7FFF);
philpem@59 765 break;
philpem@59 766 default:
philpem@60 767 return IoRead(address, 32);
philpem@59 768 }
philpem@59 769 } else {
philpem@60 770 return IoRead(address, 32);
philpem@59 771 }
philpem@59 772
philpem@40 773 return data;
philpem@59 774 }/*}}}*/
philpem@40 775
philpem@40 776 /**
philpem@40 777 * @brief Read M68K memory, 16-bit
philpem@40 778 */
philpem@59 779 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
philpem@40 780 {
philpem@119 781 uint16_t data = EMPTY & 0xFFFF;
philpem@40 782
philpem@40 783 // If ROMLMAP is set, force system to access ROM
philpem@40 784 if (!state.romlmap)
philpem@40 785 address |= 0x800000;
philpem@40 786
philpem@40 787 // Check access permissions
philpem@40 788 ACCESS_CHECK_RD(address, 16);
philpem@40 789
philpem@40 790 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 791 // ROM access
philpem@40 792 data = RD16(state.rom, address, ROM_SIZE - 1);
philpem@60 793 } else if (address <= 0x3fffff) {
philpem@40 794 // RAM access
philpem@128 795 uint32_t newAddr = MAP_ADDR(address);
philpem@128 796
philpem@63 797 if (newAddr <= 0x1fffff) {
philpem@129 798 // Base memory wraps around
philpem@129 799 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 800 } else {
philpem@119 801 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@63 802 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 803 else
philpem@119 804 return EMPTY & 0xffff;
philpem@63 805 }
philpem@40 806 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 807 // I/O register space, zone A
philpem@40 808 switch (address & 0x0F0000) {
philpem@40 809 case 0x000000: // Map RAM access
philpem@40 810 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 811 data = RD16(state.map, address, 0x7FF);
philpem@40 812 break;
philpem@40 813 case 0x020000: // Video RAM
philpem@40 814 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 815 data = RD16(state.vram, address, 0x7FFF);
philpem@40 816 break;
philpem@59 817 default:
philpem@59 818 data = IoRead(address, 16);
philpem@40 819 }
philpem@59 820 } else {
philpem@59 821 data = IoRead(address, 16);
philpem@40 822 }
philpem@40 823
philpem@40 824 return data;
philpem@59 825 }/*}}}*/
philpem@40 826
philpem@40 827 /**
philpem@40 828 * @brief Read M68K memory, 8-bit
philpem@40 829 */
philpem@59 830 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
philpem@40 831 {
philpem@119 832 uint8_t data = EMPTY & 0xFF;
philpem@40 833
philpem@40 834 // If ROMLMAP is set, force system to access ROM
philpem@40 835 if (!state.romlmap)
philpem@40 836 address |= 0x800000;
philpem@40 837
philpem@40 838 // Check access permissions
philpem@40 839 ACCESS_CHECK_RD(address, 8);
philpem@40 840
philpem@40 841 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 842 // ROM access
philpem@40 843 data = RD8(state.rom, address, ROM_SIZE - 1);
philpem@60 844 } else if (address <= 0x3fffff) {
philpem@40 845 // RAM access
philpem@128 846 uint32_t newAddr = MAP_ADDR(address);
philpem@128 847
philpem@63 848 if (newAddr <= 0x1fffff) {
philpem@129 849 // Base memory wraps around
philpem@129 850 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 851 } else {
philpem@119 852 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@63 853 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 854 else
philpem@119 855 return EMPTY & 0xff;
philpem@63 856 }
philpem@40 857 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 858 // I/O register space, zone A
philpem@40 859 switch (address & 0x0F0000) {
philpem@40 860 case 0x000000: // Map RAM access
philpem@40 861 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 862 data = RD8(state.map, address, 0x7FF);
philpem@40 863 break;
philpem@40 864 case 0x020000: // Video RAM
philpem@40 865 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 866 data = RD8(state.vram, address, 0x7FFF);
philpem@40 867 break;
philpem@59 868 default:
philpem@59 869 data = IoRead(address, 8);
philpem@40 870 }
philpem@59 871 } else {
philpem@59 872 data = IoRead(address, 8);
philpem@40 873 }
philpem@40 874
philpem@40 875 return data;
philpem@59 876 }/*}}}*/
philpem@40 877
philpem@40 878 /**
philpem@40 879 * @brief Write M68K memory, 32-bit
philpem@40 880 */
philpem@59 881 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
philpem@40 882 {
philpem@40 883 // If ROMLMAP is set, force system to access ROM
philpem@40 884 if (!state.romlmap)
philpem@40 885 address |= 0x800000;
philpem@40 886
philpem@40 887 // Check access permissions
philpem@40 888 ACCESS_CHECK_WR(address, 32);
philpem@40 889
philpem@40 890 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 891 // ROM access
philpem@60 892 } else if (address <= 0x3FFFFF) {
philpem@40 893 // RAM access
philpem@128 894 uint32_t newAddr = MAP_ADDR(address);
philpem@128 895
philpem@119 896 if (newAddr <= 0x1fffff) {
philpem@119 897 if (newAddr < state.base_ram_size) {
philpem@119 898 WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@119 899 }
philpem@119 900 } else {
philpem@119 901 if ((newAddr - 0x200000) < state.exp_ram_size) {
philpem@119 902 WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@119 903 }
philpem@119 904 }
philpem@40 905 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 906 // I/O register space, zone A
philpem@40 907 switch (address & 0x0F0000) {
philpem@40 908 case 0x000000: // Map RAM access
philpem@105 909 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X\n", address);
philpem@40 910 WR32(state.map, address, 0x7FF, value);
philpem@40 911 break;
philpem@40 912 case 0x020000: // Video RAM
philpem@105 913 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 914 WR32(state.vram, address, 0x7FFF, value);
philpem@40 915 break;
philpem@59 916 default:
philpem@59 917 IoWrite(address, value, 32);
philpem@40 918 }
philpem@59 919 } else {
philpem@59 920 IoWrite(address, value, 32);
philpem@40 921 }
philpem@59 922 }/*}}}*/
philpem@40 923
philpem@40 924 /**
philpem@40 925 * @brief Write M68K memory, 16-bit
philpem@40 926 */
philpem@59 927 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
philpem@40 928 {
philpem@40 929 // If ROMLMAP is set, force system to access ROM
philpem@40 930 if (!state.romlmap)
philpem@40 931 address |= 0x800000;
philpem@40 932
philpem@40 933 // Check access permissions
philpem@40 934 ACCESS_CHECK_WR(address, 16);
philpem@40 935
philpem@40 936 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 937 // ROM access
philpem@60 938 } else if (address <= 0x3FFFFF) {
philpem@40 939 // RAM access
philpem@128 940 uint32_t newAddr = MAP_ADDR(address);
philpem@112 941
philpem@119 942 if (newAddr <= 0x1fffff) {
philpem@119 943 if (newAddr < state.base_ram_size) {
philpem@119 944 WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@119 945 }
philpem@119 946 } else {
philpem@119 947 if ((newAddr - 0x200000) < state.exp_ram_size) {
philpem@119 948 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@119 949 }
philpem@119 950 }
philpem@40 951 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 952 // I/O register space, zone A
philpem@40 953 switch (address & 0x0F0000) {
philpem@40 954 case 0x000000: // Map RAM access
philpem@40 955 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 956 WR16(state.map, address, 0x7FF, value);
philpem@40 957 break;
philpem@40 958 case 0x020000: // Video RAM
philpem@40 959 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 960 WR16(state.vram, address, 0x7FFF, value);
philpem@40 961 break;
philpem@59 962 default:
philpem@59 963 IoWrite(address, value, 16);
philpem@40 964 }
philpem@59 965 } else {
philpem@59 966 IoWrite(address, value, 16);
philpem@40 967 }
philpem@59 968 }/*}}}*/
philpem@40 969
philpem@40 970 /**
philpem@40 971 * @brief Write M68K memory, 8-bit
philpem@40 972 */
philpem@59 973 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
philpem@40 974 {
philpem@40 975 // If ROMLMAP is set, force system to access ROM
philpem@40 976 if (!state.romlmap)
philpem@40 977 address |= 0x800000;
philpem@40 978
philpem@40 979 // Check access permissions
philpem@40 980 ACCESS_CHECK_WR(address, 8);
philpem@40 981
philpem@40 982 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 983 // ROM access (read only!)
philpem@60 984 } else if (address <= 0x3FFFFF) {
philpem@40 985 // RAM access
philpem@128 986 uint32_t newAddr = MAP_ADDR(address);
philpem@128 987
philpem@119 988 if (newAddr <= 0x1fffff) {
philpem@119 989 if (newAddr < state.base_ram_size) {
philpem@119 990 WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@119 991 }
philpem@119 992 } else {
philpem@119 993 if ((newAddr - 0x200000) < state.exp_ram_size) {
philpem@119 994 WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@119 995 }
philpem@119 996 }
philpem@40 997 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 998 // I/O register space, zone A
philpem@40 999 switch (address & 0x0F0000) {
philpem@40 1000 case 0x000000: // Map RAM access
philpem@59 1001 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 1002 WR8(state.map, address, 0x7FF, value);
philpem@40 1003 break;
philpem@40 1004 case 0x020000: // Video RAM
philpem@59 1005 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 1006 WR8(state.vram, address, 0x7FFF, value);
philpem@40 1007 break;
philpem@59 1008 default:
philpem@59 1009 IoWrite(address, value, 8);
philpem@40 1010 }
philpem@59 1011 } else {
philpem@59 1012 IoWrite(address, value, 8);
philpem@40 1013 }
philpem@59 1014 }/*}}}*/
philpem@40 1015
philpem@40 1016
philpem@40 1017 // for the disassembler
philpem@121 1018 uint32_t m68k_read_disassembler_32(uint32_t addr)
philpem@121 1019 {
philpem@121 1020 if (addr < 0x400000) {
philpem@128 1021 // XXX FIXME BUGBUG update this to use the new mapper macros!
philpem@121 1022 uint16_t page = (addr >> 12) & 0x3FF;
philpem@121 1023 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@121 1024 uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
philpem@121 1025 if (newAddr <= 0x1fffff) {
philpem@121 1026 if (newAddr >= state.base_ram_size)
philpem@121 1027 return EMPTY;
philpem@121 1028 else
philpem@121 1029 return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@121 1030 } else {
philpem@121 1031 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@121 1032 return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@121 1033 else
philpem@121 1034 return EMPTY;
philpem@121 1035 }
philpem@121 1036 } else {
philpem@128 1037 LOG("WARNING: Disassembler RD32 out of range 0x%08X\n", addr);
philpem@121 1038 return EMPTY;
philpem@121 1039 }
philpem@121 1040 }
philpem@40 1041
philpem@121 1042 uint32_t m68k_read_disassembler_16(uint32_t addr)
philpem@121 1043 {
philpem@121 1044 if (addr < 0x400000) {
philpem@121 1045 uint16_t page = (addr >> 12) & 0x3FF;
philpem@121 1046 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@121 1047 uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
philpem@121 1048 if (newAddr <= 0x1fffff) {
philpem@121 1049 if (newAddr >= state.base_ram_size)
philpem@121 1050 return EMPTY & 0xffff;
philpem@121 1051 else
philpem@121 1052 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@121 1053 } else {
philpem@121 1054 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@121 1055 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@121 1056 else
philpem@121 1057 return EMPTY & 0xffff;
philpem@121 1058 }
philpem@121 1059 } else {
philpem@128 1060 LOG("WARNING: Disassembler RD16 out of range 0x%08X\n", addr);
philpem@121 1061 return EMPTY & 0xffff;
philpem@121 1062 }
philpem@121 1063 }
philpem@121 1064
philpem@121 1065 uint32_t m68k_read_disassembler_8 (uint32_t addr)
philpem@121 1066 {
philpem@121 1067 if (addr < 0x400000) {
philpem@121 1068 uint16_t page = (addr >> 12) & 0x3FF;
philpem@121 1069 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@121 1070 uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
philpem@121 1071 if (newAddr <= 0x1fffff) {
philpem@121 1072 if (newAddr >= state.base_ram_size)
philpem@121 1073 return EMPTY & 0xff;
philpem@121 1074 else
philpem@121 1075 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@121 1076 } else {
philpem@121 1077 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@121 1078 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@121 1079 else
philpem@121 1080 return EMPTY & 0xff;
philpem@121 1081 }
philpem@121 1082 } else {
philpem@128 1083 LOG("WARNING: Disassembler RD8 out of range 0x%08X\n", addr);
philpem@121 1084 return EMPTY & 0xff;
philpem@121 1085 }
philpem@121 1086 }
philpem@121 1087