src/memory.c

Sat, 17 Nov 2012 22:26:53 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 17 Nov 2012 22:26:53 +0000
changeset 116
21521e62007f
parent 114
36367ebd34e0
child 117
73caf968b67b
permissions
-rw-r--r--

Add support for MSR2, partial reads from GENSTAT

* GENSTAT is sometimes read in 8bit mode. Handle this properly.

* Add support for the MSR2 register (additional HDD head select bit only at
the moment)

philpem@40 1 #include <stdio.h>
philpem@40 2 #include <stdlib.h>
philpem@40 3 #include <stdint.h>
philpem@40 4 #include <stdbool.h>
philpem@59 5 #include <assert.h>
philpem@40 6 #include "musashi/m68k.h"
philpem@40 7 #include "state.h"
philpem@100 8 #include "utils.h"
philpem@40 9 #include "memory.h"
philpem@40 10
philpem@40 11 /******************
philpem@40 12 * Memory mapping
philpem@40 13 ******************/
philpem@40 14
philpem@40 15 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
philpem@40 16
philpem@59 17 uint32_t mapAddr(uint32_t addr, bool writing)/*{{{*/
philpem@40 18 {
philpem@40 19 if (addr < 0x400000) {
philpem@40 20 // RAM access. Check against the Map RAM
philpem@40 21 // Start by getting the original page address
philpem@40 22 uint16_t page = (addr >> 12) & 0x3FF;
philpem@40 23
philpem@40 24 // Look it up in the map RAM and get the physical page address
philpem@40 25 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@40 26
philpem@40 27 // Update the Page Status bits
philpem@40 28 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
philpem@100 29 // Pagebits --
philpem@100 30 // 0 = not present
philpem@100 31 // 1 = present but not accessed
philpem@100 32 // 2 = present, accessed (read from)
philpem@100 33 // 3 = present, dirty (written to)
philpem@100 34 switch (pagebits) {
philpem@100 35 case 0:
philpem@100 36 // Page not present
philpem@100 37 // This should cause a page fault
philpem@100 38 LOGS("Whoa! Pagebit update, when the page is not present!");
philpem@100 39 break;
philpem@100 40
philpem@100 41 case 1:
philpem@100 42 // Page present -- first access
philpem@104 43 state.map[page*2] &= 0x9F; // turn off "present" bit (but not write enable!)
philpem@100 44 if (writing)
philpem@100 45 state.map[page*2] |= 0x60; // Page written to (dirty)
philpem@100 46 else
philpem@100 47 state.map[page*2] |= 0x40; // Page accessed but not written
philpem@100 48 break;
philpem@100 49
philpem@100 50 case 2:
philpem@100 51 case 3:
philpem@100 52 // Page present, 2nd or later access
philpem@100 53 if (writing)
philpem@100 54 state.map[page*2] |= 0x60; // Page written to (dirty)
philpem@100 55 break;
philpem@40 56 }
philpem@40 57
philpem@40 58 // Return the address with the new physical page spliced in
philpem@40 59 return (new_page_addr << 12) + (addr & 0xFFF);
philpem@40 60 } else {
philpem@40 61 // I/O, VRAM or MapRAM space; no mapping is performed or required
philpem@40 62 // TODO: assert here?
philpem@40 63 return addr;
philpem@40 64 }
philpem@59 65 }/*}}}*/
philpem@40 66
philpem@59 67 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)/*{{{*/
philpem@40 68 {
philpem@104 69 // Get the page bits for this page.
philpem@104 70 uint16_t page = (addr >> 12) & 0x3FF;
philpem@104 71 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
philpem@104 72
philpem@104 73 // Check page is present (but only for RAM zone)
philpem@104 74 if ((addr < 0x400000) && ((pagebits & 0x03) == 0)) {
philpem@104 75 LOG("Page not mapped in: addr %08X, page %04X, mapbits %04X", addr, page, MAPRAM(page));
philpem@104 76 return MEM_PAGEFAULT;
philpem@104 77 }
philpem@104 78
philpem@40 79 // Are we in Supervisor mode?
philpem@40 80 if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
philpem@40 81 // Yes. We can do anything we like.
philpem@40 82 return MEM_ALLOWED;
philpem@40 83
philpem@40 84 // If we're here, then we must be in User mode.
philpem@40 85 // Check that the user didn't access memory outside of the RAM area
philpem@106 86 if (addr >= 0x400000) {
philpem@106 87 LOGS("User accessed privileged memory");
philpem@40 88 return MEM_UIE;
philpem@106 89 }
philpem@40 90
philpem@40 91 // User attempt to access the kernel
philpem@40 92 // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
philpem@106 93 if (((addr >> 19) & 0x0F) == 0) {
philpem@106 94 LOGS("Attempt by user code to access kernel space");
philpem@40 95 return MEM_KERNEL;
philpem@106 96 }
philpem@40 97
philpem@40 98 // Check page is write enabled
philpem@106 99 if (writing && ((pagebits & 0x04) == 0)) {
philpem@106 100 LOG("Page not write enabled: inaddr %08X, page %04X, mapram %04X [%02X %02X], pagebits %d",
philpem@106 101 addr, page, MAPRAM(page), state.map[page*2], state.map[(page*2)+1], pagebits);
philpem@40 102 return MEM_PAGE_NO_WE;
philpem@106 103 }
philpem@40 104
philpem@40 105 // Page access allowed.
philpem@40 106 return MEM_ALLOWED;
philpem@59 107 }/*}}}*/
philpem@40 108
philpem@40 109 #undef MAPRAM
philpem@40 110
philpem@40 111
philpem@40 112 /********************************************************
philpem@40 113 * m68k memory read/write support functions for Musashi
philpem@40 114 ********************************************************/
philpem@40 115
philpem@40 116 /**
philpem@40 117 * @brief Check memory access permissions for a write operation.
philpem@40 118 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
philpem@40 119 * gcc throws warnings when you have a return-with-value in a void
philpem@40 120 * function, even if the return-with-value is completely unreachable.
philpem@40 121 * Similarly it doesn't like it if you have a return without a value
philpem@40 122 * in a non-void function, even if it's impossible to ever reach the
philpem@40 123 * return-with-no-value. UGH!
philpem@40 124 */
philpem@59 125 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
philpem@59 126 #define ACCESS_CHECK_WR(address, bits) \
philpem@59 127 do { \
philpem@40 128 bool fault = false; \
philpem@103 129 MEM_STATUS st; \
philpem@103 130 switch (st = checkMemoryAccess(address, true)) { \
philpem@40 131 case MEM_ALLOWED: \
philpem@40 132 /* Access allowed */ \
philpem@40 133 break; \
philpem@40 134 case MEM_PAGEFAULT: \
philpem@40 135 /* Page fault */ \
philpem@44 136 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0); \
philpem@40 137 fault = true; \
philpem@40 138 break; \
philpem@40 139 case MEM_UIE: \
philpem@40 140 /* User access to memory above 4MB */ \
philpem@44 141 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0); \
philpem@40 142 fault = true; \
philpem@40 143 break; \
philpem@40 144 case MEM_KERNEL: \
philpem@40 145 case MEM_PAGE_NO_WE: \
philpem@40 146 /* kernel access or page not write enabled */ \
philpem@112 147 /* XXX: is this the correct value? */ \
philpem@112 148 state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0); \
philpem@40 149 fault = true; \
philpem@40 150 break; \
philpem@40 151 } \
philpem@40 152 \
philpem@40 153 if (fault) { \
philpem@40 154 if (bits >= 16) \
philpem@68 155 state.bsr0 = 0x7C00; \
philpem@40 156 else \
philpem@108 157 state.bsr0 = (address & 1) ? 0x7E00 : 0x7D00; \
philpem@40 158 state.bsr0 |= (address >> 16); \
philpem@40 159 state.bsr1 = address & 0xffff; \
philpem@103 160 LOG("Bus Error while writing, addr %08X, statcode %d", address, st); \
philpem@103 161 if (state.ee) m68k_pulse_bus_error(); \
philpem@40 162 return; \
philpem@40 163 } \
philpem@70 164 } while (0)
philpem@59 165 /*}}}*/
philpem@40 166
philpem@40 167 /**
philpem@40 168 * @brief Check memory access permissions for a read operation.
philpem@40 169 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
philpem@40 170 * gcc throws warnings when you have a return-with-value in a void
philpem@40 171 * function, even if the return-with-value is completely unreachable.
philpem@40 172 * Similarly it doesn't like it if you have a return without a value
philpem@40 173 * in a non-void function, even if it's impossible to ever reach the
philpem@40 174 * return-with-no-value. UGH!
philpem@40 175 */
philpem@59 176 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
philpem@59 177 #define ACCESS_CHECK_RD(address, bits) \
philpem@59 178 do { \
philpem@40 179 bool fault = false; \
philpem@103 180 MEM_STATUS st; \
philpem@103 181 switch (st = checkMemoryAccess(address, false)) { \
philpem@40 182 case MEM_ALLOWED: \
philpem@40 183 /* Access allowed */ \
philpem@40 184 break; \
philpem@40 185 case MEM_PAGEFAULT: \
philpem@40 186 /* Page fault */ \
philpem@44 187 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0); \
philpem@40 188 fault = true; \
philpem@40 189 break; \
philpem@40 190 case MEM_UIE: \
philpem@40 191 /* User access to memory above 4MB */ \
philpem@44 192 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0); \
philpem@40 193 fault = true; \
philpem@40 194 break; \
philpem@40 195 case MEM_KERNEL: \
philpem@40 196 case MEM_PAGE_NO_WE: \
philpem@40 197 /* kernel access or page not write enabled */ \
philpem@112 198 /* XXX: is this the correct value? */ \
philpem@112 199 state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0); \
philpem@40 200 fault = true; \
philpem@40 201 break; \
philpem@40 202 } \
philpem@40 203 \
philpem@40 204 if (fault) { \
philpem@40 205 if (bits >= 16) \
philpem@68 206 state.bsr0 = 0x7C00; \
philpem@40 207 else \
philpem@108 208 state.bsr0 = (address & 1) ? 0x7E00 : 0x7D00; \
philpem@40 209 state.bsr0 |= (address >> 16); \
philpem@40 210 state.bsr1 = address & 0xffff; \
philpem@103 211 LOG("Bus Error while reading, addr %08X, statcode %d", address, st); \
philpem@103 212 if (state.ee) m68k_pulse_bus_error(); \
philpem@113 213 if (bits == 32) \
philpem@113 214 return 0xFFFFFFFF; \
philpem@113 215 else \
philpem@114 216 return (1UL << bits)-1; \
philpem@40 217 } \
philpem@70 218 } while (0)
philpem@59 219 /*}}}*/
philpem@40 220
philpem@112 221 bool access_check_dma(int reading)
philpem@112 222 {
philpem@112 223 // Check memory access permissions
philpem@112 224 bool access_ok;
philpem@112 225 switch (checkMemoryAccess(state.dma_address, !reading)) {
philpem@112 226 case MEM_PAGEFAULT:
philpem@112 227 // Page fault
philpem@112 228 state.genstat = 0xABFF
philpem@112 229 | (reading ? 0x4000 : 0)
philpem@112 230 | (state.pie ? 0x0400 : 0);
philpem@112 231 access_ok = false;
philpem@112 232 break;
philpem@112 233
philpem@112 234 case MEM_UIE:
philpem@112 235 // User access to memory above 4MB
philpem@112 236 // FIXME? Shouldn't be possible with DMA... assert this?
philpem@112 237 state.genstat = 0xBAFF
philpem@112 238 | (reading ? 0x4000 : 0)
philpem@112 239 | (state.pie ? 0x0400 : 0);
philpem@112 240 access_ok = false;
philpem@112 241 break;
philpem@112 242
philpem@112 243 case MEM_KERNEL:
philpem@112 244 case MEM_PAGE_NO_WE:
philpem@112 245 // Kernel access or page not write enabled
philpem@112 246 /* XXX: is this correct? */
philpem@112 247 state.genstat = 0xBBFF
philpem@112 248 | (reading ? 0x4000 : 0)
philpem@112 249 | (state.pie ? 0x0400 : 0);
philpem@112 250 access_ok = false;
philpem@112 251 break;
philpem@112 252
philpem@112 253 case MEM_ALLOWED:
philpem@112 254 access_ok = true;
philpem@112 255 break;
philpem@112 256 }
philpem@112 257 if (!access_ok) {
philpem@112 258 state.bsr0 = 0x3C00;
philpem@112 259 state.bsr0 |= (state.dma_address >> 16);
philpem@112 260 state.bsr1 = state.dma_address & 0xffff;
philpem@112 261 if (state.ee) m68k_set_irq(7);
philpem@112 262 printf("BUS ERROR FROM DMA: genstat=%04X, bsr0=%04X, bsr1=%04X\n", state.genstat, state.bsr0, state.bsr1);
philpem@112 263 }
philpem@112 264 return (access_ok);
philpem@112 265 }
philpem@112 266
philpem@40 267 // Logging macros
philpem@59 268 #define LOG_NOT_HANDLED_R(bits) \
philpem@64 269 if (!handled) printf("unhandled read%02d, addr=0x%08X\n", bits, address);
philpem@40 270
philpem@59 271 #define LOG_NOT_HANDLED_W(bits) \
philpem@64 272 if (!handled) printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
philpem@59 273
philpem@59 274 /********************************************************
philpem@59 275 * I/O read/write functions
philpem@59 276 ********************************************************/
philpem@40 277
philpem@40 278 /**
philpem@59 279 * Issue a warning if a read operation is made with an invalid size
philpem@40 280 */
philpem@66 281 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
philpem@40 282 {
philpem@59 283 assert((bits == 8) || (bits == 16) || (bits == 32));
philpem@59 284 if ((bits & allowed) == 0) {
philpem@66 285 printf("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
philpem@59 286 }
philpem@59 287 }
philpem@59 288
philpem@66 289 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
philpem@40 290 {
philpem@66 291 ENFORCE_SIZE(bits, address, true, allowed, regname);
philpem@66 292 }
philpem@66 293
philpem@66 294 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
philpem@66 295 {
philpem@66 296 ENFORCE_SIZE(bits, address, false, allowed, regname);
philpem@66 297 }
philpem@66 298
philpem@59 299 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
philpem@59 300 {
philpem@40 301 bool handled = false;
philpem@40 302
philpem@59 303 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 304 // I/O register space, zone A
philpem@40 305 switch (address & 0x0F0000) {
philpem@40 306 case 0x010000: // General Status Register
philpem@59 307 if (bits == 16)
philpem@59 308 state.genstat = (data & 0xffff);
philpem@59 309 else if (bits == 8) {
philpem@59 310 if (address & 0)
philpem@59 311 state.genstat = data;
philpem@59 312 else
philpem@59 313 state.genstat = data << 8;
philpem@59 314 }
philpem@40 315 handled = true;
philpem@40 316 break;
philpem@40 317 case 0x030000: // Bus Status Register 0
philpem@40 318 break;
philpem@40 319 case 0x040000: // Bus Status Register 1
philpem@40 320 break;
philpem@40 321 case 0x050000: // Phone status
philpem@40 322 break;
philpem@40 323 case 0x060000: // DMA Count
philpem@66 324 ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
philpem@59 325 state.dma_count = (data & 0x3FFF);
philpem@59 326 state.idmarw = ((data & 0x4000) == 0x4000);
philpem@59 327 state.dmaen = ((data & 0x8000) == 0x8000);
philpem@59 328 // This handles the "dummy DMA transfer" mentioned in the docs
philpem@112 329 // disabled because it causes the floppy test to fail
philpem@112 330 #if 0
philpem@112 331 if (!state.idmarw){
philpem@112 332 if (access_check_dma(true)){
philpem@112 333 uint32_t newAddr = mapAddr(state.dma_address, true);
philpem@112 334 // RAM access
philpem@112 335 if (newAddr <= 0x1fffff)
philpem@112 336 WR16(state.base_ram, newAddr, state.base_ram_size - 1, 0xFF);
philpem@112 337 else if (address <= 0x3FFFFF)
philpem@112 338 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, 0xFF);
philpem@112 339 }
philpem@112 340 }
philpem@112 341 #endif
philpem@59 342 state.dma_count++;
philpem@53 343 handled = true;
philpem@40 344 break;
philpem@40 345 case 0x070000: // Line Printer Status Register
philpem@40 346 break;
philpem@40 347 case 0x080000: // Real Time Clock
philpem@40 348 break;
philpem@40 349 case 0x090000: // Phone registers
philpem@40 350 switch (address & 0x0FF000) {
philpem@40 351 case 0x090000: // Handset relay
philpem@40 352 case 0x098000:
philpem@40 353 break;
philpem@40 354 case 0x091000: // Line select 2
philpem@40 355 case 0x099000:
philpem@40 356 break;
philpem@40 357 case 0x092000: // Hook relay 1
philpem@40 358 case 0x09A000:
philpem@40 359 break;
philpem@40 360 case 0x093000: // Hook relay 2
philpem@40 361 case 0x09B000:
philpem@40 362 break;
philpem@40 363 case 0x094000: // Line 1 hold
philpem@40 364 case 0x09C000:
philpem@40 365 break;
philpem@40 366 case 0x095000: // Line 2 hold
philpem@40 367 case 0x09D000:
philpem@40 368 break;
philpem@40 369 case 0x096000: // Line 1 A-lead
philpem@40 370 case 0x09E000:
philpem@40 371 break;
philpem@40 372 case 0x097000: // Line 2 A-lead
philpem@40 373 case 0x09F000:
philpem@40 374 break;
philpem@40 375 }
philpem@40 376 break;
philpem@59 377 case 0x0A0000: // Miscellaneous Control Register
philpem@66 378 ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
philpem@59 379 // TODO: handle the ctrl bits properly
philpem@97 380 if (data & 0x8000){
philpem@97 381 state.timer_enabled = 1;
philpem@97 382 }else{
philpem@97 383 state.timer_enabled = 0;
philpem@97 384 state.timer_asserted = 0;
philpem@97 385 }
philpem@59 386 state.dma_reading = (data & 0x4000);
philpem@72 387 if (state.leds != ((~data & 0xF00) >> 8)) {
philpem@72 388 state.leds = (~data & 0xF00) >> 8;
philpem@72 389 printf("LEDs: %s %s %s %s\n",
philpem@72 390 (state.leds & 8) ? "R" : "-",
philpem@72 391 (state.leds & 4) ? "G" : "-",
philpem@72 392 (state.leds & 2) ? "Y" : "-",
philpem@72 393 (state.leds & 1) ? "R" : "-");
philpem@72 394 }
philpem@46 395 handled = true;
philpem@40 396 break;
philpem@40 397 case 0x0B0000: // TM/DIALWR
philpem@40 398 break;
philpem@59 399 case 0x0C0000: // Clear Status Register
philpem@59 400 state.genstat = 0xFFFF;
philpem@59 401 state.bsr0 = 0xFFFF;
philpem@59 402 state.bsr1 = 0xFFFF;
philpem@43 403 handled = true;
philpem@40 404 break;
philpem@40 405 case 0x0D0000: // DMA Address Register
philpem@59 406 if (address & 0x004000) {
philpem@59 407 // A14 high -- set most significant bits
philpem@59 408 state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
philpem@59 409 } else {
philpem@59 410 // A14 low -- set least significant bits
philpem@59 411 state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
philpem@59 412 }
philpem@59 413 handled = true;
philpem@40 414 break;
philpem@40 415 case 0x0E0000: // Disk Control Register
philpem@112 416 {
philpem@112 417 bool fd_selected;
philpem@112 418 bool hd_selected;
philpem@112 419 ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
philpem@112 420 // B7 = FDD controller reset
philpem@112 421 if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
philpem@112 422 // B6 = drive 0 select
philpem@112 423 fd_selected = (data & 0x40) != 0;
philpem@112 424 // B5 = motor enable -- TODO
philpem@112 425 // B4 = HDD controller reset
philpem@112 426 if ((data & 0x10) == 0) wd2010_reset(&state.hdc_ctx);
philpem@112 427 // B3 = HDD0 select
philpem@112 428 hd_selected = (data & 0x08) != 0;
philpem@112 429 // B2,1,0 = HDD0 head select -- TODO?
philpem@112 430 if (hd_selected && !state.hd_selected){
philpem@112 431 state.fd_selected = false;
philpem@112 432 state.hd_selected = true;
philpem@112 433 }else if (fd_selected && !state.fd_selected){
philpem@112 434 state.hd_selected = false;
philpem@112 435 state.fd_selected = true;
philpem@112 436 }
philpem@112 437 handled = true;
philpem@112 438 break;
philpem@112 439 }
philpem@40 440 case 0x0F0000: // Line Printer Data Register
philpem@40 441 break;
philpem@40 442 }
philpem@40 443 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 444 // I/O register space, zone B
philpem@40 445 switch (address & 0xF00000) {
philpem@40 446 case 0xC00000: // Expansion slots
philpem@40 447 case 0xD00000:
philpem@40 448 switch (address & 0xFC0000) {
philpem@40 449 case 0xC00000: // Expansion slot 0
philpem@40 450 case 0xC40000: // Expansion slot 1
philpem@40 451 case 0xC80000: // Expansion slot 2
philpem@40 452 case 0xCC0000: // Expansion slot 3
philpem@40 453 case 0xD00000: // Expansion slot 4
philpem@40 454 case 0xD40000: // Expansion slot 5
philpem@40 455 case 0xD80000: // Expansion slot 6
philpem@40 456 case 0xDC0000: // Expansion slot 7
philpem@59 457 fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
philpem@59 458 handled = true;
philpem@40 459 break;
philpem@40 460 }
philpem@40 461 break;
philpem@40 462 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 463 case 0xF00000:
philpem@40 464 switch (address & 0x070000) {
philpem@112 465 case 0x000000: // [ef][08]xxxx ==> WD2010 hard disc controller
philpem@112 466 wd2010_write_reg(&state.hdc_ctx, (address >> 1) & 7, data);
philpem@112 467 handled = true;
philpem@40 468 break;
philpem@40 469 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@112 470 /*ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");*/
philpem@59 471 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
philpem@52 472 handled = true;
philpem@40 473 break;
philpem@40 474 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@116 475 // MCR2 - UNIX PC Rev. P5.1 HDD head select b3 and potential HDD#2 select
philpem@116 476 wd2010_write_reg(&state.hdc_ctx, UNIXPC_REG_MCR2, data);
philpem@116 477 handled = true;
philpem@40 478 break;
philpem@40 479 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 480 break;
philpem@40 481 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 482 switch (address & 0x077000) {
philpem@40 483 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@102 484 // Error Enable. If =0, Level7 intrs and bus errors are masked.
philpem@102 485 ENFORCE_SIZE_W(bits, address, 16, "EE");
philpem@102 486 state.ee = ((data & 0x8000) == 0x8000);
philpem@102 487 handled = true;
philpem@59 488 break;
philpem@44 489 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@66 490 ENFORCE_SIZE_W(bits, address, 16, "PIE");
philpem@59 491 state.pie = ((data & 0x8000) == 0x8000);
philpem@59 492 handled = true;
philpem@59 493 break;
philpem@40 494 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@59 495 break;
philpem@40 496 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@66 497 ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
philpem@59 498 state.romlmap = ((data & 0x8000) == 0x8000);
philpem@44 499 handled = true;
philpem@40 500 break;
philpem@59 501 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@66 502 ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
philpem@59 503 break;
philpem@59 504 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@66 505 ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
philpem@59 506 break;
philpem@59 507 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@66 508 ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
philpem@59 509 break;
philpem@59 510 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@66 511 ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
philpem@40 512 break;
philpem@40 513 }
philpem@40 514 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 515 break;
philpem@40 516 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 517 switch (address & 0x07F000) {
philpem@40 518 default:
philpem@40 519 break;
philpem@40 520 }
philpem@40 521 break;
philpem@40 522 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@84 523 // TODO: figure out which sizes are valid (probably just 8 and 16)
philpem@84 524 // ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER");
philpem@93 525 if (bits == 8) {
philpem@93 526 printf("KBD WR %02X => %02X\n", (address >> 1) & 3, data);
philpem@93 527 keyboard_write(&state.kbd, (address >> 1) & 3, data);
philpem@93 528 handled = true;
philpem@93 529 } else if (bits == 16) {
philpem@93 530 printf("KBD WR %02X => %04X\n", (address >> 1) & 3, data);
philpem@93 531 keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8);
philpem@93 532 handled = true;
philpem@93 533 }
philpem@40 534 break;
philpem@40 535 }
philpem@40 536 }
philpem@40 537 }
philpem@40 538
philpem@64 539 LOG_NOT_HANDLED_W(bits);
philpem@59 540 }/*}}}*/
philpem@40 541
philpem@59 542 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
philpem@59 543 {
philpem@59 544 bool handled = false;
philpem@59 545 uint32_t data = 0xFFFFFFFF;
philpem@40 546
philpem@59 547 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 548 // I/O register space, zone A
philpem@40 549 switch (address & 0x0F0000) {
philpem@40 550 case 0x010000: // General Status Register
philpem@116 551 /* ENFORCE_SIZE_R(bits, address, 16, "GENSTAT"); */
philpem@116 552 if (bits == 32) {
philpem@116 553 return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
philpem@116 554 } else if (bits == 16) {
philpem@116 555 return (uint16_t)state.genstat;
philpem@116 556 } else {
philpem@116 557 return (uint8_t)(state.genstat & 0xff);
philpem@116 558 }
philpem@40 559 break;
philpem@40 560 case 0x030000: // Bus Status Register 0
philpem@66 561 ENFORCE_SIZE_R(bits, address, 16, "BSR0");
philpem@59 562 return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
philpem@40 563 break;
philpem@40 564 case 0x040000: // Bus Status Register 1
philpem@66 565 ENFORCE_SIZE_R(bits, address, 16, "BSR1");
philpem@59 566 return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
philpem@40 567 break;
philpem@40 568 case 0x050000: // Phone status
philpem@66 569 ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
philpem@40 570 break;
philpem@40 571 case 0x060000: // DMA Count
philpem@55 572 // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
philpem@55 573 // Bit 14 is always unused, so leave it set
philpem@66 574 ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
philpem@59 575 return (state.dma_count & 0x3fff) | 0xC000;
philpem@40 576 break;
philpem@40 577 case 0x070000: // Line Printer Status Register
philpem@53 578 data = 0x00120012; // no parity error, no line printer error, no irqs from FDD or HDD
philpem@78 579 data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0;
philpem@112 580 data |= wd2010_get_irq(&state.hdc_ctx) ? 0x00040004 : 0;
philpem@59 581 return data;
philpem@40 582 break;
philpem@40 583 case 0x080000: // Real Time Clock
philpem@59 584 printf("READ NOTIMP: Realtime Clock\n");
philpem@40 585 break;
philpem@40 586 case 0x090000: // Phone registers
philpem@40 587 switch (address & 0x0FF000) {
philpem@40 588 case 0x090000: // Handset relay
philpem@40 589 case 0x098000:
philpem@40 590 break;
philpem@40 591 case 0x091000: // Line select 2
philpem@40 592 case 0x099000:
philpem@40 593 break;
philpem@40 594 case 0x092000: // Hook relay 1
philpem@40 595 case 0x09A000:
philpem@40 596 break;
philpem@40 597 case 0x093000: // Hook relay 2
philpem@40 598 case 0x09B000:
philpem@40 599 break;
philpem@40 600 case 0x094000: // Line 1 hold
philpem@40 601 case 0x09C000:
philpem@40 602 break;
philpem@40 603 case 0x095000: // Line 2 hold
philpem@40 604 case 0x09D000:
philpem@40 605 break;
philpem@40 606 case 0x096000: // Line 1 A-lead
philpem@40 607 case 0x09E000:
philpem@40 608 break;
philpem@40 609 case 0x097000: // Line 2 A-lead
philpem@40 610 case 0x09F000:
philpem@40 611 break;
philpem@40 612 }
philpem@40 613 break;
philpem@46 614 case 0x0A0000: // Miscellaneous Control Register -- write only!
philpem@46 615 handled = true;
philpem@40 616 break;
philpem@40 617 case 0x0B0000: // TM/DIALWR
philpem@40 618 break;
philpem@46 619 case 0x0C0000: // Clear Status Register -- write only!
philpem@43 620 handled = true;
philpem@40 621 break;
philpem@40 622 case 0x0D0000: // DMA Address Register
philpem@40 623 break;
philpem@40 624 case 0x0E0000: // Disk Control Register
philpem@40 625 break;
philpem@40 626 case 0x0F0000: // Line Printer Data Register
philpem@40 627 break;
philpem@40 628 }
philpem@40 629 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 630 // I/O register space, zone B
philpem@40 631 switch (address & 0xF00000) {
philpem@40 632 case 0xC00000: // Expansion slots
philpem@40 633 case 0xD00000:
philpem@40 634 switch (address & 0xFC0000) {
philpem@40 635 case 0xC00000: // Expansion slot 0
philpem@40 636 case 0xC40000: // Expansion slot 1
philpem@40 637 case 0xC80000: // Expansion slot 2
philpem@40 638 case 0xCC0000: // Expansion slot 3
philpem@40 639 case 0xD00000: // Expansion slot 4
philpem@40 640 case 0xD40000: // Expansion slot 5
philpem@40 641 case 0xD80000: // Expansion slot 6
philpem@40 642 case 0xDC0000: // Expansion slot 7
philpem@65 643 fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
philpem@65 644 handled = true;
philpem@40 645 break;
philpem@40 646 }
philpem@40 647 break;
philpem@40 648 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 649 case 0xF00000:
philpem@40 650 switch (address & 0x070000) {
philpem@40 651 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@112 652 return (wd2010_read_reg(&state.hdc_ctx, (address >> 1) & 7));
philpem@112 653
philpem@40 654 break;
philpem@40 655 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@112 656 /*ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");*/
philpem@59 657 return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
philpem@40 658 break;
philpem@40 659 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 660 break;
philpem@40 661 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 662 break;
philpem@40 663 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 664 switch (address & 0x077000) {
philpem@40 665 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@44 666 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@40 667 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 668 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@40 669 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@40 670 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@40 671 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@44 672 // All write-only registers... TODO: bus error?
philpem@44 673 handled = true;
philpem@40 674 break;
philpem@44 675 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
philpem@40 676 break;
philpem@40 677 }
philpem@40 678 break;
philpem@40 679 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 680 break;
philpem@40 681 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 682 switch (address & 0x07F000) {
philpem@40 683 default:
philpem@40 684 break;
philpem@40 685 }
philpem@40 686 break;
philpem@40 687 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@84 688 // TODO: figure out which sizes are valid (probably just 8 and 16)
philpem@84 689 //ENFORCE_SIZE_R(bits, address, 16, "KEYBOARD CONTROLLER");
philpem@84 690 {
philpem@93 691 if (bits == 8) {
philpem@93 692 return keyboard_read(&state.kbd, (address >> 1) & 3);
philpem@93 693 } else {
philpem@93 694 return keyboard_read(&state.kbd, (address >> 1) & 3) << 8;
philpem@93 695 }
philpem@84 696 return data;
philpem@84 697 }
philpem@40 698 break;
philpem@40 699 }
philpem@40 700 }
philpem@40 701 }
philpem@40 702
philpem@64 703 LOG_NOT_HANDLED_R(bits);
philpem@64 704
philpem@59 705 return data;
philpem@59 706 }/*}}}*/
philpem@40 707
philpem@59 708
philpem@59 709 /********************************************************
philpem@59 710 * m68k memory read/write support functions for Musashi
philpem@59 711 ********************************************************/
philpem@59 712
philpem@59 713 /**
philpem@59 714 * @brief Read M68K memory, 32-bit
philpem@59 715 */
philpem@59 716 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
philpem@59 717 {
philpem@59 718 uint32_t data = 0xFFFFFFFF;
philpem@59 719
philpem@59 720 // If ROMLMAP is set, force system to access ROM
philpem@59 721 if (!state.romlmap)
philpem@59 722 address |= 0x800000;
philpem@59 723
philpem@59 724 // Check access permissions
philpem@59 725 ACCESS_CHECK_RD(address, 32);
philpem@59 726
philpem@59 727 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@59 728 // ROM access
philpem@60 729 return RD32(state.rom, address, ROM_SIZE - 1);
philpem@60 730 } else if (address <= 0x3fffff) {
philpem@59 731 // RAM access
philpem@60 732 uint32_t newAddr = mapAddr(address, false);
philpem@63 733 if (newAddr <= 0x1fffff) {
philpem@60 734 return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 735 } else {
philpem@63 736 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
philpem@63 737 return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 738 else
philpem@63 739 return 0xffffffff;
philpem@63 740 }
philpem@59 741 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@59 742 // I/O register space, zone A
philpem@59 743 switch (address & 0x0F0000) {
philpem@59 744 case 0x000000: // Map RAM access
philpem@59 745 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
philpem@60 746 return RD32(state.map, address, 0x7FF);
philpem@59 747 break;
philpem@59 748 case 0x020000: // Video RAM
philpem@59 749 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@60 750 return RD32(state.vram, address, 0x7FFF);
philpem@59 751 break;
philpem@59 752 default:
philpem@60 753 return IoRead(address, 32);
philpem@59 754 }
philpem@59 755 } else {
philpem@60 756 return IoRead(address, 32);
philpem@59 757 }
philpem@59 758
philpem@40 759 return data;
philpem@59 760 }/*}}}*/
philpem@40 761
philpem@40 762 /**
philpem@40 763 * @brief Read M68K memory, 16-bit
philpem@40 764 */
philpem@59 765 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
philpem@40 766 {
philpem@40 767 uint16_t data = 0xFFFF;
philpem@40 768
philpem@40 769 // If ROMLMAP is set, force system to access ROM
philpem@40 770 if (!state.romlmap)
philpem@40 771 address |= 0x800000;
philpem@40 772
philpem@40 773 // Check access permissions
philpem@40 774 ACCESS_CHECK_RD(address, 16);
philpem@40 775
philpem@40 776 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 777 // ROM access
philpem@40 778 data = RD16(state.rom, address, ROM_SIZE - 1);
philpem@60 779 } else if (address <= 0x3fffff) {
philpem@40 780 // RAM access
philpem@60 781 uint32_t newAddr = mapAddr(address, false);
philpem@63 782 if (newAddr <= 0x1fffff) {
philpem@60 783 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 784 } else {
philpem@63 785 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
philpem@63 786 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 787 else
philpem@63 788 return 0xffff;
philpem@63 789 }
philpem@40 790 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 791 // I/O register space, zone A
philpem@40 792 switch (address & 0x0F0000) {
philpem@40 793 case 0x000000: // Map RAM access
philpem@40 794 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 795 data = RD16(state.map, address, 0x7FF);
philpem@40 796 break;
philpem@40 797 case 0x020000: // Video RAM
philpem@40 798 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 799 data = RD16(state.vram, address, 0x7FFF);
philpem@40 800 break;
philpem@59 801 default:
philpem@59 802 data = IoRead(address, 16);
philpem@40 803 }
philpem@59 804 } else {
philpem@59 805 data = IoRead(address, 16);
philpem@40 806 }
philpem@40 807
philpem@40 808 return data;
philpem@59 809 }/*}}}*/
philpem@40 810
philpem@40 811 /**
philpem@40 812 * @brief Read M68K memory, 8-bit
philpem@40 813 */
philpem@59 814 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
philpem@40 815 {
philpem@40 816 uint8_t data = 0xFF;
philpem@40 817
philpem@40 818 // If ROMLMAP is set, force system to access ROM
philpem@40 819 if (!state.romlmap)
philpem@40 820 address |= 0x800000;
philpem@40 821
philpem@40 822 // Check access permissions
philpem@40 823 ACCESS_CHECK_RD(address, 8);
philpem@40 824
philpem@40 825 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 826 // ROM access
philpem@40 827 data = RD8(state.rom, address, ROM_SIZE - 1);
philpem@60 828 } else if (address <= 0x3fffff) {
philpem@40 829 // RAM access
philpem@60 830 uint32_t newAddr = mapAddr(address, false);
philpem@63 831 if (newAddr <= 0x1fffff) {
philpem@60 832 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 833 } else {
philpem@63 834 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
philpem@63 835 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 836 else
philpem@63 837 return 0xff;
philpem@63 838 }
philpem@40 839 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 840 // I/O register space, zone A
philpem@40 841 switch (address & 0x0F0000) {
philpem@40 842 case 0x000000: // Map RAM access
philpem@40 843 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 844 data = RD8(state.map, address, 0x7FF);
philpem@40 845 break;
philpem@40 846 case 0x020000: // Video RAM
philpem@40 847 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 848 data = RD8(state.vram, address, 0x7FFF);
philpem@40 849 break;
philpem@59 850 default:
philpem@59 851 data = IoRead(address, 8);
philpem@40 852 }
philpem@59 853 } else {
philpem@59 854 data = IoRead(address, 8);
philpem@40 855 }
philpem@40 856
philpem@40 857 return data;
philpem@59 858 }/*}}}*/
philpem@40 859
philpem@40 860 /**
philpem@40 861 * @brief Write M68K memory, 32-bit
philpem@40 862 */
philpem@59 863 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
philpem@40 864 {
philpem@40 865 // If ROMLMAP is set, force system to access ROM
philpem@40 866 if (!state.romlmap)
philpem@40 867 address |= 0x800000;
philpem@40 868
philpem@40 869 // Check access permissions
philpem@40 870 ACCESS_CHECK_WR(address, 32);
philpem@40 871
philpem@40 872 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 873 // ROM access
philpem@60 874 } else if (address <= 0x3FFFFF) {
philpem@40 875 // RAM access
philpem@60 876 uint32_t newAddr = mapAddr(address, true);
philpem@70 877 if (newAddr <= 0x1fffff)
philpem@60 878 WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@70 879 else
philpem@65 880 WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@40 881 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 882 // I/O register space, zone A
philpem@40 883 switch (address & 0x0F0000) {
philpem@40 884 case 0x000000: // Map RAM access
philpem@105 885 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X\n", address);
philpem@40 886 WR32(state.map, address, 0x7FF, value);
philpem@40 887 break;
philpem@40 888 case 0x020000: // Video RAM
philpem@105 889 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 890 WR32(state.vram, address, 0x7FFF, value);
philpem@40 891 break;
philpem@59 892 default:
philpem@59 893 IoWrite(address, value, 32);
philpem@40 894 }
philpem@59 895 } else {
philpem@59 896 IoWrite(address, value, 32);
philpem@40 897 }
philpem@59 898 }/*}}}*/
philpem@40 899
philpem@40 900 /**
philpem@40 901 * @brief Write M68K memory, 16-bit
philpem@40 902 */
philpem@59 903 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
philpem@40 904 {
philpem@40 905 // If ROMLMAP is set, force system to access ROM
philpem@40 906 if (!state.romlmap)
philpem@40 907 address |= 0x800000;
philpem@40 908
philpem@40 909 // Check access permissions
philpem@40 910 ACCESS_CHECK_WR(address, 16);
philpem@40 911
philpem@40 912 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 913 // ROM access
philpem@60 914 } else if (address <= 0x3FFFFF) {
philpem@40 915 // RAM access
philpem@60 916 uint32_t newAddr = mapAddr(address, true);
philpem@112 917
philpem@70 918 if (newAddr <= 0x1fffff)
philpem@60 919 WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@70 920 else
philpem@65 921 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@40 922 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 923 // I/O register space, zone A
philpem@40 924 switch (address & 0x0F0000) {
philpem@40 925 case 0x000000: // Map RAM access
philpem@40 926 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 927 WR16(state.map, address, 0x7FF, value);
philpem@40 928 break;
philpem@40 929 case 0x020000: // Video RAM
philpem@40 930 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 931 WR16(state.vram, address, 0x7FFF, value);
philpem@40 932 break;
philpem@59 933 default:
philpem@59 934 IoWrite(address, value, 16);
philpem@40 935 }
philpem@59 936 } else {
philpem@59 937 IoWrite(address, value, 16);
philpem@40 938 }
philpem@59 939 }/*}}}*/
philpem@40 940
philpem@40 941 /**
philpem@40 942 * @brief Write M68K memory, 8-bit
philpem@40 943 */
philpem@59 944 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
philpem@40 945 {
philpem@40 946 // If ROMLMAP is set, force system to access ROM
philpem@40 947 if (!state.romlmap)
philpem@40 948 address |= 0x800000;
philpem@40 949
philpem@40 950 // Check access permissions
philpem@40 951 ACCESS_CHECK_WR(address, 8);
philpem@40 952
philpem@40 953 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 954 // ROM access (read only!)
philpem@60 955 } else if (address <= 0x3FFFFF) {
philpem@40 956 // RAM access
philpem@60 957 uint32_t newAddr = mapAddr(address, true);
philpem@70 958 if (newAddr <= 0x1fffff)
philpem@60 959 WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@70 960 else
philpem@65 961 WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@40 962 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 963 // I/O register space, zone A
philpem@40 964 switch (address & 0x0F0000) {
philpem@40 965 case 0x000000: // Map RAM access
philpem@59 966 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 967 WR8(state.map, address, 0x7FF, value);
philpem@40 968 break;
philpem@40 969 case 0x020000: // Video RAM
philpem@59 970 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 971 WR8(state.vram, address, 0x7FFF, value);
philpem@40 972 break;
philpem@59 973 default:
philpem@59 974 IoWrite(address, value, 8);
philpem@40 975 }
philpem@59 976 } else {
philpem@59 977 IoWrite(address, value, 8);
philpem@40 978 }
philpem@59 979 }/*}}}*/
philpem@40 980
philpem@40 981
philpem@40 982 // for the disassembler
philpem@40 983 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
philpem@40 984 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
philpem@40 985 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }
philpem@40 986