src/main.c

Thu, 02 Dec 2010 02:43:49 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Thu, 02 Dec 2010 02:43:49 +0000
changeset 30
3190629004b2
parent 29
d73d07c1d492
child 32
a44afcf2354c
permissions
-rw-r--r--

add routines for memory access checking

philpem@0 1 #include <stdio.h>
philpem@7 2 #include <stdlib.h>
philpem@4 3 #include <stdint.h>
philpem@7 4 #include <stdbool.h>
philpem@7 5 #include <malloc.h>
philpem@7 6 #include <string.h>
philpem@18 7
philpem@20 8 #include "SDL.h"
philpem@20 9
philpem@4 10 #include "musashi/m68k.h"
philpem@7 11 #include "version.h"
philpem@18 12 #include "state.h"
philpem@7 13
philpem@7 14 void FAIL(char *err)
philpem@7 15 {
philpem@7 16 state_done();
philpem@7 17 fprintf(stderr, "ERROR: %s\nExiting...\n", err);
philpem@7 18 exit(EXIT_FAILURE);
philpem@7 19 }
philpem@7 20
philpem@26 21 /***********************************
philpem@26 22 * Array read/write utility macros
philpem@26 23 * "Don't Repeat Yourself" :)
philpem@26 24 ***********************************/
philpem@26 25
philpem@26 26 /// Array read, 32-bit
philpem@26 27 #define RD32(array, address, andmask) \
philpem@26 28 (((uint32_t)array[(address + 0) & (andmask)] << 24) | \
philpem@26 29 ((uint32_t)array[(address + 1) & (andmask)] << 16) | \
philpem@26 30 ((uint32_t)array[(address + 2) & (andmask)] << 8) | \
philpem@26 31 ((uint32_t)array[(address + 3) & (andmask)]))
philpem@26 32
philpem@26 33 /// Array read, 16-bit
philpem@26 34 #define RD16(array, address, andmask) \
philpem@26 35 (((uint32_t)array[(address + 0) & (andmask)] << 8) | \
philpem@26 36 ((uint32_t)array[(address + 1) & (andmask)]))
philpem@26 37
philpem@26 38 /// Array read, 8-bit
philpem@26 39 #define RD8(array, address, andmask) \
philpem@26 40 ((uint32_t)array[(address + 0) & (andmask)])
philpem@26 41
philpem@26 42 /// Array write, 32-bit
philpem@26 43 #define WR32(array, address, andmask, value) { \
philpem@26 44 array[(address + 0) & (andmask)] = (value >> 24) & 0xff; \
philpem@26 45 array[(address + 1) & (andmask)] = (value >> 16) & 0xff; \
philpem@26 46 array[(address + 2) & (andmask)] = (value >> 8) & 0xff; \
philpem@26 47 array[(address + 3) & (andmask)] = value & 0xff; \
philpem@26 48 }
philpem@26 49
philpem@26 50 /// Array write, 16-bit
philpem@26 51 #define WR16(array, address, andmask, value) { \
philpem@26 52 array[(address + 0) & (andmask)] = (value >> 8) & 0xff; \
philpem@26 53 array[(address + 1) & (andmask)] = value & 0xff; \
philpem@26 54 }
philpem@26 55
philpem@26 56 /// Array write, 8-bit
philpem@26 57 #define WR8(array, address, andmask, value) \
philpem@26 58 array[(address + 0) & (andmask)] = value & 0xff;
philpem@26 59
philpem@30 60 /******************
philpem@30 61 * Memory mapping
philpem@30 62 ******************/
philpem@30 63
philpem@30 64 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
philpem@30 65
philpem@30 66 uint32_t mapAddr(uint32_t addr, bool writing)
philpem@30 67 {
philpem@30 68 if (addr < 0x400000) {
philpem@30 69 // RAM access. Check against the Map RAM
philpem@30 70 // Start by getting the original page address
philpem@30 71 uint16_t page = (addr >> 12) & 0x3FF;
philpem@30 72
philpem@30 73 // Look it up in the map RAM and get the physical page address
philpem@30 74 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@30 75
philpem@30 76 // Update the Page Status bits
philpem@30 77 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
philpem@30 78 if (pagebits != 0) {
philpem@30 79 if (writing)
philpem@30 80 state.map[addr*2] |= 0x60; // Page written to (dirty)
philpem@30 81 else
philpem@30 82 state.map[addr*2] |= 0x40; // Page accessed but not written
philpem@30 83 }
philpem@30 84
philpem@30 85 // Return the address with the new physical page spliced in
philpem@30 86 return (new_page_addr << 12) + (addr & 0xFFF);
philpem@30 87 } else {
philpem@30 88 // I/O, VRAM or MapRAM space; no mapping is performed or required
philpem@30 89 // TODO: assert here?
philpem@30 90 return addr;
philpem@30 91 }
philpem@30 92 }
philpem@30 93
philpem@30 94 typedef enum {
philpem@30 95 MEM_ALLOWED = 0,
philpem@30 96 MEM_PAGEFAULT, // Page fault -- page not present
philpem@30 97 MEM_PAGE_NO_WE, // Page not write enabled
philpem@30 98 MEM_KERNEL, // User attempted to access kernel memory
philpem@30 99 MEM_UIE // User Nonmemory Location Access
philpem@30 100 } MEM_STATUS;
philpem@30 101
philpem@30 102 // check memory access permissions
philpem@30 103 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)
philpem@30 104 {
philpem@30 105 // Are we in Supervisor mode?
philpem@30 106 if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
philpem@30 107 // Yes. We can do anything we like.
philpem@30 108 return MEM_ALLOWED;
philpem@30 109
philpem@30 110 // If we're here, then we must be in User mode.
philpem@30 111 // Check that the user didn't access memory outside of the RAM area
philpem@30 112 if (addr >= 0x400000)
philpem@30 113 return MEM_UIE;
philpem@30 114
philpem@30 115 // This leaves us with Page Fault checking. Get the page bits for this page.
philpem@30 116 uint16_t page = (addr >> 12) & 0x3FF;
philpem@30 117 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
philpem@30 118
philpem@30 119 // Check page is present
philpem@30 120 if ((pagebits & 0x03) == 0)
philpem@30 121 return MEM_PAGEFAULT;
philpem@30 122
philpem@30 123 // User attempt to access the kernel
philpem@30 124 // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
philpem@30 125 if (((addr >> 19) & 0x0F) == 0)
philpem@30 126 return MEM_KERNEL;
philpem@30 127
philpem@30 128 // Check page is write enabled
philpem@30 129 if ((pagebits & 0x04) == 0)
philpem@30 130 return MEM_PAGE_NO_WE;
philpem@30 131
philpem@30 132 // Page access allowed.
philpem@30 133 return MEM_ALLOWED;
philpem@30 134 }
philpem@30 135
philpem@30 136 #undef MAPRAM
philpem@26 137
philpem@26 138 /********************************************************
philpem@26 139 * m68k memory read/write support functions for Musashi
philpem@26 140 ********************************************************/
philpem@26 141
philpem@4 142 // read m68k memory
philpem@4 143 uint32_t m68k_read_memory_32(uint32_t address)
philpem@4 144 {
philpem@9 145 uint32_t data = 0xFFFFFFFF;
philpem@9 146
philpem@7 147 // If ROMLMAP is set, force system to access ROM
philpem@7 148 if (!state.romlmap)
philpem@7 149 address |= 0x800000;
philpem@7 150
philpem@9 151 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@7 152 // ROM access
philpem@26 153 data = RD32(state.rom, address, ROM_SIZE - 1);
philpem@26 154 } else if (address <= (state.ram_size - 1)) {
philpem@27 155 // RAM access -- TODO: mapping
philpem@26 156 data = RD32(state.ram, address, state.ram_size - 1);
philpem@24 157 } else if ((address >= 0x420000) && (address <= 0x427FFF)) {
philpem@27 158 // VRAM access
philpem@26 159 data = RD32(state.vram, address, 0x7FFF);
philpem@27 160 } else if ((address >= 0x400000) && (address <= 0x4007FF)) {
philpem@27 161 // Map RAM access
philpem@27 162 data = RD32(state.map, address, 0x7FF);
philpem@21 163 } else {
philpem@21 164 // I/O register -- TODO
philpem@29 165 printf("RD32 0x%08X ==> ??? %s\n", address, m68k_get_reg(NULL, M68K_REG_SR) & 0x2000 ? "[SV]" : "");
philpem@7 166 }
philpem@9 167 return data;
philpem@4 168 }
philpem@4 169
philpem@4 170 uint32_t m68k_read_memory_16(uint32_t address)
philpem@4 171 {
philpem@9 172 uint16_t data = 0xFFFF;
philpem@9 173
philpem@9 174 // If ROMLMAP is set, force system to access ROM
philpem@9 175 if (!state.romlmap)
philpem@9 176 address |= 0x800000;
philpem@9 177
philpem@10 178 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@10 179 // ROM access
philpem@26 180 data = RD16(state.rom, address, ROM_SIZE - 1);
philpem@26 181 } else if (address <= (state.ram_size - 1)) {
philpem@27 182 // RAM access -- TODO: mapping
philpem@26 183 data = RD16(state.ram, address, state.ram_size - 1);
philpem@24 184 } else if ((address >= 0x420000) && (address <= 0x427FFF)) {
philpem@27 185 // VRAM access
philpem@26 186 data = RD16(state.vram, address, 0x7FFF);
philpem@27 187 } else if ((address >= 0x400000) && (address <= 0x4007FF)) {
philpem@27 188 // Map RAM access
philpem@27 189 data = RD16(state.map, address, 0x7FF);
philpem@21 190 } else {
philpem@21 191 // I/O register -- TODO
philpem@29 192 printf("RD16 0x%08X ==> ??? %s\n", address, m68k_get_reg(NULL, M68K_REG_SR) & 0x2000 ? "[SV]" : "");
philpem@10 193 }
philpem@9 194
philpem@9 195 return data;
philpem@4 196 }
philpem@4 197
philpem@4 198 uint32_t m68k_read_memory_8(uint32_t address)
philpem@4 199 {
philpem@9 200 uint8_t data = 0xFF;
philpem@9 201
philpem@7 202 // If ROMLMAP is set, force system to access ROM
philpem@7 203 if (!state.romlmap)
philpem@7 204 address |= 0x800000;
philpem@7 205
philpem@10 206 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@10 207 // ROM access
philpem@26 208 data = RD8(state.rom, address, ROM_SIZE - 1);
philpem@26 209 } else if (address <= (state.ram_size - 1)) {
philpem@27 210 // RAM access -- TODO: mapping
philpem@26 211 data = RD8(state.ram, address, state.ram_size - 1);
philpem@24 212 } else if ((address >= 0x420000) && (address <= 0x427FFF)) {
philpem@27 213 // VRAM access
philpem@26 214 data = RD8(state.vram, address, 0x7FFF);
philpem@27 215 } else if ((address >= 0x400000) && (address <= 0x4007FF)) {
philpem@27 216 // Map RAM access
philpem@27 217 data = RD8(state.map, address, 0x7FF);
philpem@21 218 } else {
philpem@21 219 // I/O register -- TODO
philpem@29 220 printf("RD08 0x%08X ==> ??? %s\n", address, m68k_get_reg(NULL, M68K_REG_SR) & 0x2000 ? "[SV]" : "");
philpem@10 221 }
philpem@9 222
philpem@9 223 return data;
philpem@4 224 }
philpem@4 225
philpem@4 226 // write m68k memory
philpem@4 227 void m68k_write_memory_32(uint32_t address, uint32_t value)
philpem@4 228 {
philpem@7 229 // If ROMLMAP is set, force system to access ROM
philpem@7 230 if (!state.romlmap)
philpem@7 231 address |= 0x800000;
philpem@7 232
philpem@9 233 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@7 234 // ROM access
philpem@7 235 // TODO: bus error here? can't write to rom!
philpem@26 236 } else if (address <= (state.ram_size - 1)) {
philpem@27 237 // RAM -- TODO: mapping
philpem@26 238 WR32(state.ram, address, state.ram_size - 1, value);
philpem@24 239 } else if ((address >= 0x420000) && (address <= 0x427FFF)) {
philpem@24 240 // VRAM access
philpem@26 241 WR32(state.vram, address, 0x7fff, value);
philpem@27 242 } else if ((address >= 0x400000) && (address <= 0x4007FF)) {
philpem@27 243 // Map RAM access
philpem@27 244 WR32(state.map, address, 0x7FF, value);
philpem@9 245 } else {
philpem@9 246 switch (address) {
philpem@21 247 case 0xE43000: state.romlmap = ((value & 0x8000) == 0x8000); break; // GCR3: ROMLMAP
philpem@29 248 default: printf("WR32 0x%08X ==> 0x%08X %s\n", address, value, m68k_get_reg(NULL, M68K_REG_SR) & 0x2000 ? "[SV]" : ""); break;
philpem@9 249 }
philpem@7 250 }
philpem@4 251 }
philpem@4 252
philpem@4 253 void m68k_write_memory_16(uint32_t address, uint32_t value)
philpem@4 254 {
philpem@7 255 // If ROMLMAP is set, force system to access ROM
philpem@7 256 if (!state.romlmap)
philpem@7 257 address |= 0x800000;
philpem@7 258
philpem@9 259 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@7 260 // ROM access
philpem@7 261 // TODO: bus error here? can't write to rom!
philpem@26 262 } else if (address <= (state.ram_size - 1)) {
philpem@27 263 // RAM access -- TODO: mapping
philpem@26 264 WR16(state.ram, address, state.ram_size - 1, value);
philpem@24 265 } else if ((address >= 0x420000) && (address <= 0x427FFF)) {
philpem@24 266 // VRAM access
philpem@26 267 WR16(state.vram, address, 0x7fff, value);
philpem@27 268 } else if ((address >= 0x400000) && (address <= 0x4007FF)) {
philpem@27 269 // Map RAM access
philpem@27 270 WR16(state.map, address, 0x7FF, value);
philpem@9 271 } else {
philpem@9 272 switch (address) {
philpem@21 273 case 0xE43000: state.romlmap = ((value & 0x8000) == 0x8000); break; // GCR3: ROMLMAP
philpem@29 274 default: printf("WR16 0x%08X ==> 0x%04X %s\n", address, value, m68k_get_reg(NULL, M68K_REG_SR) & 0x2000 ? "[SV]" : ""); break;
philpem@9 275 }
philpem@25 276 if (address == 0x4A0000) {
philpem@25 277 printf("\tLED WRITE: %s %s %s %s\n",
philpem@25 278 value & 0x800 ? "-" : "R",
philpem@25 279 value & 0x400 ? "-" : "G",
philpem@25 280 value & 0x200 ? "-" : "Y",
philpem@25 281 value & 0x100 ? "-" : "R"
philpem@25 282 );
philpem@25 283 }
philpem@7 284 }
philpem@4 285 }
philpem@4 286
philpem@4 287 void m68k_write_memory_8(uint32_t address, uint32_t value)
philpem@4 288 {
philpem@7 289 // If ROMLMAP is set, force system to access ROM
philpem@7 290 if (!state.romlmap)
philpem@7 291 address |= 0x800000;
philpem@7 292
philpem@9 293 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@7 294 // ROM access
philpem@7 295 // TODO: bus error here? can't write to rom!
philpem@26 296 } else if (address <= (state.ram_size - 1)) {
philpem@27 297 // RAM access -- TODO: mapping
philpem@26 298 WR8(state.ram, address, state.ram_size - 1, value);
philpem@24 299 } else if ((address >= 0x420000) && (address <= 0x427FFF)) {
philpem@24 300 // VRAM access
philpem@26 301 WR8(state.vram, address, 0x7fff, value);
philpem@27 302 } else if ((address >= 0x400000) && (address <= 0x4007FF)) {
philpem@27 303 // Map RAM access
philpem@27 304 WR8(state.map, address, 0x7FF, value);
philpem@9 305 } else {
philpem@9 306 switch (address) {
philpem@21 307 case 0xE43000: state.romlmap = ((value & 0x80) == 0x80); break; // GCR3: ROMLMAP
philpem@29 308 default: printf("WR08 0x%08X ==> 0x%02X %s\n", address, value, m68k_get_reg(NULL, M68K_REG_SR) & 0x2000 ? "[SV]" : ""); break;
philpem@9 309 }
philpem@7 310 }
philpem@4 311 }
philpem@4 312
philpem@10 313 // for the disassembler
philpem@9 314 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
philpem@9 315 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
philpem@9 316 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }
philpem@9 317
philpem@27 318
philpem@27 319 /****************************
philpem@27 320 * blessed be thy main()...
philpem@27 321 ****************************/
philpem@27 322
philpem@0 323 int main(void)
philpem@0 324 {
philpem@7 325 // copyright banner
philpem@16 326 printf("FreeBee: A Quick-and-Dirty AT&T 3B1 Emulator. Version %s, %s mode.\n", VER_FULLSTR, VER_BUILD_TYPE);
philpem@17 327 printf("Copyright (C) 2010 P. A. Pemberton. All rights reserved.\nLicensed under the Apache License Version 2.0.\n");
philpem@17 328 printf("Musashi M680x0 emulator engine developed by Karl Stenerud <kstenerud@gmail.com>\n");
philpem@16 329 printf("Built %s by %s@%s.\n", VER_COMPILE_DATETIME, VER_COMPILE_BY, VER_COMPILE_HOST);
philpem@16 330 printf("Compiler: %s\n", VER_COMPILER);
philpem@16 331 printf("CFLAGS: %s\n", VER_CFLAGS);
philpem@17 332 printf("\n");
philpem@7 333
philpem@7 334 // set up system state
philpem@7 335 // 512K of RAM
philpem@18 336 state_init(512*1024);
philpem@7 337
philpem@20 338 // set up musashi and reset the CPU
philpem@7 339 m68k_set_cpu_type(M68K_CPU_TYPE_68010);
philpem@7 340 m68k_pulse_reset();
philpem@9 341
philpem@28 342 // Set up SDL
philpem@20 343 if (SDL_Init(SDL_INIT_VIDEO | SDL_INIT_TIMER) == -1) {
philpem@20 344 printf("Could not initialise SDL: %s.\n", SDL_GetError());
philpem@28 345 exit(EXIT_FAILURE);
philpem@20 346 }
philpem@7 347
philpem@28 348 // Make sure SDL cleans up after itself
philpem@28 349 atexit(SDL_Quit);
philpem@28 350
philpem@28 351 // Set up the video display
philpem@28 352 SDL_Surface *screen = NULL;
philpem@28 353 if ((screen = SDL_SetVideoMode(720, 384, 8, SDL_SWSURFACE | SDL_ANYFORMAT)) == NULL) {
philpem@28 354 printf("Could not find a suitable video mode: %s.\n", SDL_GetError());
philpem@28 355 exit(EXIT_FAILURE);
philpem@28 356 }
philpem@28 357 printf("Set %dx%d at %d bits-per-pixel mode\n", screen->w, screen->h, screen->format->BitsPerPixel);
philpem@28 358 SDL_WM_SetCaption("FreeBee 3B1 emulator", "FreeBee");
philpem@28 359
philpem@20 360 /***
philpem@20 361 * The 3B1 CPU runs at 10MHz, with DMA running at 1MHz and video refreshing at
philpem@20 362 * around 60Hz (???), with a 60Hz periodic interrupt.
philpem@20 363 */
philpem@20 364 const uint32_t TIMESLOT_FREQUENCY = 240; // Hz
philpem@20 365 const uint32_t MILLISECS_PER_TIMESLOT = 1e3 / TIMESLOT_FREQUENCY;
philpem@20 366 const uint32_t CLOCKS_PER_60HZ = (10e6 / 60);
philpem@20 367 uint32_t next_timeslot = SDL_GetTicks() + MILLISECS_PER_TIMESLOT;
philpem@20 368 uint32_t clock_cycles = 0;
philpem@16 369 bool exitEmu = false;
philpem@16 370 for (;;) {
philpem@20 371 // Run the CPU for however many cycles we need to. CPU core clock is
philpem@20 372 // 10MHz, and we're running at 240Hz/timeslot. Thus: 10e6/240 or
philpem@20 373 // 41667 cycles per timeslot.
philpem@20 374 clock_cycles += m68k_execute(10e6/TIMESLOT_FREQUENCY);
philpem@20 375
philpem@20 376 // TODO: run DMA here
philpem@16 377
philpem@20 378 // Is it time to run the 60Hz periodic interrupt yet?
philpem@20 379 if (clock_cycles > CLOCKS_PER_60HZ) {
philpem@20 380 // TODO: refresh screen
philpem@20 381 // TODO: trigger periodic interrupt (if enabled)
philpem@20 382 // decrement clock cycle counter, we've handled the intr.
philpem@20 383 clock_cycles -= CLOCKS_PER_60HZ;
philpem@16 384 }
philpem@16 385
philpem@20 386 // make sure frame rate is equal to real time
philpem@20 387 uint32_t now = SDL_GetTicks();
philpem@20 388 if (now < next_timeslot) {
philpem@20 389 // timeslot finished early -- eat up some time
philpem@20 390 SDL_Delay(next_timeslot - now);
philpem@20 391 } else {
philpem@20 392 // timeslot finished late -- skip ahead to gain time
philpem@20 393 // TODO: if this happens a lot, we should let the user know
philpem@20 394 // that their PC might not be fast enough...
philpem@20 395 next_timeslot = now;
philpem@20 396 }
philpem@20 397 // advance to the next timeslot
philpem@20 398 next_timeslot += MILLISECS_PER_TIMESLOT;
philpem@20 399
philpem@20 400 // if we've been asked to exit the emulator, then do so.
philpem@16 401 if (exitEmu) break;
philpem@16 402 }
philpem@7 403
philpem@7 404 // shut down and exit
philpem@20 405 SDL_Quit();
philpem@7 406
philpem@0 407 return 0;
philpem@0 408 }