Fri, 04 Mar 2011 01:37:42 +0000
fix small typos in WriteMem32
WriteMem32 warnings for writes to MapRAM and VRAM mirrors were incorrectly declaring themselves as read operations.
philpem@40 | 1 | #include <stdio.h> |
philpem@40 | 2 | #include <stdlib.h> |
philpem@40 | 3 | #include <stdint.h> |
philpem@40 | 4 | #include <stdbool.h> |
philpem@59 | 5 | #include <assert.h> |
philpem@40 | 6 | #include "musashi/m68k.h" |
philpem@40 | 7 | #include "state.h" |
philpem@100 | 8 | #include "utils.h" |
philpem@40 | 9 | #include "memory.h" |
philpem@40 | 10 | |
philpem@40 | 11 | /****************** |
philpem@40 | 12 | * Memory mapping |
philpem@40 | 13 | ******************/ |
philpem@40 | 14 | |
philpem@40 | 15 | #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1])) |
philpem@40 | 16 | |
philpem@59 | 17 | uint32_t mapAddr(uint32_t addr, bool writing)/*{{{*/ |
philpem@40 | 18 | { |
philpem@40 | 19 | if (addr < 0x400000) { |
philpem@40 | 20 | // RAM access. Check against the Map RAM |
philpem@40 | 21 | // Start by getting the original page address |
philpem@40 | 22 | uint16_t page = (addr >> 12) & 0x3FF; |
philpem@40 | 23 | |
philpem@40 | 24 | // Look it up in the map RAM and get the physical page address |
philpem@40 | 25 | uint32_t new_page_addr = MAPRAM(page) & 0x3FF; |
philpem@40 | 26 | |
philpem@40 | 27 | // Update the Page Status bits |
philpem@40 | 28 | uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03; |
philpem@100 | 29 | // Pagebits -- |
philpem@100 | 30 | // 0 = not present |
philpem@100 | 31 | // 1 = present but not accessed |
philpem@100 | 32 | // 2 = present, accessed (read from) |
philpem@100 | 33 | // 3 = present, dirty (written to) |
philpem@100 | 34 | switch (pagebits) { |
philpem@100 | 35 | case 0: |
philpem@100 | 36 | // Page not present |
philpem@100 | 37 | // This should cause a page fault |
philpem@100 | 38 | LOGS("Whoa! Pagebit update, when the page is not present!"); |
philpem@100 | 39 | break; |
philpem@100 | 40 | |
philpem@100 | 41 | case 1: |
philpem@100 | 42 | // Page present -- first access |
philpem@104 | 43 | state.map[page*2] &= 0x9F; // turn off "present" bit (but not write enable!) |
philpem@100 | 44 | if (writing) |
philpem@100 | 45 | state.map[page*2] |= 0x60; // Page written to (dirty) |
philpem@100 | 46 | else |
philpem@100 | 47 | state.map[page*2] |= 0x40; // Page accessed but not written |
philpem@100 | 48 | break; |
philpem@100 | 49 | |
philpem@100 | 50 | case 2: |
philpem@100 | 51 | case 3: |
philpem@100 | 52 | // Page present, 2nd or later access |
philpem@100 | 53 | if (writing) |
philpem@100 | 54 | state.map[page*2] |= 0x60; // Page written to (dirty) |
philpem@100 | 55 | break; |
philpem@40 | 56 | } |
philpem@40 | 57 | |
philpem@40 | 58 | // Return the address with the new physical page spliced in |
philpem@40 | 59 | return (new_page_addr << 12) + (addr & 0xFFF); |
philpem@40 | 60 | } else { |
philpem@40 | 61 | // I/O, VRAM or MapRAM space; no mapping is performed or required |
philpem@40 | 62 | // TODO: assert here? |
philpem@40 | 63 | return addr; |
philpem@40 | 64 | } |
philpem@59 | 65 | }/*}}}*/ |
philpem@40 | 66 | |
philpem@59 | 67 | MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)/*{{{*/ |
philpem@40 | 68 | { |
philpem@104 | 69 | // Get the page bits for this page. |
philpem@104 | 70 | uint16_t page = (addr >> 12) & 0x3FF; |
philpem@104 | 71 | uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07; |
philpem@104 | 72 | |
philpem@104 | 73 | // Check page is present (but only for RAM zone) |
philpem@104 | 74 | if ((addr < 0x400000) && ((pagebits & 0x03) == 0)) { |
philpem@104 | 75 | LOG("Page not mapped in: addr %08X, page %04X, mapbits %04X", addr, page, MAPRAM(page)); |
philpem@104 | 76 | return MEM_PAGEFAULT; |
philpem@104 | 77 | } |
philpem@104 | 78 | |
philpem@40 | 79 | // Are we in Supervisor mode? |
philpem@40 | 80 | if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000) |
philpem@40 | 81 | // Yes. We can do anything we like. |
philpem@40 | 82 | return MEM_ALLOWED; |
philpem@40 | 83 | |
philpem@40 | 84 | // If we're here, then we must be in User mode. |
philpem@40 | 85 | // Check that the user didn't access memory outside of the RAM area |
philpem@40 | 86 | if (addr >= 0x400000) |
philpem@40 | 87 | return MEM_UIE; |
philpem@40 | 88 | |
philpem@40 | 89 | // User attempt to access the kernel |
philpem@40 | 90 | // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode |
philpem@40 | 91 | if (((addr >> 19) & 0x0F) == 0) |
philpem@40 | 92 | return MEM_KERNEL; |
philpem@40 | 93 | |
philpem@40 | 94 | // Check page is write enabled |
philpem@68 | 95 | if (writing && ((pagebits & 0x04) == 0)) |
philpem@40 | 96 | return MEM_PAGE_NO_WE; |
philpem@40 | 97 | |
philpem@40 | 98 | // Page access allowed. |
philpem@40 | 99 | return MEM_ALLOWED; |
philpem@59 | 100 | }/*}}}*/ |
philpem@40 | 101 | |
philpem@40 | 102 | #undef MAPRAM |
philpem@40 | 103 | |
philpem@40 | 104 | |
philpem@40 | 105 | /******************************************************** |
philpem@40 | 106 | * m68k memory read/write support functions for Musashi |
philpem@40 | 107 | ********************************************************/ |
philpem@40 | 108 | |
philpem@40 | 109 | /** |
philpem@40 | 110 | * @brief Check memory access permissions for a write operation. |
philpem@40 | 111 | * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but |
philpem@40 | 112 | * gcc throws warnings when you have a return-with-value in a void |
philpem@40 | 113 | * function, even if the return-with-value is completely unreachable. |
philpem@40 | 114 | * Similarly it doesn't like it if you have a return without a value |
philpem@40 | 115 | * in a non-void function, even if it's impossible to ever reach the |
philpem@40 | 116 | * return-with-no-value. UGH! |
philpem@40 | 117 | */ |
philpem@59 | 118 | /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/ |
philpem@59 | 119 | #define ACCESS_CHECK_WR(address, bits) \ |
philpem@59 | 120 | do { \ |
philpem@40 | 121 | bool fault = false; \ |
philpem@103 | 122 | MEM_STATUS st; \ |
philpem@103 | 123 | switch (st = checkMemoryAccess(address, true)) { \ |
philpem@40 | 124 | case MEM_ALLOWED: \ |
philpem@40 | 125 | /* Access allowed */ \ |
philpem@40 | 126 | break; \ |
philpem@40 | 127 | case MEM_PAGEFAULT: \ |
philpem@40 | 128 | /* Page fault */ \ |
philpem@44 | 129 | state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0); \ |
philpem@40 | 130 | fault = true; \ |
philpem@40 | 131 | break; \ |
philpem@40 | 132 | case MEM_UIE: \ |
philpem@40 | 133 | /* User access to memory above 4MB */ \ |
philpem@44 | 134 | state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0); \ |
philpem@40 | 135 | fault = true; \ |
philpem@40 | 136 | break; \ |
philpem@40 | 137 | case MEM_KERNEL: \ |
philpem@40 | 138 | case MEM_PAGE_NO_WE: \ |
philpem@40 | 139 | /* kernel access or page not write enabled */ \ |
philpem@68 | 140 | /* FIXME: which regs need setting? */ \ |
philpem@40 | 141 | fault = true; \ |
philpem@40 | 142 | break; \ |
philpem@40 | 143 | } \ |
philpem@40 | 144 | \ |
philpem@40 | 145 | if (fault) { \ |
philpem@40 | 146 | if (bits >= 16) \ |
philpem@68 | 147 | state.bsr0 = 0x7C00; \ |
philpem@40 | 148 | else \ |
philpem@40 | 149 | state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \ |
philpem@40 | 150 | state.bsr0 |= (address >> 16); \ |
philpem@40 | 151 | state.bsr1 = address & 0xffff; \ |
philpem@103 | 152 | LOG("Bus Error while writing, addr %08X, statcode %d", address, st); \ |
philpem@103 | 153 | if (state.ee) m68k_pulse_bus_error(); \ |
philpem@40 | 154 | return; \ |
philpem@40 | 155 | } \ |
philpem@70 | 156 | } while (0) |
philpem@59 | 157 | /*}}}*/ |
philpem@40 | 158 | |
philpem@40 | 159 | /** |
philpem@40 | 160 | * @brief Check memory access permissions for a read operation. |
philpem@40 | 161 | * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but |
philpem@40 | 162 | * gcc throws warnings when you have a return-with-value in a void |
philpem@40 | 163 | * function, even if the return-with-value is completely unreachable. |
philpem@40 | 164 | * Similarly it doesn't like it if you have a return without a value |
philpem@40 | 165 | * in a non-void function, even if it's impossible to ever reach the |
philpem@40 | 166 | * return-with-no-value. UGH! |
philpem@40 | 167 | */ |
philpem@59 | 168 | /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/ |
philpem@59 | 169 | #define ACCESS_CHECK_RD(address, bits) \ |
philpem@59 | 170 | do { \ |
philpem@40 | 171 | bool fault = false; \ |
philpem@103 | 172 | MEM_STATUS st; \ |
philpem@103 | 173 | switch (st = checkMemoryAccess(address, false)) { \ |
philpem@40 | 174 | case MEM_ALLOWED: \ |
philpem@40 | 175 | /* Access allowed */ \ |
philpem@40 | 176 | break; \ |
philpem@40 | 177 | case MEM_PAGEFAULT: \ |
philpem@40 | 178 | /* Page fault */ \ |
philpem@44 | 179 | state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0); \ |
philpem@40 | 180 | fault = true; \ |
philpem@40 | 181 | break; \ |
philpem@40 | 182 | case MEM_UIE: \ |
philpem@40 | 183 | /* User access to memory above 4MB */ \ |
philpem@44 | 184 | state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0); \ |
philpem@40 | 185 | fault = true; \ |
philpem@40 | 186 | break; \ |
philpem@40 | 187 | case MEM_KERNEL: \ |
philpem@40 | 188 | case MEM_PAGE_NO_WE: \ |
philpem@40 | 189 | /* kernel access or page not write enabled */ \ |
philpem@68 | 190 | /* FIXME: which regs need setting? */ \ |
philpem@40 | 191 | fault = true; \ |
philpem@40 | 192 | break; \ |
philpem@40 | 193 | } \ |
philpem@40 | 194 | \ |
philpem@40 | 195 | if (fault) { \ |
philpem@40 | 196 | if (bits >= 16) \ |
philpem@68 | 197 | state.bsr0 = 0x7C00; \ |
philpem@40 | 198 | else \ |
philpem@40 | 199 | state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \ |
philpem@40 | 200 | state.bsr0 |= (address >> 16); \ |
philpem@40 | 201 | state.bsr1 = address & 0xffff; \ |
philpem@103 | 202 | LOG("Bus Error while reading, addr %08X, statcode %d", address, st); \ |
philpem@103 | 203 | if (state.ee) m68k_pulse_bus_error(); \ |
philpem@40 | 204 | return 0xFFFFFFFF; \ |
philpem@40 | 205 | } \ |
philpem@70 | 206 | } while (0) |
philpem@59 | 207 | /*}}}*/ |
philpem@40 | 208 | |
philpem@40 | 209 | // Logging macros |
philpem@59 | 210 | #define LOG_NOT_HANDLED_R(bits) \ |
philpem@64 | 211 | if (!handled) printf("unhandled read%02d, addr=0x%08X\n", bits, address); |
philpem@40 | 212 | |
philpem@59 | 213 | #define LOG_NOT_HANDLED_W(bits) \ |
philpem@64 | 214 | if (!handled) printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data); |
philpem@59 | 215 | |
philpem@59 | 216 | /******************************************************** |
philpem@59 | 217 | * I/O read/write functions |
philpem@59 | 218 | ********************************************************/ |
philpem@40 | 219 | |
philpem@40 | 220 | /** |
philpem@59 | 221 | * Issue a warning if a read operation is made with an invalid size |
philpem@40 | 222 | */ |
philpem@66 | 223 | inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname) |
philpem@40 | 224 | { |
philpem@59 | 225 | assert((bits == 8) || (bits == 16) || (bits == 32)); |
philpem@59 | 226 | if ((bits & allowed) == 0) { |
philpem@66 | 227 | printf("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits); |
philpem@59 | 228 | } |
philpem@59 | 229 | } |
philpem@59 | 230 | |
philpem@66 | 231 | inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname) |
philpem@40 | 232 | { |
philpem@66 | 233 | ENFORCE_SIZE(bits, address, true, allowed, regname); |
philpem@66 | 234 | } |
philpem@66 | 235 | |
philpem@66 | 236 | inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname) |
philpem@66 | 237 | { |
philpem@66 | 238 | ENFORCE_SIZE(bits, address, false, allowed, regname); |
philpem@66 | 239 | } |
philpem@66 | 240 | |
philpem@59 | 241 | void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/ |
philpem@59 | 242 | { |
philpem@40 | 243 | bool handled = false; |
philpem@40 | 244 | |
philpem@59 | 245 | if ((address >= 0x400000) && (address <= 0x7FFFFF)) { |
philpem@40 | 246 | // I/O register space, zone A |
philpem@40 | 247 | switch (address & 0x0F0000) { |
philpem@40 | 248 | case 0x010000: // General Status Register |
philpem@59 | 249 | if (bits == 16) |
philpem@59 | 250 | state.genstat = (data & 0xffff); |
philpem@59 | 251 | else if (bits == 8) { |
philpem@59 | 252 | if (address & 0) |
philpem@59 | 253 | state.genstat = data; |
philpem@59 | 254 | else |
philpem@59 | 255 | state.genstat = data << 8; |
philpem@59 | 256 | } |
philpem@40 | 257 | handled = true; |
philpem@40 | 258 | break; |
philpem@40 | 259 | case 0x030000: // Bus Status Register 0 |
philpem@40 | 260 | break; |
philpem@40 | 261 | case 0x040000: // Bus Status Register 1 |
philpem@40 | 262 | break; |
philpem@40 | 263 | case 0x050000: // Phone status |
philpem@40 | 264 | break; |
philpem@40 | 265 | case 0x060000: // DMA Count |
philpem@66 | 266 | ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT"); |
philpem@59 | 267 | state.dma_count = (data & 0x3FFF); |
philpem@59 | 268 | state.idmarw = ((data & 0x4000) == 0x4000); |
philpem@59 | 269 | state.dmaen = ((data & 0x8000) == 0x8000); |
philpem@59 | 270 | // This handles the "dummy DMA transfer" mentioned in the docs |
philpem@59 | 271 | // TODO: access check, peripheral access |
philpem@59 | 272 | if (!state.idmarw) |
philpem@60 | 273 | WR32(state.base_ram, mapAddr(address, true), state.base_ram_size - 1, 0xDEAD); |
philpem@59 | 274 | state.dma_count++; |
philpem@53 | 275 | handled = true; |
philpem@40 | 276 | break; |
philpem@40 | 277 | case 0x070000: // Line Printer Status Register |
philpem@40 | 278 | break; |
philpem@40 | 279 | case 0x080000: // Real Time Clock |
philpem@40 | 280 | break; |
philpem@40 | 281 | case 0x090000: // Phone registers |
philpem@40 | 282 | switch (address & 0x0FF000) { |
philpem@40 | 283 | case 0x090000: // Handset relay |
philpem@40 | 284 | case 0x098000: |
philpem@40 | 285 | break; |
philpem@40 | 286 | case 0x091000: // Line select 2 |
philpem@40 | 287 | case 0x099000: |
philpem@40 | 288 | break; |
philpem@40 | 289 | case 0x092000: // Hook relay 1 |
philpem@40 | 290 | case 0x09A000: |
philpem@40 | 291 | break; |
philpem@40 | 292 | case 0x093000: // Hook relay 2 |
philpem@40 | 293 | case 0x09B000: |
philpem@40 | 294 | break; |
philpem@40 | 295 | case 0x094000: // Line 1 hold |
philpem@40 | 296 | case 0x09C000: |
philpem@40 | 297 | break; |
philpem@40 | 298 | case 0x095000: // Line 2 hold |
philpem@40 | 299 | case 0x09D000: |
philpem@40 | 300 | break; |
philpem@40 | 301 | case 0x096000: // Line 1 A-lead |
philpem@40 | 302 | case 0x09E000: |
philpem@40 | 303 | break; |
philpem@40 | 304 | case 0x097000: // Line 2 A-lead |
philpem@40 | 305 | case 0x09F000: |
philpem@40 | 306 | break; |
philpem@40 | 307 | } |
philpem@40 | 308 | break; |
philpem@59 | 309 | case 0x0A0000: // Miscellaneous Control Register |
philpem@66 | 310 | ENFORCE_SIZE_W(bits, address, 16, "MISCCON"); |
philpem@59 | 311 | // TODO: handle the ctrl bits properly |
philpem@59 | 312 | // TODO: &0x8000 --> dismiss 60hz intr |
philpem@97 | 313 | if (data & 0x8000){ |
philpem@97 | 314 | state.timer_enabled = 1; |
philpem@97 | 315 | }else{ |
philpem@97 | 316 | state.timer_enabled = 0; |
philpem@97 | 317 | state.timer_asserted = 0; |
philpem@97 | 318 | } |
philpem@59 | 319 | state.dma_reading = (data & 0x4000); |
philpem@72 | 320 | if (state.leds != ((~data & 0xF00) >> 8)) { |
philpem@72 | 321 | state.leds = (~data & 0xF00) >> 8; |
philpem@72 | 322 | printf("LEDs: %s %s %s %s\n", |
philpem@72 | 323 | (state.leds & 8) ? "R" : "-", |
philpem@72 | 324 | (state.leds & 4) ? "G" : "-", |
philpem@72 | 325 | (state.leds & 2) ? "Y" : "-", |
philpem@72 | 326 | (state.leds & 1) ? "R" : "-"); |
philpem@72 | 327 | } |
philpem@46 | 328 | handled = true; |
philpem@40 | 329 | break; |
philpem@40 | 330 | case 0x0B0000: // TM/DIALWR |
philpem@40 | 331 | break; |
philpem@59 | 332 | case 0x0C0000: // Clear Status Register |
philpem@59 | 333 | state.genstat = 0xFFFF; |
philpem@59 | 334 | state.bsr0 = 0xFFFF; |
philpem@59 | 335 | state.bsr1 = 0xFFFF; |
philpem@43 | 336 | handled = true; |
philpem@40 | 337 | break; |
philpem@40 | 338 | case 0x0D0000: // DMA Address Register |
philpem@59 | 339 | if (address & 0x004000) { |
philpem@59 | 340 | // A14 high -- set most significant bits |
philpem@59 | 341 | state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8); |
philpem@59 | 342 | } else { |
philpem@59 | 343 | // A14 low -- set least significant bits |
philpem@59 | 344 | state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe); |
philpem@59 | 345 | } |
philpem@59 | 346 | handled = true; |
philpem@40 | 347 | break; |
philpem@40 | 348 | case 0x0E0000: // Disk Control Register |
philpem@66 | 349 | ENFORCE_SIZE_W(bits, address, 16, "DISKCON"); |
philpem@59 | 350 | // B7 = FDD controller reset |
philpem@59 | 351 | if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx); |
philpem@59 | 352 | // B6 = drive 0 select -- TODO |
philpem@59 | 353 | // B5 = motor enable -- TODO |
philpem@59 | 354 | // B4 = HDD controller reset -- TODO |
philpem@59 | 355 | // B3 = HDD0 select -- TODO |
philpem@59 | 356 | // B2,1,0 = HDD0 head select |
philpem@59 | 357 | handled = true; |
philpem@40 | 358 | break; |
philpem@40 | 359 | case 0x0F0000: // Line Printer Data Register |
philpem@40 | 360 | break; |
philpem@40 | 361 | } |
philpem@40 | 362 | } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) { |
philpem@40 | 363 | // I/O register space, zone B |
philpem@40 | 364 | switch (address & 0xF00000) { |
philpem@40 | 365 | case 0xC00000: // Expansion slots |
philpem@40 | 366 | case 0xD00000: |
philpem@40 | 367 | switch (address & 0xFC0000) { |
philpem@40 | 368 | case 0xC00000: // Expansion slot 0 |
philpem@40 | 369 | case 0xC40000: // Expansion slot 1 |
philpem@40 | 370 | case 0xC80000: // Expansion slot 2 |
philpem@40 | 371 | case 0xCC0000: // Expansion slot 3 |
philpem@40 | 372 | case 0xD00000: // Expansion slot 4 |
philpem@40 | 373 | case 0xD40000: // Expansion slot 5 |
philpem@40 | 374 | case 0xD80000: // Expansion slot 6 |
philpem@40 | 375 | case 0xDC0000: // Expansion slot 7 |
philpem@59 | 376 | fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data); |
philpem@59 | 377 | handled = true; |
philpem@40 | 378 | break; |
philpem@40 | 379 | } |
philpem@40 | 380 | break; |
philpem@40 | 381 | case 0xE00000: // HDC, FDC, MCR2 and RTC data bits |
philpem@40 | 382 | case 0xF00000: |
philpem@40 | 383 | switch (address & 0x070000) { |
philpem@40 | 384 | case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller |
philpem@40 | 385 | break; |
philpem@40 | 386 | case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller |
philpem@66 | 387 | ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS"); |
philpem@59 | 388 | wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data); |
philpem@52 | 389 | handled = true; |
philpem@40 | 390 | break; |
philpem@40 | 391 | case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2 |
philpem@40 | 392 | break; |
philpem@40 | 393 | case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits |
philpem@40 | 394 | break; |
philpem@40 | 395 | case 0x040000: // [ef][4c]xxxx ==> General Control Register |
philpem@40 | 396 | switch (address & 0x077000) { |
philpem@40 | 397 | case 0x040000: // [ef][4c][08]xxx ==> EE |
philpem@102 | 398 | // Error Enable. If =0, Level7 intrs and bus errors are masked. |
philpem@102 | 399 | ENFORCE_SIZE_W(bits, address, 16, "EE"); |
philpem@102 | 400 | state.ee = ((data & 0x8000) == 0x8000); |
philpem@102 | 401 | handled = true; |
philpem@59 | 402 | break; |
philpem@44 | 403 | case 0x041000: // [ef][4c][19]xxx ==> PIE |
philpem@66 | 404 | ENFORCE_SIZE_W(bits, address, 16, "PIE"); |
philpem@59 | 405 | state.pie = ((data & 0x8000) == 0x8000); |
philpem@59 | 406 | handled = true; |
philpem@59 | 407 | break; |
philpem@40 | 408 | case 0x042000: // [ef][4c][2A]xxx ==> BP |
philpem@59 | 409 | break; |
philpem@40 | 410 | case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP |
philpem@66 | 411 | ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP"); |
philpem@59 | 412 | state.romlmap = ((data & 0x8000) == 0x8000); |
philpem@44 | 413 | handled = true; |
philpem@40 | 414 | break; |
philpem@59 | 415 | case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM |
philpem@66 | 416 | ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM"); |
philpem@59 | 417 | break; |
philpem@59 | 418 | case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM |
philpem@66 | 419 | ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM"); |
philpem@59 | 420 | break; |
philpem@59 | 421 | case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT |
philpem@66 | 422 | ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT"); |
philpem@59 | 423 | break; |
philpem@59 | 424 | case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video |
philpem@66 | 425 | ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO"); |
philpem@40 | 426 | break; |
philpem@40 | 427 | } |
philpem@40 | 428 | case 0x050000: // [ef][5d]xxxx ==> 8274 |
philpem@40 | 429 | break; |
philpem@40 | 430 | case 0x060000: // [ef][6e]xxxx ==> Control regs |
philpem@40 | 431 | switch (address & 0x07F000) { |
philpem@40 | 432 | default: |
philpem@40 | 433 | break; |
philpem@40 | 434 | } |
philpem@40 | 435 | break; |
philpem@40 | 436 | case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller |
philpem@84 | 437 | // TODO: figure out which sizes are valid (probably just 8 and 16) |
philpem@84 | 438 | // ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER"); |
philpem@93 | 439 | if (bits == 8) { |
philpem@93 | 440 | printf("KBD WR %02X => %02X\n", (address >> 1) & 3, data); |
philpem@93 | 441 | keyboard_write(&state.kbd, (address >> 1) & 3, data); |
philpem@93 | 442 | handled = true; |
philpem@93 | 443 | } else if (bits == 16) { |
philpem@93 | 444 | printf("KBD WR %02X => %04X\n", (address >> 1) & 3, data); |
philpem@93 | 445 | keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8); |
philpem@93 | 446 | handled = true; |
philpem@93 | 447 | } |
philpem@40 | 448 | break; |
philpem@40 | 449 | } |
philpem@40 | 450 | } |
philpem@40 | 451 | } |
philpem@40 | 452 | |
philpem@64 | 453 | LOG_NOT_HANDLED_W(bits); |
philpem@59 | 454 | }/*}}}*/ |
philpem@40 | 455 | |
philpem@59 | 456 | uint32_t IoRead(uint32_t address, int bits)/*{{{*/ |
philpem@59 | 457 | { |
philpem@59 | 458 | bool handled = false; |
philpem@59 | 459 | uint32_t data = 0xFFFFFFFF; |
philpem@40 | 460 | |
philpem@59 | 461 | if ((address >= 0x400000) && (address <= 0x7FFFFF)) { |
philpem@40 | 462 | // I/O register space, zone A |
philpem@40 | 463 | switch (address & 0x0F0000) { |
philpem@40 | 464 | case 0x010000: // General Status Register |
philpem@66 | 465 | ENFORCE_SIZE_R(bits, address, 16, "GENSTAT"); |
philpem@59 | 466 | return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat; |
philpem@40 | 467 | break; |
philpem@40 | 468 | case 0x030000: // Bus Status Register 0 |
philpem@66 | 469 | ENFORCE_SIZE_R(bits, address, 16, "BSR0"); |
philpem@59 | 470 | return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0; |
philpem@40 | 471 | break; |
philpem@40 | 472 | case 0x040000: // Bus Status Register 1 |
philpem@66 | 473 | ENFORCE_SIZE_R(bits, address, 16, "BSR1"); |
philpem@59 | 474 | return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1; |
philpem@40 | 475 | break; |
philpem@40 | 476 | case 0x050000: // Phone status |
philpem@66 | 477 | ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS"); |
philpem@40 | 478 | break; |
philpem@40 | 479 | case 0x060000: // DMA Count |
philpem@55 | 480 | // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+? |
philpem@55 | 481 | // Bit 14 is always unused, so leave it set |
philpem@66 | 482 | ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT"); |
philpem@59 | 483 | return (state.dma_count & 0x3fff) | 0xC000; |
philpem@40 | 484 | break; |
philpem@40 | 485 | case 0x070000: // Line Printer Status Register |
philpem@53 | 486 | data = 0x00120012; // no parity error, no line printer error, no irqs from FDD or HDD |
philpem@78 | 487 | data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0; |
philpem@59 | 488 | return data; |
philpem@40 | 489 | break; |
philpem@40 | 490 | case 0x080000: // Real Time Clock |
philpem@59 | 491 | printf("READ NOTIMP: Realtime Clock\n"); |
philpem@40 | 492 | break; |
philpem@40 | 493 | case 0x090000: // Phone registers |
philpem@40 | 494 | switch (address & 0x0FF000) { |
philpem@40 | 495 | case 0x090000: // Handset relay |
philpem@40 | 496 | case 0x098000: |
philpem@40 | 497 | break; |
philpem@40 | 498 | case 0x091000: // Line select 2 |
philpem@40 | 499 | case 0x099000: |
philpem@40 | 500 | break; |
philpem@40 | 501 | case 0x092000: // Hook relay 1 |
philpem@40 | 502 | case 0x09A000: |
philpem@40 | 503 | break; |
philpem@40 | 504 | case 0x093000: // Hook relay 2 |
philpem@40 | 505 | case 0x09B000: |
philpem@40 | 506 | break; |
philpem@40 | 507 | case 0x094000: // Line 1 hold |
philpem@40 | 508 | case 0x09C000: |
philpem@40 | 509 | break; |
philpem@40 | 510 | case 0x095000: // Line 2 hold |
philpem@40 | 511 | case 0x09D000: |
philpem@40 | 512 | break; |
philpem@40 | 513 | case 0x096000: // Line 1 A-lead |
philpem@40 | 514 | case 0x09E000: |
philpem@40 | 515 | break; |
philpem@40 | 516 | case 0x097000: // Line 2 A-lead |
philpem@40 | 517 | case 0x09F000: |
philpem@40 | 518 | break; |
philpem@40 | 519 | } |
philpem@40 | 520 | break; |
philpem@46 | 521 | case 0x0A0000: // Miscellaneous Control Register -- write only! |
philpem@46 | 522 | handled = true; |
philpem@40 | 523 | break; |
philpem@40 | 524 | case 0x0B0000: // TM/DIALWR |
philpem@40 | 525 | break; |
philpem@46 | 526 | case 0x0C0000: // Clear Status Register -- write only! |
philpem@43 | 527 | handled = true; |
philpem@40 | 528 | break; |
philpem@40 | 529 | case 0x0D0000: // DMA Address Register |
philpem@40 | 530 | break; |
philpem@40 | 531 | case 0x0E0000: // Disk Control Register |
philpem@40 | 532 | break; |
philpem@40 | 533 | case 0x0F0000: // Line Printer Data Register |
philpem@40 | 534 | break; |
philpem@40 | 535 | } |
philpem@40 | 536 | } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) { |
philpem@40 | 537 | // I/O register space, zone B |
philpem@40 | 538 | switch (address & 0xF00000) { |
philpem@40 | 539 | case 0xC00000: // Expansion slots |
philpem@40 | 540 | case 0xD00000: |
philpem@40 | 541 | switch (address & 0xFC0000) { |
philpem@40 | 542 | case 0xC00000: // Expansion slot 0 |
philpem@40 | 543 | case 0xC40000: // Expansion slot 1 |
philpem@40 | 544 | case 0xC80000: // Expansion slot 2 |
philpem@40 | 545 | case 0xCC0000: // Expansion slot 3 |
philpem@40 | 546 | case 0xD00000: // Expansion slot 4 |
philpem@40 | 547 | case 0xD40000: // Expansion slot 5 |
philpem@40 | 548 | case 0xD80000: // Expansion slot 6 |
philpem@40 | 549 | case 0xDC0000: // Expansion slot 7 |
philpem@65 | 550 | fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address); |
philpem@65 | 551 | handled = true; |
philpem@40 | 552 | break; |
philpem@40 | 553 | } |
philpem@40 | 554 | break; |
philpem@40 | 555 | case 0xE00000: // HDC, FDC, MCR2 and RTC data bits |
philpem@40 | 556 | case 0xF00000: |
philpem@40 | 557 | switch (address & 0x070000) { |
philpem@40 | 558 | case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller |
philpem@40 | 559 | break; |
philpem@40 | 560 | case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller |
philpem@66 | 561 | ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS"); |
philpem@59 | 562 | return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3); |
philpem@40 | 563 | break; |
philpem@40 | 564 | case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2 |
philpem@40 | 565 | break; |
philpem@40 | 566 | case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits |
philpem@40 | 567 | break; |
philpem@40 | 568 | case 0x040000: // [ef][4c]xxxx ==> General Control Register |
philpem@40 | 569 | switch (address & 0x077000) { |
philpem@40 | 570 | case 0x040000: // [ef][4c][08]xxx ==> EE |
philpem@44 | 571 | case 0x041000: // [ef][4c][19]xxx ==> PIE |
philpem@40 | 572 | case 0x042000: // [ef][4c][2A]xxx ==> BP |
philpem@40 | 573 | case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP |
philpem@40 | 574 | case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM |
philpem@40 | 575 | case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM |
philpem@40 | 576 | case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT |
philpem@44 | 577 | // All write-only registers... TODO: bus error? |
philpem@44 | 578 | handled = true; |
philpem@40 | 579 | break; |
philpem@44 | 580 | case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM] |
philpem@40 | 581 | break; |
philpem@40 | 582 | } |
philpem@40 | 583 | break; |
philpem@40 | 584 | case 0x050000: // [ef][5d]xxxx ==> 8274 |
philpem@40 | 585 | break; |
philpem@40 | 586 | case 0x060000: // [ef][6e]xxxx ==> Control regs |
philpem@40 | 587 | switch (address & 0x07F000) { |
philpem@40 | 588 | default: |
philpem@40 | 589 | break; |
philpem@40 | 590 | } |
philpem@40 | 591 | break; |
philpem@40 | 592 | case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller |
philpem@84 | 593 | // TODO: figure out which sizes are valid (probably just 8 and 16) |
philpem@84 | 594 | //ENFORCE_SIZE_R(bits, address, 16, "KEYBOARD CONTROLLER"); |
philpem@84 | 595 | { |
philpem@93 | 596 | if (bits == 8) { |
philpem@93 | 597 | return keyboard_read(&state.kbd, (address >> 1) & 3); |
philpem@93 | 598 | } else { |
philpem@93 | 599 | return keyboard_read(&state.kbd, (address >> 1) & 3) << 8; |
philpem@93 | 600 | } |
philpem@84 | 601 | return data; |
philpem@84 | 602 | } |
philpem@40 | 603 | break; |
philpem@40 | 604 | } |
philpem@40 | 605 | } |
philpem@40 | 606 | } |
philpem@40 | 607 | |
philpem@64 | 608 | LOG_NOT_HANDLED_R(bits); |
philpem@64 | 609 | |
philpem@59 | 610 | return data; |
philpem@59 | 611 | }/*}}}*/ |
philpem@40 | 612 | |
philpem@59 | 613 | |
philpem@59 | 614 | /******************************************************** |
philpem@59 | 615 | * m68k memory read/write support functions for Musashi |
philpem@59 | 616 | ********************************************************/ |
philpem@59 | 617 | |
philpem@59 | 618 | /** |
philpem@59 | 619 | * @brief Read M68K memory, 32-bit |
philpem@59 | 620 | */ |
philpem@59 | 621 | uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/ |
philpem@59 | 622 | { |
philpem@59 | 623 | uint32_t data = 0xFFFFFFFF; |
philpem@59 | 624 | |
philpem@59 | 625 | // If ROMLMAP is set, force system to access ROM |
philpem@59 | 626 | if (!state.romlmap) |
philpem@59 | 627 | address |= 0x800000; |
philpem@59 | 628 | |
philpem@59 | 629 | // Check access permissions |
philpem@59 | 630 | ACCESS_CHECK_RD(address, 32); |
philpem@59 | 631 | |
philpem@59 | 632 | if ((address >= 0x800000) && (address <= 0xBFFFFF)) { |
philpem@59 | 633 | // ROM access |
philpem@60 | 634 | return RD32(state.rom, address, ROM_SIZE - 1); |
philpem@60 | 635 | } else if (address <= 0x3fffff) { |
philpem@59 | 636 | // RAM access |
philpem@60 | 637 | uint32_t newAddr = mapAddr(address, false); |
philpem@63 | 638 | if (newAddr <= 0x1fffff) { |
philpem@60 | 639 | return RD32(state.base_ram, newAddr, state.base_ram_size - 1); |
philpem@63 | 640 | } else { |
philpem@63 | 641 | if (newAddr <= (state.exp_ram_size + 0x200000 - 1)) |
philpem@63 | 642 | return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1); |
philpem@63 | 643 | else |
philpem@63 | 644 | return 0xffffffff; |
philpem@63 | 645 | } |
philpem@59 | 646 | } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { |
philpem@59 | 647 | // I/O register space, zone A |
philpem@59 | 648 | switch (address & 0x0F0000) { |
philpem@59 | 649 | case 0x000000: // Map RAM access |
philpem@59 | 650 | if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address); |
philpem@60 | 651 | return RD32(state.map, address, 0x7FF); |
philpem@59 | 652 | break; |
philpem@59 | 653 | case 0x020000: // Video RAM |
philpem@59 | 654 | if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address); |
philpem@60 | 655 | return RD32(state.vram, address, 0x7FFF); |
philpem@59 | 656 | break; |
philpem@59 | 657 | default: |
philpem@60 | 658 | return IoRead(address, 32); |
philpem@59 | 659 | } |
philpem@59 | 660 | } else { |
philpem@60 | 661 | return IoRead(address, 32); |
philpem@59 | 662 | } |
philpem@59 | 663 | |
philpem@40 | 664 | return data; |
philpem@59 | 665 | }/*}}}*/ |
philpem@40 | 666 | |
philpem@40 | 667 | /** |
philpem@40 | 668 | * @brief Read M68K memory, 16-bit |
philpem@40 | 669 | */ |
philpem@59 | 670 | uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/ |
philpem@40 | 671 | { |
philpem@40 | 672 | uint16_t data = 0xFFFF; |
philpem@40 | 673 | |
philpem@40 | 674 | // If ROMLMAP is set, force system to access ROM |
philpem@40 | 675 | if (!state.romlmap) |
philpem@40 | 676 | address |= 0x800000; |
philpem@40 | 677 | |
philpem@40 | 678 | // Check access permissions |
philpem@40 | 679 | ACCESS_CHECK_RD(address, 16); |
philpem@40 | 680 | |
philpem@40 | 681 | if ((address >= 0x800000) && (address <= 0xBFFFFF)) { |
philpem@40 | 682 | // ROM access |
philpem@40 | 683 | data = RD16(state.rom, address, ROM_SIZE - 1); |
philpem@60 | 684 | } else if (address <= 0x3fffff) { |
philpem@40 | 685 | // RAM access |
philpem@60 | 686 | uint32_t newAddr = mapAddr(address, false); |
philpem@63 | 687 | if (newAddr <= 0x1fffff) { |
philpem@60 | 688 | return RD16(state.base_ram, newAddr, state.base_ram_size - 1); |
philpem@63 | 689 | } else { |
philpem@63 | 690 | if (newAddr <= (state.exp_ram_size + 0x200000 - 1)) |
philpem@63 | 691 | return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1); |
philpem@63 | 692 | else |
philpem@63 | 693 | return 0xffff; |
philpem@63 | 694 | } |
philpem@40 | 695 | } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { |
philpem@40 | 696 | // I/O register space, zone A |
philpem@40 | 697 | switch (address & 0x0F0000) { |
philpem@40 | 698 | case 0x000000: // Map RAM access |
philpem@40 | 699 | if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address); |
philpem@40 | 700 | data = RD16(state.map, address, 0x7FF); |
philpem@40 | 701 | break; |
philpem@40 | 702 | case 0x020000: // Video RAM |
philpem@40 | 703 | if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address); |
philpem@40 | 704 | data = RD16(state.vram, address, 0x7FFF); |
philpem@40 | 705 | break; |
philpem@59 | 706 | default: |
philpem@59 | 707 | data = IoRead(address, 16); |
philpem@40 | 708 | } |
philpem@59 | 709 | } else { |
philpem@59 | 710 | data = IoRead(address, 16); |
philpem@40 | 711 | } |
philpem@40 | 712 | |
philpem@40 | 713 | return data; |
philpem@59 | 714 | }/*}}}*/ |
philpem@40 | 715 | |
philpem@40 | 716 | /** |
philpem@40 | 717 | * @brief Read M68K memory, 8-bit |
philpem@40 | 718 | */ |
philpem@59 | 719 | uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/ |
philpem@40 | 720 | { |
philpem@40 | 721 | uint8_t data = 0xFF; |
philpem@40 | 722 | |
philpem@40 | 723 | // If ROMLMAP is set, force system to access ROM |
philpem@40 | 724 | if (!state.romlmap) |
philpem@40 | 725 | address |= 0x800000; |
philpem@40 | 726 | |
philpem@40 | 727 | // Check access permissions |
philpem@40 | 728 | ACCESS_CHECK_RD(address, 8); |
philpem@40 | 729 | |
philpem@40 | 730 | if ((address >= 0x800000) && (address <= 0xBFFFFF)) { |
philpem@40 | 731 | // ROM access |
philpem@40 | 732 | data = RD8(state.rom, address, ROM_SIZE - 1); |
philpem@60 | 733 | } else if (address <= 0x3fffff) { |
philpem@40 | 734 | // RAM access |
philpem@60 | 735 | uint32_t newAddr = mapAddr(address, false); |
philpem@63 | 736 | if (newAddr <= 0x1fffff) { |
philpem@60 | 737 | return RD8(state.base_ram, newAddr, state.base_ram_size - 1); |
philpem@63 | 738 | } else { |
philpem@63 | 739 | if (newAddr <= (state.exp_ram_size + 0x200000 - 1)) |
philpem@63 | 740 | return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1); |
philpem@63 | 741 | else |
philpem@63 | 742 | return 0xff; |
philpem@63 | 743 | } |
philpem@40 | 744 | } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { |
philpem@40 | 745 | // I/O register space, zone A |
philpem@40 | 746 | switch (address & 0x0F0000) { |
philpem@40 | 747 | case 0x000000: // Map RAM access |
philpem@40 | 748 | if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address); |
philpem@40 | 749 | data = RD8(state.map, address, 0x7FF); |
philpem@40 | 750 | break; |
philpem@40 | 751 | case 0x020000: // Video RAM |
philpem@40 | 752 | if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address); |
philpem@40 | 753 | data = RD8(state.vram, address, 0x7FFF); |
philpem@40 | 754 | break; |
philpem@59 | 755 | default: |
philpem@59 | 756 | data = IoRead(address, 8); |
philpem@40 | 757 | } |
philpem@59 | 758 | } else { |
philpem@59 | 759 | data = IoRead(address, 8); |
philpem@40 | 760 | } |
philpem@40 | 761 | |
philpem@40 | 762 | return data; |
philpem@59 | 763 | }/*}}}*/ |
philpem@40 | 764 | |
philpem@40 | 765 | /** |
philpem@40 | 766 | * @brief Write M68K memory, 32-bit |
philpem@40 | 767 | */ |
philpem@59 | 768 | void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/ |
philpem@40 | 769 | { |
philpem@40 | 770 | // If ROMLMAP is set, force system to access ROM |
philpem@40 | 771 | if (!state.romlmap) |
philpem@40 | 772 | address |= 0x800000; |
philpem@40 | 773 | |
philpem@40 | 774 | // Check access permissions |
philpem@40 | 775 | ACCESS_CHECK_WR(address, 32); |
philpem@40 | 776 | |
philpem@40 | 777 | if ((address >= 0x800000) && (address <= 0xBFFFFF)) { |
philpem@40 | 778 | // ROM access |
philpem@60 | 779 | } else if (address <= 0x3FFFFF) { |
philpem@40 | 780 | // RAM access |
philpem@60 | 781 | uint32_t newAddr = mapAddr(address, true); |
philpem@70 | 782 | if (newAddr <= 0x1fffff) |
philpem@60 | 783 | WR32(state.base_ram, newAddr, state.base_ram_size - 1, value); |
philpem@70 | 784 | else |
philpem@65 | 785 | WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value); |
philpem@40 | 786 | } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { |
philpem@40 | 787 | // I/O register space, zone A |
philpem@40 | 788 | switch (address & 0x0F0000) { |
philpem@40 | 789 | case 0x000000: // Map RAM access |
philpem@105 | 790 | if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X\n", address); |
philpem@40 | 791 | WR32(state.map, address, 0x7FF, value); |
philpem@40 | 792 | break; |
philpem@40 | 793 | case 0x020000: // Video RAM |
philpem@105 | 794 | if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X\n", address); |
philpem@40 | 795 | WR32(state.vram, address, 0x7FFF, value); |
philpem@40 | 796 | break; |
philpem@59 | 797 | default: |
philpem@59 | 798 | IoWrite(address, value, 32); |
philpem@40 | 799 | } |
philpem@59 | 800 | } else { |
philpem@59 | 801 | IoWrite(address, value, 32); |
philpem@40 | 802 | } |
philpem@59 | 803 | }/*}}}*/ |
philpem@40 | 804 | |
philpem@40 | 805 | /** |
philpem@40 | 806 | * @brief Write M68K memory, 16-bit |
philpem@40 | 807 | */ |
philpem@59 | 808 | void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/ |
philpem@40 | 809 | { |
philpem@40 | 810 | // If ROMLMAP is set, force system to access ROM |
philpem@40 | 811 | if (!state.romlmap) |
philpem@40 | 812 | address |= 0x800000; |
philpem@40 | 813 | |
philpem@40 | 814 | // Check access permissions |
philpem@40 | 815 | ACCESS_CHECK_WR(address, 16); |
philpem@40 | 816 | |
philpem@40 | 817 | if ((address >= 0x800000) && (address <= 0xBFFFFF)) { |
philpem@40 | 818 | // ROM access |
philpem@60 | 819 | } else if (address <= 0x3FFFFF) { |
philpem@40 | 820 | // RAM access |
philpem@60 | 821 | uint32_t newAddr = mapAddr(address, true); |
philpem@70 | 822 | if (newAddr <= 0x1fffff) |
philpem@60 | 823 | WR16(state.base_ram, newAddr, state.base_ram_size - 1, value); |
philpem@70 | 824 | else |
philpem@65 | 825 | WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value); |
philpem@40 | 826 | } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { |
philpem@40 | 827 | // I/O register space, zone A |
philpem@40 | 828 | switch (address & 0x0F0000) { |
philpem@40 | 829 | case 0x000000: // Map RAM access |
philpem@40 | 830 | if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value); |
philpem@40 | 831 | WR16(state.map, address, 0x7FF, value); |
philpem@40 | 832 | break; |
philpem@40 | 833 | case 0x020000: // Video RAM |
philpem@40 | 834 | if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value); |
philpem@40 | 835 | WR16(state.vram, address, 0x7FFF, value); |
philpem@40 | 836 | break; |
philpem@59 | 837 | default: |
philpem@59 | 838 | IoWrite(address, value, 16); |
philpem@40 | 839 | } |
philpem@59 | 840 | } else { |
philpem@59 | 841 | IoWrite(address, value, 16); |
philpem@40 | 842 | } |
philpem@59 | 843 | }/*}}}*/ |
philpem@40 | 844 | |
philpem@40 | 845 | /** |
philpem@40 | 846 | * @brief Write M68K memory, 8-bit |
philpem@40 | 847 | */ |
philpem@59 | 848 | void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/ |
philpem@40 | 849 | { |
philpem@40 | 850 | // If ROMLMAP is set, force system to access ROM |
philpem@40 | 851 | if (!state.romlmap) |
philpem@40 | 852 | address |= 0x800000; |
philpem@40 | 853 | |
philpem@40 | 854 | // Check access permissions |
philpem@40 | 855 | ACCESS_CHECK_WR(address, 8); |
philpem@40 | 856 | |
philpem@40 | 857 | if ((address >= 0x800000) && (address <= 0xBFFFFF)) { |
philpem@40 | 858 | // ROM access (read only!) |
philpem@60 | 859 | } else if (address <= 0x3FFFFF) { |
philpem@40 | 860 | // RAM access |
philpem@60 | 861 | uint32_t newAddr = mapAddr(address, true); |
philpem@70 | 862 | if (newAddr <= 0x1fffff) |
philpem@60 | 863 | WR8(state.base_ram, newAddr, state.base_ram_size - 1, value); |
philpem@70 | 864 | else |
philpem@65 | 865 | WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value); |
philpem@40 | 866 | } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { |
philpem@40 | 867 | // I/O register space, zone A |
philpem@40 | 868 | switch (address & 0x0F0000) { |
philpem@40 | 869 | case 0x000000: // Map RAM access |
philpem@59 | 870 | if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value); |
philpem@40 | 871 | WR8(state.map, address, 0x7FF, value); |
philpem@40 | 872 | break; |
philpem@40 | 873 | case 0x020000: // Video RAM |
philpem@59 | 874 | if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value); |
philpem@40 | 875 | WR8(state.vram, address, 0x7FFF, value); |
philpem@40 | 876 | break; |
philpem@59 | 877 | default: |
philpem@59 | 878 | IoWrite(address, value, 8); |
philpem@40 | 879 | } |
philpem@59 | 880 | } else { |
philpem@59 | 881 | IoWrite(address, value, 8); |
philpem@40 | 882 | } |
philpem@59 | 883 | }/*}}}*/ |
philpem@40 | 884 | |
philpem@40 | 885 | |
philpem@40 | 886 | // for the disassembler |
philpem@40 | 887 | uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); } |
philpem@40 | 888 | uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); } |
philpem@40 | 889 | uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); } |
philpem@40 | 890 |