Fri, 03 Dec 2010 00:04:01 +0000
add basic handling for Clear Status Register and fix mem access checks to provide PIE status
philpem@40 | 1 | #include <stdio.h> |
philpem@40 | 2 | #include <stdlib.h> |
philpem@40 | 3 | #include <stdint.h> |
philpem@40 | 4 | #include <stdbool.h> |
philpem@40 | 5 | #include "musashi/m68k.h" |
philpem@40 | 6 | #include "state.h" |
philpem@40 | 7 | #include "memory.h" |
philpem@40 | 8 | |
philpem@40 | 9 | /****************** |
philpem@40 | 10 | * Memory mapping |
philpem@40 | 11 | ******************/ |
philpem@40 | 12 | |
philpem@40 | 13 | #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1])) |
philpem@40 | 14 | |
philpem@40 | 15 | uint32_t mapAddr(uint32_t addr, bool writing) |
philpem@40 | 16 | { |
philpem@40 | 17 | if (addr < 0x400000) { |
philpem@40 | 18 | // RAM access. Check against the Map RAM |
philpem@40 | 19 | // Start by getting the original page address |
philpem@40 | 20 | uint16_t page = (addr >> 12) & 0x3FF; |
philpem@40 | 21 | |
philpem@40 | 22 | // Look it up in the map RAM and get the physical page address |
philpem@40 | 23 | uint32_t new_page_addr = MAPRAM(page) & 0x3FF; |
philpem@40 | 24 | |
philpem@40 | 25 | // Update the Page Status bits |
philpem@40 | 26 | uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03; |
philpem@40 | 27 | if (pagebits != 0) { |
philpem@40 | 28 | if (writing) |
philpem@40 | 29 | state.map[page*2] |= 0x60; // Page written to (dirty) |
philpem@40 | 30 | else |
philpem@40 | 31 | state.map[page*2] |= 0x40; // Page accessed but not written |
philpem@40 | 32 | } |
philpem@40 | 33 | |
philpem@40 | 34 | // Return the address with the new physical page spliced in |
philpem@40 | 35 | return (new_page_addr << 12) + (addr & 0xFFF); |
philpem@40 | 36 | } else { |
philpem@40 | 37 | // I/O, VRAM or MapRAM space; no mapping is performed or required |
philpem@40 | 38 | // TODO: assert here? |
philpem@40 | 39 | return addr; |
philpem@40 | 40 | } |
philpem@40 | 41 | } |
philpem@40 | 42 | |
philpem@40 | 43 | MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing) |
philpem@40 | 44 | { |
philpem@40 | 45 | // Are we in Supervisor mode? |
philpem@40 | 46 | if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000) |
philpem@40 | 47 | // Yes. We can do anything we like. |
philpem@40 | 48 | return MEM_ALLOWED; |
philpem@40 | 49 | |
philpem@40 | 50 | // If we're here, then we must be in User mode. |
philpem@40 | 51 | // Check that the user didn't access memory outside of the RAM area |
philpem@40 | 52 | if (addr >= 0x400000) |
philpem@40 | 53 | return MEM_UIE; |
philpem@40 | 54 | |
philpem@40 | 55 | // This leaves us with Page Fault checking. Get the page bits for this page. |
philpem@40 | 56 | uint16_t page = (addr >> 12) & 0x3FF; |
philpem@40 | 57 | uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07; |
philpem@40 | 58 | |
philpem@40 | 59 | // Check page is present |
philpem@40 | 60 | if ((pagebits & 0x03) == 0) |
philpem@40 | 61 | return MEM_PAGEFAULT; |
philpem@40 | 62 | |
philpem@40 | 63 | // User attempt to access the kernel |
philpem@40 | 64 | // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode |
philpem@40 | 65 | if (((addr >> 19) & 0x0F) == 0) |
philpem@40 | 66 | return MEM_KERNEL; |
philpem@40 | 67 | |
philpem@40 | 68 | // Check page is write enabled |
philpem@40 | 69 | if ((pagebits & 0x04) == 0) |
philpem@40 | 70 | return MEM_PAGE_NO_WE; |
philpem@40 | 71 | |
philpem@40 | 72 | // Page access allowed. |
philpem@40 | 73 | return MEM_ALLOWED; |
philpem@40 | 74 | } |
philpem@40 | 75 | |
philpem@40 | 76 | #undef MAPRAM |
philpem@40 | 77 | |
philpem@40 | 78 | |
philpem@40 | 79 | /******************************************************** |
philpem@40 | 80 | * m68k memory read/write support functions for Musashi |
philpem@40 | 81 | ********************************************************/ |
philpem@40 | 82 | |
philpem@40 | 83 | /** |
philpem@40 | 84 | * @brief Check memory access permissions for a write operation. |
philpem@40 | 85 | * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but |
philpem@40 | 86 | * gcc throws warnings when you have a return-with-value in a void |
philpem@40 | 87 | * function, even if the return-with-value is completely unreachable. |
philpem@40 | 88 | * Similarly it doesn't like it if you have a return without a value |
philpem@40 | 89 | * in a non-void function, even if it's impossible to ever reach the |
philpem@40 | 90 | * return-with-no-value. UGH! |
philpem@40 | 91 | */ |
philpem@40 | 92 | #define ACCESS_CHECK_WR(address, bits) do { \ |
philpem@40 | 93 | bool fault = false; \ |
philpem@40 | 94 | /* MEM_STATUS st; */ \ |
philpem@40 | 95 | switch (checkMemoryAccess(address, true)) { \ |
philpem@40 | 96 | case MEM_ALLOWED: \ |
philpem@40 | 97 | /* Access allowed */ \ |
philpem@40 | 98 | break; \ |
philpem@40 | 99 | case MEM_PAGEFAULT: \ |
philpem@40 | 100 | /* Page fault */ \ |
philpem@43 | 101 | state.genstat = 0x8BFF | (status.pie ? 0x0400 : 0); \ |
philpem@40 | 102 | fault = true; \ |
philpem@40 | 103 | break; \ |
philpem@40 | 104 | case MEM_UIE: \ |
philpem@40 | 105 | /* User access to memory above 4MB */ \ |
philpem@43 | 106 | state.genstat = 0x9AFF | (status.pie ? 0x0400 : 0); \ |
philpem@40 | 107 | fault = true; \ |
philpem@40 | 108 | break; \ |
philpem@40 | 109 | case MEM_KERNEL: \ |
philpem@40 | 110 | case MEM_PAGE_NO_WE: \ |
philpem@40 | 111 | /* kernel access or page not write enabled */ \ |
philpem@40 | 112 | /* TODO: which regs need setting? */ \ |
philpem@40 | 113 | fault = true; \ |
philpem@40 | 114 | break; \ |
philpem@40 | 115 | } \ |
philpem@40 | 116 | \ |
philpem@40 | 117 | if (fault) { \ |
philpem@40 | 118 | if (bits >= 16) \ |
philpem@40 | 119 | state.bsr0 = 0x7F00; \ |
philpem@40 | 120 | else \ |
philpem@40 | 121 | state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \ |
philpem@40 | 122 | state.bsr0 |= (address >> 16); \ |
philpem@40 | 123 | state.bsr1 = address & 0xffff; \ |
philpem@40 | 124 | printf("ERR: BusError WR\n"); \ |
philpem@40 | 125 | m68k_pulse_bus_error(); \ |
philpem@40 | 126 | return; \ |
philpem@40 | 127 | } \ |
philpem@40 | 128 | } while (false) |
philpem@40 | 129 | |
philpem@40 | 130 | /** |
philpem@40 | 131 | * @brief Check memory access permissions for a read operation. |
philpem@40 | 132 | * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but |
philpem@40 | 133 | * gcc throws warnings when you have a return-with-value in a void |
philpem@40 | 134 | * function, even if the return-with-value is completely unreachable. |
philpem@40 | 135 | * Similarly it doesn't like it if you have a return without a value |
philpem@40 | 136 | * in a non-void function, even if it's impossible to ever reach the |
philpem@40 | 137 | * return-with-no-value. UGH! |
philpem@40 | 138 | */ |
philpem@40 | 139 | #define ACCESS_CHECK_RD(address, bits) do { \ |
philpem@40 | 140 | bool fault = false; \ |
philpem@40 | 141 | /* MEM_STATUS st; */ \ |
philpem@40 | 142 | switch (checkMemoryAccess(address, false)) { \ |
philpem@40 | 143 | case MEM_ALLOWED: \ |
philpem@40 | 144 | /* Access allowed */ \ |
philpem@40 | 145 | break; \ |
philpem@40 | 146 | case MEM_PAGEFAULT: \ |
philpem@40 | 147 | /* Page fault */ \ |
philpem@43 | 148 | state.genstat = 0xCBFF | (status.pie ? 0x0400 : 0); \ |
philpem@40 | 149 | fault = true; \ |
philpem@40 | 150 | break; \ |
philpem@40 | 151 | case MEM_UIE: \ |
philpem@40 | 152 | /* User access to memory above 4MB */ \ |
philpem@43 | 153 | state.genstat = 0xDAFF | (status.pie ? 0x0400 : 0); \ |
philpem@40 | 154 | fault = true; \ |
philpem@40 | 155 | break; \ |
philpem@40 | 156 | case MEM_KERNEL: \ |
philpem@40 | 157 | case MEM_PAGE_NO_WE: \ |
philpem@40 | 158 | /* kernel access or page not write enabled */ \ |
philpem@40 | 159 | /* TODO: which regs need setting? */ \ |
philpem@40 | 160 | fault = true; \ |
philpem@40 | 161 | break; \ |
philpem@40 | 162 | } \ |
philpem@40 | 163 | \ |
philpem@40 | 164 | if (fault) { \ |
philpem@40 | 165 | if (bits >= 16) \ |
philpem@40 | 166 | state.bsr0 = 0x7F00; \ |
philpem@40 | 167 | else \ |
philpem@40 | 168 | state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \ |
philpem@40 | 169 | state.bsr0 |= (address >> 16); \ |
philpem@40 | 170 | state.bsr1 = address & 0xffff; \ |
philpem@40 | 171 | printf("ERR: BusError RD\n"); \ |
philpem@40 | 172 | m68k_pulse_bus_error(); \ |
philpem@40 | 173 | return 0xFFFFFFFF; \ |
philpem@40 | 174 | } \ |
philpem@40 | 175 | } while (false) |
philpem@40 | 176 | |
philpem@40 | 177 | // Logging macros |
philpem@40 | 178 | #define LOG_NOT_HANDLED_R(bits) \ |
philpem@40 | 179 | do { \ |
philpem@40 | 180 | if (!handled) \ |
philpem@40 | 181 | printf("unhandled read%02d, addr=0x%08X\n", bits, address); \ |
philpem@40 | 182 | } while (0); |
philpem@40 | 183 | |
philpem@40 | 184 | #define LOG_NOT_HANDLED_W(bits) \ |
philpem@40 | 185 | do { \ |
philpem@40 | 186 | if (!handled) \ |
philpem@40 | 187 | printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, value); \ |
philpem@40 | 188 | } while (0); |
philpem@40 | 189 | |
philpem@40 | 190 | /** |
philpem@40 | 191 | * @brief Read M68K memory, 32-bit |
philpem@40 | 192 | */ |
philpem@40 | 193 | uint32_t m68k_read_memory_32(uint32_t address) |
philpem@40 | 194 | { |
philpem@40 | 195 | uint32_t data = 0xFFFFFFFF; |
philpem@40 | 196 | bool handled = false; |
philpem@40 | 197 | |
philpem@40 | 198 | // If ROMLMAP is set, force system to access ROM |
philpem@40 | 199 | if (!state.romlmap) |
philpem@40 | 200 | address |= 0x800000; |
philpem@40 | 201 | |
philpem@40 | 202 | // Check access permissions |
philpem@40 | 203 | ACCESS_CHECK_RD(address, 32); |
philpem@40 | 204 | |
philpem@40 | 205 | if ((address >= 0x800000) && (address <= 0xBFFFFF)) { |
philpem@40 | 206 | // ROM access |
philpem@40 | 207 | data = RD32(state.rom, address, ROM_SIZE - 1); |
philpem@40 | 208 | handled = true; |
philpem@40 | 209 | } else if (address <= (state.ram_size - 1)) { |
philpem@40 | 210 | // RAM access |
philpem@40 | 211 | data = RD32(state.ram, mapAddr(address, false), state.ram_size - 1); |
philpem@40 | 212 | handled = true; |
philpem@40 | 213 | } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { |
philpem@40 | 214 | // I/O register space, zone A |
philpem@40 | 215 | switch (address & 0x0F0000) { |
philpem@40 | 216 | case 0x000000: // Map RAM access |
philpem@40 | 217 | if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address); |
philpem@40 | 218 | data = RD32(state.map, address, 0x7FF); |
philpem@40 | 219 | handled = true; |
philpem@40 | 220 | break; |
philpem@40 | 221 | case 0x010000: // General Status Register |
philpem@40 | 222 | data = ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat; |
philpem@40 | 223 | handled = true; |
philpem@40 | 224 | break; |
philpem@40 | 225 | case 0x020000: // Video RAM |
philpem@40 | 226 | if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address); |
philpem@40 | 227 | data = RD32(state.vram, address, 0x7FFF); |
philpem@40 | 228 | handled = true; |
philpem@40 | 229 | break; |
philpem@40 | 230 | case 0x030000: // Bus Status Register 0 |
philpem@40 | 231 | data = ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0; |
philpem@40 | 232 | handled = true; |
philpem@40 | 233 | break; |
philpem@40 | 234 | case 0x040000: // Bus Status Register 1 |
philpem@40 | 235 | data = ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1; |
philpem@40 | 236 | handled = true; |
philpem@40 | 237 | break; |
philpem@40 | 238 | case 0x050000: // Phone status |
philpem@40 | 239 | break; |
philpem@40 | 240 | case 0x060000: // DMA Count |
philpem@40 | 241 | break; |
philpem@40 | 242 | case 0x070000: // Line Printer Status Register |
philpem@40 | 243 | break; |
philpem@40 | 244 | case 0x080000: // Real Time Clock |
philpem@40 | 245 | break; |
philpem@40 | 246 | case 0x090000: // Phone registers |
philpem@40 | 247 | switch (address & 0x0FF000) { |
philpem@40 | 248 | case 0x090000: // Handset relay |
philpem@40 | 249 | case 0x098000: |
philpem@40 | 250 | break; |
philpem@40 | 251 | case 0x091000: // Line select 2 |
philpem@40 | 252 | case 0x099000: |
philpem@40 | 253 | break; |
philpem@40 | 254 | case 0x092000: // Hook relay 1 |
philpem@40 | 255 | case 0x09A000: |
philpem@40 | 256 | break; |
philpem@40 | 257 | case 0x093000: // Hook relay 2 |
philpem@40 | 258 | case 0x09B000: |
philpem@40 | 259 | break; |
philpem@40 | 260 | case 0x094000: // Line 1 hold |
philpem@40 | 261 | case 0x09C000: |
philpem@40 | 262 | break; |
philpem@40 | 263 | case 0x095000: // Line 2 hold |
philpem@40 | 264 | case 0x09D000: |
philpem@40 | 265 | break; |
philpem@40 | 266 | case 0x096000: // Line 1 A-lead |
philpem@40 | 267 | case 0x09E000: |
philpem@40 | 268 | break; |
philpem@40 | 269 | case 0x097000: // Line 2 A-lead |
philpem@40 | 270 | case 0x09F000: |
philpem@40 | 271 | break; |
philpem@40 | 272 | } |
philpem@40 | 273 | break; |
philpem@40 | 274 | case 0x0A0000: // Miscellaneous Control Register |
philpem@40 | 275 | break; |
philpem@40 | 276 | case 0x0B0000: // TM/DIALWR |
philpem@40 | 277 | break; |
philpem@43 | 278 | case 0x0C0000: // Clear Status Register |
philpem@43 | 279 | handled = true; |
philpem@40 | 280 | break; |
philpem@40 | 281 | case 0x0D0000: // DMA Address Register |
philpem@40 | 282 | break; |
philpem@40 | 283 | case 0x0E0000: // Disk Control Register |
philpem@40 | 284 | break; |
philpem@40 | 285 | case 0x0F0000: // Line Printer Data Register |
philpem@40 | 286 | break; |
philpem@40 | 287 | } |
philpem@40 | 288 | } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) { |
philpem@40 | 289 | // I/O register space, zone B |
philpem@40 | 290 | switch (address & 0xF00000) { |
philpem@40 | 291 | case 0xC00000: // Expansion slots |
philpem@40 | 292 | case 0xD00000: |
philpem@40 | 293 | switch (address & 0xFC0000) { |
philpem@40 | 294 | case 0xC00000: // Expansion slot 0 |
philpem@40 | 295 | case 0xC40000: // Expansion slot 1 |
philpem@40 | 296 | case 0xC80000: // Expansion slot 2 |
philpem@40 | 297 | case 0xCC0000: // Expansion slot 3 |
philpem@40 | 298 | case 0xD00000: // Expansion slot 4 |
philpem@40 | 299 | case 0xD40000: // Expansion slot 5 |
philpem@40 | 300 | case 0xD80000: // Expansion slot 6 |
philpem@40 | 301 | case 0xDC0000: // Expansion slot 7 |
philpem@40 | 302 | fprintf(stderr, "NOTE: RD32 from expansion card space, addr=0x%08X\n", address); |
philpem@40 | 303 | break; |
philpem@40 | 304 | } |
philpem@40 | 305 | break; |
philpem@40 | 306 | case 0xE00000: // HDC, FDC, MCR2 and RTC data bits |
philpem@40 | 307 | case 0xF00000: |
philpem@40 | 308 | switch (address & 0x070000) { |
philpem@40 | 309 | case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller |
philpem@40 | 310 | break; |
philpem@40 | 311 | case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller |
philpem@40 | 312 | break; |
philpem@40 | 313 | case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2 |
philpem@40 | 314 | break; |
philpem@40 | 315 | case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits |
philpem@40 | 316 | break; |
philpem@40 | 317 | case 0x040000: // [ef][4c]xxxx ==> General Control Register |
philpem@40 | 318 | switch (address & 0x077000) { |
philpem@40 | 319 | case 0x040000: // [ef][4c][08]xxx ==> EE |
philpem@40 | 320 | break; |
philpem@40 | 321 | case 0x041000: // [ef][4c][19]xxx ==> P1E |
philpem@40 | 322 | break; |
philpem@40 | 323 | case 0x042000: // [ef][4c][2A]xxx ==> BP |
philpem@40 | 324 | break; |
philpem@40 | 325 | case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP |
philpem@40 | 326 | break; |
philpem@40 | 327 | case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM |
philpem@40 | 328 | break; |
philpem@40 | 329 | case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM |
philpem@40 | 330 | break; |
philpem@40 | 331 | case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT |
philpem@40 | 332 | break; |
philpem@40 | 333 | case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video |
philpem@40 | 334 | break; |
philpem@40 | 335 | } |
philpem@40 | 336 | break; |
philpem@40 | 337 | case 0x050000: // [ef][5d]xxxx ==> 8274 |
philpem@40 | 338 | break; |
philpem@40 | 339 | case 0x060000: // [ef][6e]xxxx ==> Control regs |
philpem@40 | 340 | switch (address & 0x07F000) { |
philpem@40 | 341 | default: |
philpem@40 | 342 | break; |
philpem@40 | 343 | } |
philpem@40 | 344 | break; |
philpem@40 | 345 | case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller |
philpem@40 | 346 | break; |
philpem@40 | 347 | } |
philpem@40 | 348 | } |
philpem@40 | 349 | } |
philpem@40 | 350 | |
philpem@40 | 351 | LOG_NOT_HANDLED_R(32); |
philpem@40 | 352 | return data; |
philpem@40 | 353 | } |
philpem@40 | 354 | |
philpem@40 | 355 | /** |
philpem@40 | 356 | * @brief Read M68K memory, 16-bit |
philpem@40 | 357 | */ |
philpem@40 | 358 | uint32_t m68k_read_memory_16(uint32_t address) |
philpem@40 | 359 | { |
philpem@40 | 360 | uint16_t data = 0xFFFF; |
philpem@40 | 361 | bool handled = false; |
philpem@40 | 362 | |
philpem@40 | 363 | // If ROMLMAP is set, force system to access ROM |
philpem@40 | 364 | if (!state.romlmap) |
philpem@40 | 365 | address |= 0x800000; |
philpem@40 | 366 | |
philpem@40 | 367 | // Check access permissions |
philpem@40 | 368 | ACCESS_CHECK_RD(address, 16); |
philpem@40 | 369 | |
philpem@40 | 370 | if ((address >= 0x800000) && (address <= 0xBFFFFF)) { |
philpem@40 | 371 | // ROM access |
philpem@40 | 372 | data = RD16(state.rom, address, ROM_SIZE - 1); |
philpem@40 | 373 | handled = true; |
philpem@40 | 374 | } else if (address <= (state.ram_size - 1)) { |
philpem@40 | 375 | // RAM access |
philpem@40 | 376 | data = RD16(state.ram, mapAddr(address, false), state.ram_size - 1); |
philpem@40 | 377 | handled = true; |
philpem@40 | 378 | } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { |
philpem@40 | 379 | // I/O register space, zone A |
philpem@40 | 380 | switch (address & 0x0F0000) { |
philpem@40 | 381 | case 0x000000: // Map RAM access |
philpem@40 | 382 | if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address); |
philpem@40 | 383 | data = RD16(state.map, address, 0x7FF); |
philpem@40 | 384 | handled = true; |
philpem@40 | 385 | break; |
philpem@40 | 386 | case 0x010000: // General Status Register |
philpem@40 | 387 | data = state.genstat; |
philpem@40 | 388 | handled = true; |
philpem@40 | 389 | break; |
philpem@40 | 390 | case 0x020000: // Video RAM |
philpem@40 | 391 | if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address); |
philpem@40 | 392 | data = RD16(state.vram, address, 0x7FFF); |
philpem@40 | 393 | handled = true; |
philpem@40 | 394 | break; |
philpem@40 | 395 | case 0x030000: // Bus Status Register 0 |
philpem@40 | 396 | data = state.bsr0; |
philpem@40 | 397 | handled = true; |
philpem@40 | 398 | break; |
philpem@40 | 399 | case 0x040000: // Bus Status Register 1 |
philpem@40 | 400 | data = state.bsr1; |
philpem@40 | 401 | handled = true; |
philpem@40 | 402 | break; |
philpem@40 | 403 | case 0x050000: // Phone status |
philpem@40 | 404 | break; |
philpem@40 | 405 | case 0x060000: // DMA Count |
philpem@40 | 406 | break; |
philpem@40 | 407 | case 0x070000: // Line Printer Status Register |
philpem@40 | 408 | break; |
philpem@40 | 409 | case 0x080000: // Real Time Clock |
philpem@40 | 410 | break; |
philpem@40 | 411 | case 0x090000: // Phone registers |
philpem@40 | 412 | switch (address & 0x0FF000) { |
philpem@40 | 413 | case 0x090000: // Handset relay |
philpem@40 | 414 | case 0x098000: |
philpem@40 | 415 | break; |
philpem@40 | 416 | case 0x091000: // Line select 2 |
philpem@40 | 417 | case 0x099000: |
philpem@40 | 418 | break; |
philpem@40 | 419 | case 0x092000: // Hook relay 1 |
philpem@40 | 420 | case 0x09A000: |
philpem@40 | 421 | break; |
philpem@40 | 422 | case 0x093000: // Hook relay 2 |
philpem@40 | 423 | case 0x09B000: |
philpem@40 | 424 | break; |
philpem@40 | 425 | case 0x094000: // Line 1 hold |
philpem@40 | 426 | case 0x09C000: |
philpem@40 | 427 | break; |
philpem@40 | 428 | case 0x095000: // Line 2 hold |
philpem@40 | 429 | case 0x09D000: |
philpem@40 | 430 | break; |
philpem@40 | 431 | case 0x096000: // Line 1 A-lead |
philpem@40 | 432 | case 0x09E000: |
philpem@40 | 433 | break; |
philpem@40 | 434 | case 0x097000: // Line 2 A-lead |
philpem@40 | 435 | case 0x09F000: |
philpem@40 | 436 | break; |
philpem@40 | 437 | } |
philpem@40 | 438 | break; |
philpem@40 | 439 | case 0x0A0000: // Miscellaneous Control Register |
philpem@40 | 440 | break; |
philpem@40 | 441 | case 0x0B0000: // TM/DIALWR |
philpem@40 | 442 | break; |
philpem@43 | 443 | case 0x0C0000: // Clear Status Register |
philpem@43 | 444 | handled = true; |
philpem@40 | 445 | break; |
philpem@40 | 446 | case 0x0D0000: // DMA Address Register |
philpem@40 | 447 | break; |
philpem@40 | 448 | case 0x0E0000: // Disk Control Register |
philpem@40 | 449 | break; |
philpem@40 | 450 | case 0x0F0000: // Line Printer Data Register |
philpem@40 | 451 | break; |
philpem@40 | 452 | } |
philpem@40 | 453 | } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) { |
philpem@40 | 454 | // I/O register space, zone B |
philpem@40 | 455 | switch (address & 0xF00000) { |
philpem@40 | 456 | case 0xC00000: // Expansion slots |
philpem@40 | 457 | case 0xD00000: |
philpem@40 | 458 | switch (address & 0xFC0000) { |
philpem@40 | 459 | case 0xC00000: // Expansion slot 0 |
philpem@40 | 460 | case 0xC40000: // Expansion slot 1 |
philpem@40 | 461 | case 0xC80000: // Expansion slot 2 |
philpem@40 | 462 | case 0xCC0000: // Expansion slot 3 |
philpem@40 | 463 | case 0xD00000: // Expansion slot 4 |
philpem@40 | 464 | case 0xD40000: // Expansion slot 5 |
philpem@40 | 465 | case 0xD80000: // Expansion slot 6 |
philpem@40 | 466 | case 0xDC0000: // Expansion slot 7 |
philpem@40 | 467 | fprintf(stderr, "NOTE: RD16 from expansion card space, addr=0x%08X\n", address); |
philpem@40 | 468 | break; |
philpem@40 | 469 | } |
philpem@40 | 470 | break; |
philpem@40 | 471 | case 0xE00000: // HDC, FDC, MCR2 and RTC data bits |
philpem@40 | 472 | case 0xF00000: |
philpem@40 | 473 | switch (address & 0x070000) { |
philpem@40 | 474 | case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller |
philpem@40 | 475 | break; |
philpem@40 | 476 | case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller |
philpem@40 | 477 | break; |
philpem@40 | 478 | case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2 |
philpem@40 | 479 | break; |
philpem@40 | 480 | case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits |
philpem@40 | 481 | break; |
philpem@40 | 482 | case 0x040000: // [ef][4c]xxxx ==> General Control Register |
philpem@40 | 483 | switch (address & 0x077000) { |
philpem@40 | 484 | case 0x040000: // [ef][4c][08]xxx ==> EE |
philpem@40 | 485 | break; |
philpem@40 | 486 | case 0x041000: // [ef][4c][19]xxx ==> P1E |
philpem@40 | 487 | break; |
philpem@40 | 488 | case 0x042000: // [ef][4c][2A]xxx ==> BP |
philpem@40 | 489 | break; |
philpem@40 | 490 | case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP |
philpem@40 | 491 | break; |
philpem@40 | 492 | case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM |
philpem@40 | 493 | break; |
philpem@40 | 494 | case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM |
philpem@40 | 495 | break; |
philpem@40 | 496 | case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT |
philpem@40 | 497 | break; |
philpem@40 | 498 | case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video |
philpem@40 | 499 | break; |
philpem@40 | 500 | } |
philpem@40 | 501 | break; |
philpem@40 | 502 | case 0x050000: // [ef][5d]xxxx ==> 8274 |
philpem@40 | 503 | break; |
philpem@40 | 504 | case 0x060000: // [ef][6e]xxxx ==> Control regs |
philpem@40 | 505 | switch (address & 0x07F000) { |
philpem@40 | 506 | default: |
philpem@40 | 507 | break; |
philpem@40 | 508 | } |
philpem@40 | 509 | break; |
philpem@40 | 510 | case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller |
philpem@40 | 511 | break; |
philpem@40 | 512 | } |
philpem@40 | 513 | } |
philpem@40 | 514 | } |
philpem@40 | 515 | |
philpem@40 | 516 | LOG_NOT_HANDLED_R(32); |
philpem@40 | 517 | return data; |
philpem@40 | 518 | } |
philpem@40 | 519 | |
philpem@40 | 520 | /** |
philpem@40 | 521 | * @brief Read M68K memory, 8-bit |
philpem@40 | 522 | */ |
philpem@40 | 523 | uint32_t m68k_read_memory_8(uint32_t address) |
philpem@40 | 524 | { |
philpem@40 | 525 | uint8_t data = 0xFF; |
philpem@40 | 526 | bool handled = false; |
philpem@40 | 527 | |
philpem@40 | 528 | // If ROMLMAP is set, force system to access ROM |
philpem@40 | 529 | if (!state.romlmap) |
philpem@40 | 530 | address |= 0x800000; |
philpem@40 | 531 | |
philpem@40 | 532 | // Check access permissions |
philpem@40 | 533 | ACCESS_CHECK_RD(address, 8); |
philpem@40 | 534 | |
philpem@40 | 535 | if ((address >= 0x800000) && (address <= 0xBFFFFF)) { |
philpem@40 | 536 | // ROM access |
philpem@40 | 537 | data = RD8(state.rom, address, ROM_SIZE - 1); |
philpem@40 | 538 | handled = true; |
philpem@40 | 539 | } else if (address <= (state.ram_size - 1)) { |
philpem@40 | 540 | // RAM access |
philpem@40 | 541 | data = RD8(state.ram, mapAddr(address, false), state.ram_size - 1); |
philpem@40 | 542 | handled = true; |
philpem@40 | 543 | } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { |
philpem@40 | 544 | // I/O register space, zone A |
philpem@40 | 545 | switch (address & 0x0F0000) { |
philpem@40 | 546 | case 0x000000: // Map RAM access |
philpem@40 | 547 | if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address); |
philpem@40 | 548 | data = RD8(state.map, address, 0x7FF); |
philpem@40 | 549 | handled = true; |
philpem@40 | 550 | break; |
philpem@40 | 551 | case 0x010000: // General Status Register |
philpem@40 | 552 | if ((address & 1) == 0) |
philpem@40 | 553 | data = (state.genstat >> 8) & 0xff; |
philpem@40 | 554 | else |
philpem@40 | 555 | data = (state.genstat) & 0xff; |
philpem@40 | 556 | handled = true; |
philpem@40 | 557 | break; |
philpem@40 | 558 | case 0x020000: // Video RAM |
philpem@40 | 559 | if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address); |
philpem@40 | 560 | data = RD8(state.vram, address, 0x7FFF); |
philpem@40 | 561 | handled = true; |
philpem@40 | 562 | break; |
philpem@40 | 563 | case 0x030000: // Bus Status Register 0 |
philpem@40 | 564 | if ((address & 1) == 0) |
philpem@40 | 565 | data = (state.bsr0 >> 8) & 0xff; |
philpem@40 | 566 | else |
philpem@40 | 567 | data = (state.bsr0) & 0xff; |
philpem@40 | 568 | handled = true; |
philpem@40 | 569 | break; |
philpem@40 | 570 | case 0x040000: // Bus Status Register 1 |
philpem@40 | 571 | if ((address & 1) == 0) |
philpem@40 | 572 | data = (state.bsr1 >> 8) & 0xff; |
philpem@40 | 573 | else |
philpem@40 | 574 | data = (state.bsr1) & 0xff; |
philpem@40 | 575 | handled = true; |
philpem@40 | 576 | break; |
philpem@40 | 577 | case 0x050000: // Phone status |
philpem@40 | 578 | break; |
philpem@40 | 579 | case 0x060000: // DMA Count |
philpem@40 | 580 | break; |
philpem@40 | 581 | case 0x070000: // Line Printer Status Register |
philpem@40 | 582 | break; |
philpem@40 | 583 | case 0x080000: // Real Time Clock |
philpem@40 | 584 | break; |
philpem@40 | 585 | case 0x090000: // Phone registers |
philpem@40 | 586 | switch (address & 0x0FF000) { |
philpem@40 | 587 | case 0x090000: // Handset relay |
philpem@40 | 588 | case 0x098000: |
philpem@40 | 589 | break; |
philpem@40 | 590 | case 0x091000: // Line select 2 |
philpem@40 | 591 | case 0x099000: |
philpem@40 | 592 | break; |
philpem@40 | 593 | case 0x092000: // Hook relay 1 |
philpem@40 | 594 | case 0x09A000: |
philpem@40 | 595 | break; |
philpem@40 | 596 | case 0x093000: // Hook relay 2 |
philpem@40 | 597 | case 0x09B000: |
philpem@40 | 598 | break; |
philpem@40 | 599 | case 0x094000: // Line 1 hold |
philpem@40 | 600 | case 0x09C000: |
philpem@40 | 601 | break; |
philpem@40 | 602 | case 0x095000: // Line 2 hold |
philpem@40 | 603 | case 0x09D000: |
philpem@40 | 604 | break; |
philpem@40 | 605 | case 0x096000: // Line 1 A-lead |
philpem@40 | 606 | case 0x09E000: |
philpem@40 | 607 | break; |
philpem@40 | 608 | case 0x097000: // Line 2 A-lead |
philpem@40 | 609 | case 0x09F000: |
philpem@40 | 610 | break; |
philpem@40 | 611 | } |
philpem@40 | 612 | break; |
philpem@40 | 613 | case 0x0A0000: // Miscellaneous Control Register |
philpem@40 | 614 | break; |
philpem@40 | 615 | case 0x0B0000: // TM/DIALWR |
philpem@40 | 616 | break; |
philpem@43 | 617 | case 0x0C0000: // Clear Status Register |
philpem@43 | 618 | handled = true; |
philpem@40 | 619 | break; |
philpem@40 | 620 | case 0x0D0000: // DMA Address Register |
philpem@40 | 621 | break; |
philpem@40 | 622 | case 0x0E0000: // Disk Control Register |
philpem@40 | 623 | break; |
philpem@40 | 624 | case 0x0F0000: // Line Printer Data Register |
philpem@40 | 625 | break; |
philpem@40 | 626 | } |
philpem@40 | 627 | } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) { |
philpem@40 | 628 | // I/O register space, zone B |
philpem@40 | 629 | switch (address & 0xF00000) { |
philpem@40 | 630 | case 0xC00000: // Expansion slots |
philpem@40 | 631 | case 0xD00000: |
philpem@40 | 632 | switch (address & 0xFC0000) { |
philpem@40 | 633 | case 0xC00000: // Expansion slot 0 |
philpem@40 | 634 | case 0xC40000: // Expansion slot 1 |
philpem@40 | 635 | case 0xC80000: // Expansion slot 2 |
philpem@40 | 636 | case 0xCC0000: // Expansion slot 3 |
philpem@40 | 637 | case 0xD00000: // Expansion slot 4 |
philpem@40 | 638 | case 0xD40000: // Expansion slot 5 |
philpem@40 | 639 | case 0xD80000: // Expansion slot 6 |
philpem@40 | 640 | case 0xDC0000: // Expansion slot 7 |
philpem@40 | 641 | fprintf(stderr, "NOTE: RD8 from expansion card space, addr=0x%08X\n", address); |
philpem@40 | 642 | break; |
philpem@40 | 643 | } |
philpem@40 | 644 | break; |
philpem@40 | 645 | case 0xE00000: // HDC, FDC, MCR2 and RTC data bits |
philpem@40 | 646 | case 0xF00000: |
philpem@40 | 647 | switch (address & 0x070000) { |
philpem@40 | 648 | case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller |
philpem@40 | 649 | break; |
philpem@40 | 650 | case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller |
philpem@40 | 651 | break; |
philpem@40 | 652 | case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2 |
philpem@40 | 653 | break; |
philpem@40 | 654 | case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits |
philpem@40 | 655 | break; |
philpem@40 | 656 | case 0x040000: // [ef][4c]xxxx ==> General Control Register |
philpem@40 | 657 | switch (address & 0x077000) { |
philpem@40 | 658 | case 0x040000: // [ef][4c][08]xxx ==> EE |
philpem@40 | 659 | break; |
philpem@40 | 660 | case 0x041000: // [ef][4c][19]xxx ==> P1E |
philpem@40 | 661 | break; |
philpem@40 | 662 | case 0x042000: // [ef][4c][2A]xxx ==> BP |
philpem@40 | 663 | break; |
philpem@40 | 664 | case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP |
philpem@40 | 665 | break; |
philpem@40 | 666 | case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM |
philpem@40 | 667 | break; |
philpem@40 | 668 | case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM |
philpem@40 | 669 | break; |
philpem@40 | 670 | case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT |
philpem@40 | 671 | break; |
philpem@40 | 672 | case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video |
philpem@40 | 673 | break; |
philpem@40 | 674 | } |
philpem@40 | 675 | case 0x050000: // [ef][5d]xxxx ==> 8274 |
philpem@40 | 676 | break; |
philpem@40 | 677 | case 0x060000: // [ef][6e]xxxx ==> Control regs |
philpem@40 | 678 | switch (address & 0x07F000) { |
philpem@40 | 679 | default: |
philpem@40 | 680 | break; |
philpem@40 | 681 | } |
philpem@40 | 682 | break; |
philpem@40 | 683 | case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller |
philpem@40 | 684 | break; |
philpem@40 | 685 | } |
philpem@40 | 686 | } |
philpem@40 | 687 | } |
philpem@40 | 688 | |
philpem@40 | 689 | LOG_NOT_HANDLED_R(8); |
philpem@40 | 690 | |
philpem@40 | 691 | return data; |
philpem@40 | 692 | } |
philpem@40 | 693 | |
philpem@40 | 694 | /** |
philpem@40 | 695 | * @brief Write M68K memory, 32-bit |
philpem@40 | 696 | */ |
philpem@40 | 697 | void m68k_write_memory_32(uint32_t address, uint32_t value) |
philpem@40 | 698 | { |
philpem@40 | 699 | bool handled = false; |
philpem@40 | 700 | |
philpem@40 | 701 | // If ROMLMAP is set, force system to access ROM |
philpem@40 | 702 | if (!state.romlmap) |
philpem@40 | 703 | address |= 0x800000; |
philpem@40 | 704 | |
philpem@40 | 705 | // Check access permissions |
philpem@40 | 706 | ACCESS_CHECK_WR(address, 32); |
philpem@40 | 707 | |
philpem@40 | 708 | if ((address >= 0x800000) && (address <= 0xBFFFFF)) { |
philpem@40 | 709 | // ROM access |
philpem@40 | 710 | handled = true; |
philpem@40 | 711 | } else if (address <= (state.ram_size - 1)) { |
philpem@40 | 712 | // RAM access |
philpem@40 | 713 | WR32(state.ram, mapAddr(address, false), state.ram_size - 1, value); |
philpem@40 | 714 | handled = true; |
philpem@40 | 715 | } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { |
philpem@40 | 716 | // I/O register space, zone A |
philpem@40 | 717 | switch (address & 0x0F0000) { |
philpem@40 | 718 | case 0x000000: // Map RAM access |
philpem@40 | 719 | if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X, data=0x%08X\n", address, value); |
philpem@40 | 720 | WR32(state.map, address, 0x7FF, value); |
philpem@40 | 721 | handled = true; |
philpem@40 | 722 | break; |
philpem@40 | 723 | case 0x010000: // General Status Register |
philpem@40 | 724 | state.genstat = (value & 0xffff); |
philpem@40 | 725 | handled = true; |
philpem@40 | 726 | break; |
philpem@40 | 727 | case 0x020000: // Video RAM |
philpem@40 | 728 | if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X, data=0x%08X\n", address, value); |
philpem@40 | 729 | WR32(state.vram, address, 0x7FFF, value); |
philpem@40 | 730 | handled = true; |
philpem@40 | 731 | break; |
philpem@40 | 732 | case 0x030000: // Bus Status Register 0 |
philpem@40 | 733 | break; |
philpem@40 | 734 | case 0x040000: // Bus Status Register 1 |
philpem@40 | 735 | break; |
philpem@40 | 736 | case 0x050000: // Phone status |
philpem@40 | 737 | break; |
philpem@40 | 738 | case 0x060000: // DMA Count |
philpem@40 | 739 | break; |
philpem@40 | 740 | case 0x070000: // Line Printer Status Register |
philpem@40 | 741 | break; |
philpem@40 | 742 | case 0x080000: // Real Time Clock |
philpem@40 | 743 | break; |
philpem@40 | 744 | case 0x090000: // Phone registers |
philpem@40 | 745 | switch (address & 0x0FF000) { |
philpem@40 | 746 | case 0x090000: // Handset relay |
philpem@40 | 747 | case 0x098000: |
philpem@40 | 748 | break; |
philpem@40 | 749 | case 0x091000: // Line select 2 |
philpem@40 | 750 | case 0x099000: |
philpem@40 | 751 | break; |
philpem@40 | 752 | case 0x092000: // Hook relay 1 |
philpem@40 | 753 | case 0x09A000: |
philpem@40 | 754 | break; |
philpem@40 | 755 | case 0x093000: // Hook relay 2 |
philpem@40 | 756 | case 0x09B000: |
philpem@40 | 757 | break; |
philpem@40 | 758 | case 0x094000: // Line 1 hold |
philpem@40 | 759 | case 0x09C000: |
philpem@40 | 760 | break; |
philpem@40 | 761 | case 0x095000: // Line 2 hold |
philpem@40 | 762 | case 0x09D000: |
philpem@40 | 763 | break; |
philpem@40 | 764 | case 0x096000: // Line 1 A-lead |
philpem@40 | 765 | case 0x09E000: |
philpem@40 | 766 | break; |
philpem@40 | 767 | case 0x097000: // Line 2 A-lead |
philpem@40 | 768 | case 0x09F000: |
philpem@40 | 769 | break; |
philpem@40 | 770 | } |
philpem@40 | 771 | break; |
philpem@40 | 772 | case 0x0A0000: // Miscellaneous Control Register |
philpem@40 | 773 | break; |
philpem@40 | 774 | case 0x0B0000: // TM/DIALWR |
philpem@40 | 775 | break; |
philpem@43 | 776 | case 0x0C0000: // Clear Status Register |
philpem@43 | 777 | state.genstat = 0xFFFF; |
philpem@43 | 778 | state.bsr0 = 0xFFFF; |
philpem@43 | 779 | state.bsr1 = 0xFFFF; |
philpem@43 | 780 | handled = true; |
philpem@40 | 781 | break; |
philpem@40 | 782 | case 0x0D0000: // DMA Address Register |
philpem@40 | 783 | break; |
philpem@40 | 784 | case 0x0E0000: // Disk Control Register |
philpem@40 | 785 | break; |
philpem@40 | 786 | case 0x0F0000: // Line Printer Data Register |
philpem@40 | 787 | break; |
philpem@40 | 788 | } |
philpem@40 | 789 | } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) { |
philpem@40 | 790 | // I/O register space, zone B |
philpem@40 | 791 | switch (address & 0xF00000) { |
philpem@40 | 792 | case 0xC00000: // Expansion slots |
philpem@40 | 793 | case 0xD00000: |
philpem@40 | 794 | switch (address & 0xFC0000) { |
philpem@40 | 795 | case 0xC00000: // Expansion slot 0 |
philpem@40 | 796 | case 0xC40000: // Expansion slot 1 |
philpem@40 | 797 | case 0xC80000: // Expansion slot 2 |
philpem@40 | 798 | case 0xCC0000: // Expansion slot 3 |
philpem@40 | 799 | case 0xD00000: // Expansion slot 4 |
philpem@40 | 800 | case 0xD40000: // Expansion slot 5 |
philpem@40 | 801 | case 0xD80000: // Expansion slot 6 |
philpem@40 | 802 | case 0xDC0000: // Expansion slot 7 |
philpem@40 | 803 | fprintf(stderr, "NOTE: WR32 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value); |
philpem@40 | 804 | handled = true; |
philpem@40 | 805 | break; |
philpem@40 | 806 | } |
philpem@40 | 807 | break; |
philpem@40 | 808 | case 0xE00000: // HDC, FDC, MCR2 and RTC data bits |
philpem@40 | 809 | case 0xF00000: |
philpem@40 | 810 | switch (address & 0x070000) { |
philpem@40 | 811 | case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller |
philpem@40 | 812 | break; |
philpem@40 | 813 | case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller |
philpem@40 | 814 | break; |
philpem@40 | 815 | case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2 |
philpem@40 | 816 | break; |
philpem@40 | 817 | case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits |
philpem@40 | 818 | break; |
philpem@40 | 819 | case 0x040000: // [ef][4c]xxxx ==> General Control Register |
philpem@40 | 820 | switch (address & 0x077000) { |
philpem@40 | 821 | case 0x040000: // [ef][4c][08]xxx ==> EE |
philpem@40 | 822 | break; |
philpem@40 | 823 | case 0x041000: // [ef][4c][19]xxx ==> P1E |
philpem@40 | 824 | break; |
philpem@40 | 825 | case 0x042000: // [ef][4c][2A]xxx ==> BP |
philpem@40 | 826 | break; |
philpem@40 | 827 | case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP |
philpem@40 | 828 | state.romlmap = ((value & 0x8000) == 0x8000); |
philpem@40 | 829 | break; |
philpem@40 | 830 | case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM |
philpem@40 | 831 | break; |
philpem@40 | 832 | case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM |
philpem@40 | 833 | break; |
philpem@40 | 834 | case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT |
philpem@40 | 835 | break; |
philpem@40 | 836 | case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video |
philpem@40 | 837 | break; |
philpem@40 | 838 | } |
philpem@40 | 839 | case 0x050000: // [ef][5d]xxxx ==> 8274 |
philpem@40 | 840 | break; |
philpem@40 | 841 | case 0x060000: // [ef][6e]xxxx ==> Control regs |
philpem@40 | 842 | switch (address & 0x07F000) { |
philpem@40 | 843 | default: |
philpem@40 | 844 | break; |
philpem@40 | 845 | } |
philpem@40 | 846 | break; |
philpem@40 | 847 | case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller |
philpem@40 | 848 | break; |
philpem@40 | 849 | } |
philpem@40 | 850 | } |
philpem@40 | 851 | } |
philpem@40 | 852 | |
philpem@40 | 853 | LOG_NOT_HANDLED_W(32); |
philpem@40 | 854 | } |
philpem@40 | 855 | |
philpem@40 | 856 | /** |
philpem@40 | 857 | * @brief Write M68K memory, 16-bit |
philpem@40 | 858 | */ |
philpem@40 | 859 | void m68k_write_memory_16(uint32_t address, uint32_t value) |
philpem@40 | 860 | { |
philpem@40 | 861 | bool handled = false; |
philpem@40 | 862 | |
philpem@40 | 863 | // If ROMLMAP is set, force system to access ROM |
philpem@40 | 864 | if (!state.romlmap) |
philpem@40 | 865 | address |= 0x800000; |
philpem@40 | 866 | |
philpem@40 | 867 | // Check access permissions |
philpem@40 | 868 | ACCESS_CHECK_WR(address, 16); |
philpem@40 | 869 | |
philpem@40 | 870 | if ((address >= 0x800000) && (address <= 0xBFFFFF)) { |
philpem@40 | 871 | // ROM access |
philpem@40 | 872 | handled = true; |
philpem@40 | 873 | } else if (address <= (state.ram_size - 1)) { |
philpem@40 | 874 | // RAM access |
philpem@40 | 875 | WR16(state.ram, mapAddr(address, false), state.ram_size - 1, value); |
philpem@40 | 876 | handled = true; |
philpem@40 | 877 | } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { |
philpem@40 | 878 | // I/O register space, zone A |
philpem@40 | 879 | switch (address & 0x0F0000) { |
philpem@40 | 880 | case 0x000000: // Map RAM access |
philpem@40 | 881 | if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value); |
philpem@40 | 882 | WR16(state.map, address, 0x7FF, value); |
philpem@40 | 883 | handled = true; |
philpem@40 | 884 | break; |
philpem@40 | 885 | case 0x010000: // General Status Register (read only) |
philpem@40 | 886 | handled = true; |
philpem@40 | 887 | break; |
philpem@40 | 888 | case 0x020000: // Video RAM |
philpem@40 | 889 | if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value); |
philpem@40 | 890 | WR16(state.vram, address, 0x7FFF, value); |
philpem@40 | 891 | handled = true; |
philpem@40 | 892 | break; |
philpem@40 | 893 | case 0x030000: // Bus Status Register 0 (read only) |
philpem@40 | 894 | handled = true; |
philpem@40 | 895 | break; |
philpem@40 | 896 | case 0x040000: // Bus Status Register 1 (read only) |
philpem@40 | 897 | handled = true; |
philpem@40 | 898 | break; |
philpem@40 | 899 | case 0x050000: // Phone status |
philpem@40 | 900 | break; |
philpem@40 | 901 | case 0x060000: // DMA Count |
philpem@40 | 902 | break; |
philpem@40 | 903 | case 0x070000: // Line Printer Status Register |
philpem@40 | 904 | break; |
philpem@40 | 905 | case 0x080000: // Real Time Clock |
philpem@40 | 906 | break; |
philpem@40 | 907 | case 0x090000: // Phone registers |
philpem@40 | 908 | switch (address & 0x0FF000) { |
philpem@40 | 909 | case 0x090000: // Handset relay |
philpem@40 | 910 | case 0x098000: |
philpem@40 | 911 | break; |
philpem@40 | 912 | case 0x091000: // Line select 2 |
philpem@40 | 913 | case 0x099000: |
philpem@40 | 914 | break; |
philpem@40 | 915 | case 0x092000: // Hook relay 1 |
philpem@40 | 916 | case 0x09A000: |
philpem@40 | 917 | break; |
philpem@40 | 918 | case 0x093000: // Hook relay 2 |
philpem@40 | 919 | case 0x09B000: |
philpem@40 | 920 | break; |
philpem@40 | 921 | case 0x094000: // Line 1 hold |
philpem@40 | 922 | case 0x09C000: |
philpem@40 | 923 | break; |
philpem@40 | 924 | case 0x095000: // Line 2 hold |
philpem@40 | 925 | case 0x09D000: |
philpem@40 | 926 | break; |
philpem@40 | 927 | case 0x096000: // Line 1 A-lead |
philpem@40 | 928 | case 0x09E000: |
philpem@40 | 929 | break; |
philpem@40 | 930 | case 0x097000: // Line 2 A-lead |
philpem@40 | 931 | case 0x09F000: |
philpem@40 | 932 | break; |
philpem@40 | 933 | } |
philpem@40 | 934 | break; |
philpem@40 | 935 | case 0x0A0000: // Miscellaneous Control Register |
philpem@40 | 936 | break; |
philpem@40 | 937 | case 0x0B0000: // TM/DIALWR |
philpem@40 | 938 | break; |
philpem@43 | 939 | case 0x0C0000: // Clear Status Register |
philpem@43 | 940 | state.genstat = 0xFFFF; |
philpem@43 | 941 | state.bsr0 = 0xFFFF; |
philpem@43 | 942 | state.bsr1 = 0xFFFF; |
philpem@43 | 943 | handled = true; |
philpem@40 | 944 | break; |
philpem@40 | 945 | case 0x0D0000: // DMA Address Register |
philpem@40 | 946 | break; |
philpem@40 | 947 | case 0x0E0000: // Disk Control Register |
philpem@40 | 948 | break; |
philpem@40 | 949 | case 0x0F0000: // Line Printer Data Register |
philpem@40 | 950 | break; |
philpem@40 | 951 | } |
philpem@40 | 952 | } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) { |
philpem@40 | 953 | // I/O register space, zone B |
philpem@40 | 954 | switch (address & 0xF00000) { |
philpem@40 | 955 | case 0xC00000: // Expansion slots |
philpem@40 | 956 | case 0xD00000: |
philpem@40 | 957 | switch (address & 0xFC0000) { |
philpem@40 | 958 | case 0xC00000: // Expansion slot 0 |
philpem@40 | 959 | case 0xC40000: // Expansion slot 1 |
philpem@40 | 960 | case 0xC80000: // Expansion slot 2 |
philpem@40 | 961 | case 0xCC0000: // Expansion slot 3 |
philpem@40 | 962 | case 0xD00000: // Expansion slot 4 |
philpem@40 | 963 | case 0xD40000: // Expansion slot 5 |
philpem@40 | 964 | case 0xD80000: // Expansion slot 6 |
philpem@40 | 965 | case 0xDC0000: // Expansion slot 7 |
philpem@40 | 966 | fprintf(stderr, "NOTE: WR16 to expansion card space, addr=0x%08X, data=0x%04X\n", address, value); |
philpem@40 | 967 | break; |
philpem@40 | 968 | } |
philpem@40 | 969 | break; |
philpem@40 | 970 | case 0xE00000: // HDC, FDC, MCR2 and RTC data bits |
philpem@40 | 971 | case 0xF00000: |
philpem@40 | 972 | switch (address & 0x070000) { |
philpem@40 | 973 | case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller |
philpem@40 | 974 | break; |
philpem@40 | 975 | case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller |
philpem@40 | 976 | break; |
philpem@40 | 977 | case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2 |
philpem@40 | 978 | break; |
philpem@40 | 979 | case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits |
philpem@40 | 980 | break; |
philpem@40 | 981 | case 0x040000: // [ef][4c]xxxx ==> General Control Register |
philpem@40 | 982 | switch (address & 0x077000) { |
philpem@40 | 983 | case 0x040000: // [ef][4c][08]xxx ==> EE |
philpem@40 | 984 | break; |
philpem@40 | 985 | case 0x041000: // [ef][4c][19]xxx ==> P1E |
philpem@40 | 986 | break; |
philpem@40 | 987 | case 0x042000: // [ef][4c][2A]xxx ==> BP |
philpem@40 | 988 | break; |
philpem@40 | 989 | case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP |
philpem@40 | 990 | state.romlmap = ((value & 0x8000) == 0x8000); |
philpem@40 | 991 | handled = true; |
philpem@40 | 992 | break; |
philpem@40 | 993 | case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM |
philpem@40 | 994 | break; |
philpem@40 | 995 | case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM |
philpem@40 | 996 | break; |
philpem@40 | 997 | case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT |
philpem@40 | 998 | break; |
philpem@40 | 999 | case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video |
philpem@40 | 1000 | break; |
philpem@40 | 1001 | } |
philpem@40 | 1002 | case 0x050000: // [ef][5d]xxxx ==> 8274 |
philpem@40 | 1003 | break; |
philpem@40 | 1004 | case 0x060000: // [ef][6e]xxxx ==> Control regs |
philpem@40 | 1005 | switch (address & 0x07F000) { |
philpem@40 | 1006 | default: |
philpem@40 | 1007 | break; |
philpem@40 | 1008 | } |
philpem@40 | 1009 | break; |
philpem@40 | 1010 | case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller |
philpem@40 | 1011 | break; |
philpem@40 | 1012 | } |
philpem@40 | 1013 | } |
philpem@40 | 1014 | } |
philpem@40 | 1015 | |
philpem@40 | 1016 | LOG_NOT_HANDLED_W(16); |
philpem@40 | 1017 | } |
philpem@40 | 1018 | |
philpem@40 | 1019 | /** |
philpem@40 | 1020 | * @brief Write M68K memory, 8-bit |
philpem@40 | 1021 | */ |
philpem@40 | 1022 | void m68k_write_memory_8(uint32_t address, uint32_t value) |
philpem@40 | 1023 | { |
philpem@40 | 1024 | bool handled = false; |
philpem@40 | 1025 | |
philpem@40 | 1026 | // If ROMLMAP is set, force system to access ROM |
philpem@40 | 1027 | if (!state.romlmap) |
philpem@40 | 1028 | address |= 0x800000; |
philpem@40 | 1029 | |
philpem@40 | 1030 | // Check access permissions |
philpem@40 | 1031 | ACCESS_CHECK_WR(address, 8); |
philpem@40 | 1032 | |
philpem@40 | 1033 | if ((address >= 0x800000) && (address <= 0xBFFFFF)) { |
philpem@40 | 1034 | // ROM access (read only!) |
philpem@40 | 1035 | handled = true; |
philpem@40 | 1036 | } else if (address <= (state.ram_size - 1)) { |
philpem@40 | 1037 | // RAM access |
philpem@40 | 1038 | WR8(state.ram, mapAddr(address, false), state.ram_size - 1, value); |
philpem@40 | 1039 | handled = true; |
philpem@40 | 1040 | } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) { |
philpem@40 | 1041 | // I/O register space, zone A |
philpem@40 | 1042 | switch (address & 0x0F0000) { |
philpem@40 | 1043 | case 0x000000: // Map RAM access |
philpem@40 | 1044 | if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=%08X, data=%02X\n", address, value); |
philpem@40 | 1045 | WR8(state.map, address, 0x7FF, value); |
philpem@40 | 1046 | handled = true; |
philpem@40 | 1047 | break; |
philpem@40 | 1048 | case 0x010000: // General Status Register |
philpem@40 | 1049 | handled = true; |
philpem@40 | 1050 | break; |
philpem@40 | 1051 | case 0x020000: // Video RAM |
philpem@40 | 1052 | if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=%08X\n, data=0x%02X", address, value); |
philpem@40 | 1053 | WR8(state.vram, address, 0x7FFF, value); |
philpem@40 | 1054 | handled = true; |
philpem@40 | 1055 | break; |
philpem@40 | 1056 | case 0x030000: // Bus Status Register 0 |
philpem@40 | 1057 | handled = true; |
philpem@40 | 1058 | break; |
philpem@40 | 1059 | case 0x040000: // Bus Status Register 1 |
philpem@40 | 1060 | handled = true; |
philpem@40 | 1061 | break; |
philpem@40 | 1062 | case 0x050000: // Phone status |
philpem@40 | 1063 | break; |
philpem@40 | 1064 | case 0x060000: // DMA Count |
philpem@40 | 1065 | break; |
philpem@40 | 1066 | case 0x070000: // Line Printer Status Register |
philpem@40 | 1067 | break; |
philpem@40 | 1068 | case 0x080000: // Real Time Clock |
philpem@40 | 1069 | break; |
philpem@40 | 1070 | case 0x090000: // Phone registers |
philpem@40 | 1071 | switch (address & 0x0FF000) { |
philpem@40 | 1072 | case 0x090000: // Handset relay |
philpem@40 | 1073 | case 0x098000: |
philpem@40 | 1074 | break; |
philpem@40 | 1075 | case 0x091000: // Line select 2 |
philpem@40 | 1076 | case 0x099000: |
philpem@40 | 1077 | break; |
philpem@40 | 1078 | case 0x092000: // Hook relay 1 |
philpem@40 | 1079 | case 0x09A000: |
philpem@40 | 1080 | break; |
philpem@40 | 1081 | case 0x093000: // Hook relay 2 |
philpem@40 | 1082 | case 0x09B000: |
philpem@40 | 1083 | break; |
philpem@40 | 1084 | case 0x094000: // Line 1 hold |
philpem@40 | 1085 | case 0x09C000: |
philpem@40 | 1086 | break; |
philpem@40 | 1087 | case 0x095000: // Line 2 hold |
philpem@40 | 1088 | case 0x09D000: |
philpem@40 | 1089 | break; |
philpem@40 | 1090 | case 0x096000: // Line 1 A-lead |
philpem@40 | 1091 | case 0x09E000: |
philpem@40 | 1092 | break; |
philpem@40 | 1093 | case 0x097000: // Line 2 A-lead |
philpem@40 | 1094 | case 0x09F000: |
philpem@40 | 1095 | break; |
philpem@40 | 1096 | } |
philpem@40 | 1097 | break; |
philpem@40 | 1098 | case 0x0A0000: // Miscellaneous Control Register |
philpem@40 | 1099 | break; |
philpem@40 | 1100 | case 0x0B0000: // TM/DIALWR |
philpem@40 | 1101 | break; |
philpem@43 | 1102 | case 0x0C0000: // Clear Status Register |
philpem@43 | 1103 | state.genstat = 0xFFFF; |
philpem@43 | 1104 | state.bsr0 = 0xFFFF; |
philpem@43 | 1105 | state.bsr1 = 0xFFFF; |
philpem@43 | 1106 | handled = true; |
philpem@40 | 1107 | break; |
philpem@40 | 1108 | case 0x0D0000: // DMA Address Register |
philpem@40 | 1109 | break; |
philpem@40 | 1110 | case 0x0E0000: // Disk Control Register |
philpem@40 | 1111 | break; |
philpem@40 | 1112 | case 0x0F0000: // Line Printer Data Register |
philpem@40 | 1113 | break; |
philpem@40 | 1114 | } |
philpem@40 | 1115 | } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) { |
philpem@40 | 1116 | // I/O register space, zone B |
philpem@40 | 1117 | switch (address & 0xF00000) { |
philpem@40 | 1118 | case 0xC00000: // Expansion slots |
philpem@40 | 1119 | case 0xD00000: |
philpem@40 | 1120 | switch (address & 0xFC0000) { |
philpem@40 | 1121 | case 0xC00000: // Expansion slot 0 |
philpem@40 | 1122 | case 0xC40000: // Expansion slot 1 |
philpem@40 | 1123 | case 0xC80000: // Expansion slot 2 |
philpem@40 | 1124 | case 0xCC0000: // Expansion slot 3 |
philpem@40 | 1125 | case 0xD00000: // Expansion slot 4 |
philpem@40 | 1126 | case 0xD40000: // Expansion slot 5 |
philpem@40 | 1127 | case 0xD80000: // Expansion slot 6 |
philpem@40 | 1128 | case 0xDC0000: // Expansion slot 7 |
philpem@40 | 1129 | fprintf(stderr, "NOTE: WR8 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value); |
philpem@40 | 1130 | break; |
philpem@40 | 1131 | } |
philpem@40 | 1132 | break; |
philpem@40 | 1133 | case 0xE00000: // HDC, FDC, MCR2 and RTC data bits |
philpem@40 | 1134 | case 0xF00000: |
philpem@40 | 1135 | switch (address & 0x070000) { |
philpem@40 | 1136 | case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller |
philpem@40 | 1137 | break; |
philpem@40 | 1138 | case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller |
philpem@40 | 1139 | break; |
philpem@40 | 1140 | case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2 |
philpem@40 | 1141 | break; |
philpem@40 | 1142 | case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits |
philpem@40 | 1143 | break; |
philpem@40 | 1144 | case 0x040000: // [ef][4c]xxxx ==> General Control Register |
philpem@40 | 1145 | switch (address & 0x077000) { |
philpem@40 | 1146 | case 0x040000: // [ef][4c][08]xxx ==> EE |
philpem@40 | 1147 | break; |
philpem@40 | 1148 | case 0x041000: // [ef][4c][19]xxx ==> P1E |
philpem@40 | 1149 | break; |
philpem@40 | 1150 | case 0x042000: // [ef][4c][2A]xxx ==> BP |
philpem@40 | 1151 | break; |
philpem@40 | 1152 | case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP |
philpem@40 | 1153 | if ((address & 1) == 0) |
philpem@40 | 1154 | state.romlmap = ((value & 0x80) == 0x80); |
philpem@40 | 1155 | handled = true; |
philpem@40 | 1156 | break; |
philpem@40 | 1157 | case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM |
philpem@40 | 1158 | break; |
philpem@40 | 1159 | case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM |
philpem@40 | 1160 | break; |
philpem@40 | 1161 | case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT |
philpem@40 | 1162 | break; |
philpem@40 | 1163 | case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video |
philpem@40 | 1164 | break; |
philpem@40 | 1165 | } |
philpem@40 | 1166 | case 0x050000: // [ef][5d]xxxx ==> 8274 |
philpem@40 | 1167 | break; |
philpem@40 | 1168 | case 0x060000: // [ef][6e]xxxx ==> Control regs |
philpem@40 | 1169 | switch (address & 0x07F000) { |
philpem@40 | 1170 | default: |
philpem@40 | 1171 | break; |
philpem@40 | 1172 | } |
philpem@40 | 1173 | break; |
philpem@40 | 1174 | case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller |
philpem@40 | 1175 | break; |
philpem@40 | 1176 | default: |
philpem@40 | 1177 | fprintf(stderr, "NOTE: WR8 to undefined E/F-block space, addr=0x%08X, data=0x%08X\n", address, value); |
philpem@40 | 1178 | break; |
philpem@40 | 1179 | } |
philpem@40 | 1180 | } |
philpem@40 | 1181 | } |
philpem@40 | 1182 | |
philpem@40 | 1183 | LOG_NOT_HANDLED_W(8); |
philpem@40 | 1184 | } |
philpem@40 | 1185 | |
philpem@40 | 1186 | |
philpem@40 | 1187 | // for the disassembler |
philpem@40 | 1188 | uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); } |
philpem@40 | 1189 | uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); } |
philpem@40 | 1190 | uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); } |
philpem@40 | 1191 | |
philpem@40 | 1192 |