src/memory.c

Tue, 28 Dec 2010 18:19:48 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Tue, 28 Dec 2010 18:19:48 +0000
changeset 64
5005879cb6fc
parent 63
f772d3c40531
child 65
dc28926b353c
permissions
-rw-r--r--

turn logging of unhandled I/O R/W ops back on

philpem@40 1 #include <stdio.h>
philpem@40 2 #include <stdlib.h>
philpem@40 3 #include <stdint.h>
philpem@40 4 #include <stdbool.h>
philpem@59 5 #include <assert.h>
philpem@40 6 #include "musashi/m68k.h"
philpem@40 7 #include "state.h"
philpem@40 8 #include "memory.h"
philpem@40 9
philpem@40 10 /******************
philpem@40 11 * Memory mapping
philpem@40 12 ******************/
philpem@40 13
philpem@40 14 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
philpem@40 15
philpem@59 16 uint32_t mapAddr(uint32_t addr, bool writing)/*{{{*/
philpem@40 17 {
philpem@40 18 if (addr < 0x400000) {
philpem@40 19 // RAM access. Check against the Map RAM
philpem@40 20 // Start by getting the original page address
philpem@40 21 uint16_t page = (addr >> 12) & 0x3FF;
philpem@40 22
philpem@40 23 // Look it up in the map RAM and get the physical page address
philpem@40 24 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@40 25
philpem@40 26 // Update the Page Status bits
philpem@40 27 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
philpem@40 28 if (pagebits != 0) {
philpem@40 29 if (writing)
philpem@40 30 state.map[page*2] |= 0x60; // Page written to (dirty)
philpem@40 31 else
philpem@40 32 state.map[page*2] |= 0x40; // Page accessed but not written
philpem@40 33 }
philpem@40 34
philpem@40 35 // Return the address with the new physical page spliced in
philpem@40 36 return (new_page_addr << 12) + (addr & 0xFFF);
philpem@40 37 } else {
philpem@40 38 // I/O, VRAM or MapRAM space; no mapping is performed or required
philpem@40 39 // TODO: assert here?
philpem@40 40 return addr;
philpem@40 41 }
philpem@59 42 }/*}}}*/
philpem@40 43
philpem@59 44 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)/*{{{*/
philpem@40 45 {
philpem@40 46 // Are we in Supervisor mode?
philpem@40 47 if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
philpem@40 48 // Yes. We can do anything we like.
philpem@40 49 return MEM_ALLOWED;
philpem@40 50
philpem@40 51 // If we're here, then we must be in User mode.
philpem@40 52 // Check that the user didn't access memory outside of the RAM area
philpem@40 53 if (addr >= 0x400000)
philpem@40 54 return MEM_UIE;
philpem@40 55
philpem@40 56 // This leaves us with Page Fault checking. Get the page bits for this page.
philpem@40 57 uint16_t page = (addr >> 12) & 0x3FF;
philpem@40 58 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
philpem@40 59
philpem@40 60 // Check page is present
philpem@40 61 if ((pagebits & 0x03) == 0)
philpem@40 62 return MEM_PAGEFAULT;
philpem@40 63
philpem@40 64 // User attempt to access the kernel
philpem@40 65 // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
philpem@40 66 if (((addr >> 19) & 0x0F) == 0)
philpem@40 67 return MEM_KERNEL;
philpem@40 68
philpem@40 69 // Check page is write enabled
philpem@40 70 if ((pagebits & 0x04) == 0)
philpem@40 71 return MEM_PAGE_NO_WE;
philpem@40 72
philpem@40 73 // Page access allowed.
philpem@40 74 return MEM_ALLOWED;
philpem@59 75 }/*}}}*/
philpem@40 76
philpem@40 77 #undef MAPRAM
philpem@40 78
philpem@40 79
philpem@40 80 /********************************************************
philpem@40 81 * m68k memory read/write support functions for Musashi
philpem@40 82 ********************************************************/
philpem@40 83
philpem@40 84 /**
philpem@40 85 * @brief Check memory access permissions for a write operation.
philpem@40 86 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
philpem@40 87 * gcc throws warnings when you have a return-with-value in a void
philpem@40 88 * function, even if the return-with-value is completely unreachable.
philpem@40 89 * Similarly it doesn't like it if you have a return without a value
philpem@40 90 * in a non-void function, even if it's impossible to ever reach the
philpem@40 91 * return-with-no-value. UGH!
philpem@40 92 */
philpem@59 93 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
philpem@59 94 #define ACCESS_CHECK_WR(address, bits) \
philpem@59 95 do { \
philpem@40 96 bool fault = false; \
philpem@40 97 /* MEM_STATUS st; */ \
philpem@40 98 switch (checkMemoryAccess(address, true)) { \
philpem@40 99 case MEM_ALLOWED: \
philpem@40 100 /* Access allowed */ \
philpem@40 101 break; \
philpem@40 102 case MEM_PAGEFAULT: \
philpem@40 103 /* Page fault */ \
philpem@44 104 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0); \
philpem@40 105 fault = true; \
philpem@40 106 break; \
philpem@40 107 case MEM_UIE: \
philpem@40 108 /* User access to memory above 4MB */ \
philpem@44 109 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0); \
philpem@40 110 fault = true; \
philpem@40 111 break; \
philpem@40 112 case MEM_KERNEL: \
philpem@40 113 case MEM_PAGE_NO_WE: \
philpem@40 114 /* kernel access or page not write enabled */ \
philpem@40 115 /* TODO: which regs need setting? */ \
philpem@40 116 fault = true; \
philpem@40 117 break; \
philpem@40 118 } \
philpem@40 119 \
philpem@40 120 if (fault) { \
philpem@40 121 if (bits >= 16) \
philpem@40 122 state.bsr0 = 0x7F00; \
philpem@40 123 else \
philpem@40 124 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
philpem@40 125 state.bsr0 |= (address >> 16); \
philpem@40 126 state.bsr1 = address & 0xffff; \
philpem@40 127 printf("ERR: BusError WR\n"); \
philpem@40 128 m68k_pulse_bus_error(); \
philpem@40 129 return; \
philpem@40 130 } \
philpem@40 131 } while (false)
philpem@59 132 /*}}}*/
philpem@40 133
philpem@40 134 /**
philpem@40 135 * @brief Check memory access permissions for a read operation.
philpem@40 136 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
philpem@40 137 * gcc throws warnings when you have a return-with-value in a void
philpem@40 138 * function, even if the return-with-value is completely unreachable.
philpem@40 139 * Similarly it doesn't like it if you have a return without a value
philpem@40 140 * in a non-void function, even if it's impossible to ever reach the
philpem@40 141 * return-with-no-value. UGH!
philpem@40 142 */
philpem@59 143 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
philpem@59 144 #define ACCESS_CHECK_RD(address, bits) \
philpem@59 145 do { \
philpem@40 146 bool fault = false; \
philpem@40 147 /* MEM_STATUS st; */ \
philpem@40 148 switch (checkMemoryAccess(address, false)) { \
philpem@40 149 case MEM_ALLOWED: \
philpem@40 150 /* Access allowed */ \
philpem@40 151 break; \
philpem@40 152 case MEM_PAGEFAULT: \
philpem@40 153 /* Page fault */ \
philpem@44 154 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0); \
philpem@40 155 fault = true; \
philpem@40 156 break; \
philpem@40 157 case MEM_UIE: \
philpem@40 158 /* User access to memory above 4MB */ \
philpem@44 159 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0); \
philpem@40 160 fault = true; \
philpem@40 161 break; \
philpem@40 162 case MEM_KERNEL: \
philpem@40 163 case MEM_PAGE_NO_WE: \
philpem@40 164 /* kernel access or page not write enabled */ \
philpem@40 165 /* TODO: which regs need setting? */ \
philpem@40 166 fault = true; \
philpem@40 167 break; \
philpem@40 168 } \
philpem@40 169 \
philpem@40 170 if (fault) { \
philpem@40 171 if (bits >= 16) \
philpem@40 172 state.bsr0 = 0x7F00; \
philpem@40 173 else \
philpem@40 174 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
philpem@40 175 state.bsr0 |= (address >> 16); \
philpem@40 176 state.bsr1 = address & 0xffff; \
philpem@40 177 printf("ERR: BusError RD\n"); \
philpem@40 178 m68k_pulse_bus_error(); \
philpem@40 179 return 0xFFFFFFFF; \
philpem@40 180 } \
philpem@40 181 } while (false)
philpem@59 182 /*}}}*/
philpem@40 183
philpem@40 184 // Logging macros
philpem@59 185 #define LOG_NOT_HANDLED_R(bits) \
philpem@64 186 if (!handled) printf("unhandled read%02d, addr=0x%08X\n", bits, address);
philpem@40 187
philpem@59 188 #define LOG_NOT_HANDLED_W(bits) \
philpem@64 189 if (!handled) printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
philpem@59 190
philpem@59 191 /********************************************************
philpem@59 192 * I/O read/write functions
philpem@59 193 ********************************************************/
philpem@40 194
philpem@40 195 /**
philpem@59 196 * Issue a warning if a read operation is made with an invalid size
philpem@40 197 */
philpem@59 198 inline static void ENFORCE_SIZE(int bits, uint32_t address, int allowed, char *regname)
philpem@40 199 {
philpem@59 200 assert((bits == 8) || (bits == 16) || (bits == 32));
philpem@59 201 if ((bits & allowed) == 0) {
philpem@59 202 printf("WARNING: write to 0x%08X (%s) with invalid size %d!\n", address, regname, bits);
philpem@59 203 }
philpem@59 204 }
philpem@59 205
philpem@59 206 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
philpem@59 207 {
philpem@40 208 bool handled = false;
philpem@40 209
philpem@59 210 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 211 // I/O register space, zone A
philpem@40 212 switch (address & 0x0F0000) {
philpem@40 213 case 0x010000: // General Status Register
philpem@59 214 if (bits == 16)
philpem@59 215 state.genstat = (data & 0xffff);
philpem@59 216 else if (bits == 8) {
philpem@59 217 if (address & 0)
philpem@59 218 state.genstat = data;
philpem@59 219 else
philpem@59 220 state.genstat = data << 8;
philpem@59 221 }
philpem@40 222 handled = true;
philpem@40 223 break;
philpem@40 224 case 0x030000: // Bus Status Register 0
philpem@40 225 break;
philpem@40 226 case 0x040000: // Bus Status Register 1
philpem@40 227 break;
philpem@40 228 case 0x050000: // Phone status
philpem@40 229 break;
philpem@40 230 case 0x060000: // DMA Count
philpem@59 231 ENFORCE_SIZE(bits, address, 16, "DMACOUNT");
philpem@59 232 state.dma_count = (data & 0x3FFF);
philpem@59 233 state.idmarw = ((data & 0x4000) == 0x4000);
philpem@59 234 state.dmaen = ((data & 0x8000) == 0x8000);
philpem@59 235 // This handles the "dummy DMA transfer" mentioned in the docs
philpem@59 236 // TODO: access check, peripheral access
philpem@59 237 if (!state.idmarw)
philpem@60 238 WR32(state.base_ram, mapAddr(address, true), state.base_ram_size - 1, 0xDEAD);
philpem@59 239 state.dma_count++;
philpem@59 240 handled = true;
philpem@59 241 break;
philpem@59 242 case 0x070000: // Line Printer Status Register
philpem@59 243 break;
philpem@59 244 case 0x080000: // Real Time Clock
philpem@59 245 break;
philpem@59 246 case 0x090000: // Phone registers
philpem@59 247 switch (address & 0x0FF000) {
philpem@59 248 case 0x090000: // Handset relay
philpem@59 249 case 0x098000:
philpem@59 250 break;
philpem@59 251 case 0x091000: // Line select 2
philpem@59 252 case 0x099000:
philpem@59 253 break;
philpem@59 254 case 0x092000: // Hook relay 1
philpem@59 255 case 0x09A000:
philpem@59 256 break;
philpem@59 257 case 0x093000: // Hook relay 2
philpem@59 258 case 0x09B000:
philpem@59 259 break;
philpem@59 260 case 0x094000: // Line 1 hold
philpem@59 261 case 0x09C000:
philpem@59 262 break;
philpem@59 263 case 0x095000: // Line 2 hold
philpem@59 264 case 0x09D000:
philpem@59 265 break;
philpem@59 266 case 0x096000: // Line 1 A-lead
philpem@59 267 case 0x09E000:
philpem@59 268 break;
philpem@59 269 case 0x097000: // Line 2 A-lead
philpem@59 270 case 0x09F000:
philpem@59 271 break;
philpem@59 272 }
philpem@59 273 break;
philpem@59 274 case 0x0A0000: // Miscellaneous Control Register
philpem@59 275 ENFORCE_SIZE(bits, address, 16, "MISCCON");
philpem@59 276 // TODO: handle the ctrl bits properly
philpem@59 277 // TODO: &0x8000 --> dismiss 60hz intr
philpem@59 278 state.dma_reading = (data & 0x4000);
philpem@59 279 state.leds = (~data & 0xF00) >> 8;
philpem@59 280 printf("LEDs: %s %s %s %s\n",
philpem@59 281 (state.leds & 8) ? "R" : "-",
philpem@59 282 (state.leds & 4) ? "G" : "-",
philpem@59 283 (state.leds & 2) ? "Y" : "-",
philpem@59 284 (state.leds & 1) ? "R" : "-");
philpem@59 285 handled = true;
philpem@59 286 break;
philpem@59 287 case 0x0B0000: // TM/DIALWR
philpem@59 288 break;
philpem@59 289 case 0x0C0000: // Clear Status Register
philpem@59 290 state.genstat = 0xFFFF;
philpem@59 291 state.bsr0 = 0xFFFF;
philpem@59 292 state.bsr1 = 0xFFFF;
philpem@59 293 handled = true;
philpem@59 294 break;
philpem@59 295 case 0x0D0000: // DMA Address Register
philpem@59 296 if (address & 0x004000) {
philpem@59 297 // A14 high -- set most significant bits
philpem@59 298 state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
philpem@59 299 } else {
philpem@59 300 // A14 low -- set least significant bits
philpem@59 301 state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
philpem@59 302 }
philpem@59 303 handled = true;
philpem@59 304 break;
philpem@59 305 case 0x0E0000: // Disk Control Register
philpem@59 306 ENFORCE_SIZE(bits, address, 16, "DISKCON");
philpem@59 307 // B7 = FDD controller reset
philpem@59 308 if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
philpem@59 309 // B6 = drive 0 select -- TODO
philpem@59 310 // B5 = motor enable -- TODO
philpem@59 311 // B4 = HDD controller reset -- TODO
philpem@59 312 // B3 = HDD0 select -- TODO
philpem@59 313 // B2,1,0 = HDD0 head select
philpem@59 314 handled = true;
philpem@59 315 break;
philpem@59 316 case 0x0F0000: // Line Printer Data Register
philpem@59 317 break;
philpem@59 318 }
philpem@59 319 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@59 320 // I/O register space, zone B
philpem@59 321 switch (address & 0xF00000) {
philpem@59 322 case 0xC00000: // Expansion slots
philpem@59 323 case 0xD00000:
philpem@59 324 switch (address & 0xFC0000) {
philpem@59 325 case 0xC00000: // Expansion slot 0
philpem@59 326 case 0xC40000: // Expansion slot 1
philpem@59 327 case 0xC80000: // Expansion slot 2
philpem@59 328 case 0xCC0000: // Expansion slot 3
philpem@59 329 case 0xD00000: // Expansion slot 4
philpem@59 330 case 0xD40000: // Expansion slot 5
philpem@59 331 case 0xD80000: // Expansion slot 6
philpem@59 332 case 0xDC0000: // Expansion slot 7
philpem@59 333 fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
philpem@59 334 handled = true;
philpem@59 335 break;
philpem@59 336 }
philpem@59 337 break;
philpem@59 338 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@59 339 case 0xF00000:
philpem@59 340 switch (address & 0x070000) {
philpem@59 341 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@59 342 break;
philpem@59 343 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@59 344 ENFORCE_SIZE(bits, address, 16, "FDC REGISTERS");
philpem@59 345 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
philpem@59 346 handled = true;
philpem@59 347 break;
philpem@59 348 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@59 349 break;
philpem@59 350 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@59 351 break;
philpem@59 352 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@59 353 switch (address & 0x077000) {
philpem@59 354 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@59 355 break;
philpem@59 356 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@59 357 ENFORCE_SIZE(bits, address, 16, "PIE");
philpem@59 358 state.pie = ((data & 0x8000) == 0x8000);
philpem@59 359 handled = true;
philpem@59 360 break;
philpem@59 361 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@59 362 break;
philpem@59 363 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@59 364 ENFORCE_SIZE(bits, address, 16, "ROMLMAP");
philpem@59 365 state.romlmap = ((data & 0x8000) == 0x8000);
philpem@59 366 handled = true;
philpem@59 367 break;
philpem@59 368 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@59 369 ENFORCE_SIZE(bits, address, 16, "L1 MODEM");
philpem@59 370 break;
philpem@59 371 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@59 372 ENFORCE_SIZE(bits, address, 16, "L2 MODEM");
philpem@59 373 break;
philpem@59 374 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@59 375 ENFORCE_SIZE(bits, address, 16, "D/N CONNECT");
philpem@59 376 break;
philpem@59 377 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@59 378 ENFORCE_SIZE(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
philpem@59 379 break;
philpem@59 380 }
philpem@59 381 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@59 382 break;
philpem@59 383 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@59 384 switch (address & 0x07F000) {
philpem@59 385 default:
philpem@59 386 break;
philpem@59 387 }
philpem@59 388 break;
philpem@59 389 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@59 390 break;
philpem@59 391 }
philpem@59 392 }
philpem@59 393 }
philpem@64 394
philpem@64 395 LOG_NOT_HANDLED_W(bits);
philpem@59 396 }/*}}}*/
philpem@59 397
philpem@59 398 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
philpem@59 399 {
philpem@59 400 bool handled = false;
philpem@59 401 uint32_t data = 0xFFFFFFFF;
philpem@59 402
philpem@59 403 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@59 404 // I/O register space, zone A
philpem@59 405 switch (address & 0x0F0000) {
philpem@59 406 case 0x010000: // General Status Register
philpem@59 407 ENFORCE_SIZE(bits, address, 16, "GENSTAT");
philpem@59 408 return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
philpem@59 409 break;
philpem@59 410 case 0x030000: // Bus Status Register 0
philpem@59 411 ENFORCE_SIZE(bits, address, 16, "BSR0");
philpem@59 412 return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
philpem@59 413 break;
philpem@59 414 case 0x040000: // Bus Status Register 1
philpem@59 415 ENFORCE_SIZE(bits, address, 16, "BSR1");
philpem@59 416 return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
philpem@59 417 break;
philpem@59 418 case 0x050000: // Phone status
philpem@59 419 ENFORCE_SIZE(bits, address, 16, "PHONE STATUS");
philpem@59 420 break;
philpem@59 421 case 0x060000: // DMA Count
philpem@55 422 // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
philpem@55 423 // Bit 14 is always unused, so leave it set
philpem@59 424 ENFORCE_SIZE(bits, address, 16, "DMACOUNT");
philpem@59 425 return (state.dma_count & 0x3fff) | 0xC000;
philpem@40 426 break;
philpem@40 427 case 0x070000: // Line Printer Status Register
philpem@53 428 data = 0x00120012; // no parity error, no line printer error, no irqs from FDD or HDD
philpem@53 429 data |= (state.fdc_ctx.irql) ? 0x00080008 : 0; // FIXME! HACKHACKHACK! shouldn't peek inside FDC structs like this
philpem@59 430 return data;
philpem@40 431 break;
philpem@40 432 case 0x080000: // Real Time Clock
philpem@59 433 printf("READ NOTIMP: Realtime Clock\n");
philpem@40 434 break;
philpem@40 435 case 0x090000: // Phone registers
philpem@40 436 switch (address & 0x0FF000) {
philpem@40 437 case 0x090000: // Handset relay
philpem@40 438 case 0x098000:
philpem@40 439 break;
philpem@40 440 case 0x091000: // Line select 2
philpem@40 441 case 0x099000:
philpem@40 442 break;
philpem@40 443 case 0x092000: // Hook relay 1
philpem@40 444 case 0x09A000:
philpem@40 445 break;
philpem@40 446 case 0x093000: // Hook relay 2
philpem@40 447 case 0x09B000:
philpem@40 448 break;
philpem@40 449 case 0x094000: // Line 1 hold
philpem@40 450 case 0x09C000:
philpem@40 451 break;
philpem@40 452 case 0x095000: // Line 2 hold
philpem@40 453 case 0x09D000:
philpem@40 454 break;
philpem@40 455 case 0x096000: // Line 1 A-lead
philpem@40 456 case 0x09E000:
philpem@40 457 break;
philpem@40 458 case 0x097000: // Line 2 A-lead
philpem@40 459 case 0x09F000:
philpem@40 460 break;
philpem@40 461 }
philpem@40 462 break;
philpem@46 463 case 0x0A0000: // Miscellaneous Control Register -- write only!
philpem@46 464 handled = true;
philpem@40 465 break;
philpem@40 466 case 0x0B0000: // TM/DIALWR
philpem@40 467 break;
philpem@46 468 case 0x0C0000: // Clear Status Register -- write only!
philpem@43 469 handled = true;
philpem@40 470 break;
philpem@40 471 case 0x0D0000: // DMA Address Register
philpem@40 472 break;
philpem@40 473 case 0x0E0000: // Disk Control Register
philpem@40 474 break;
philpem@40 475 case 0x0F0000: // Line Printer Data Register
philpem@40 476 break;
philpem@40 477 }
philpem@40 478 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 479 // I/O register space, zone B
philpem@40 480 switch (address & 0xF00000) {
philpem@40 481 case 0xC00000: // Expansion slots
philpem@40 482 case 0xD00000:
philpem@40 483 switch (address & 0xFC0000) {
philpem@40 484 case 0xC00000: // Expansion slot 0
philpem@40 485 case 0xC40000: // Expansion slot 1
philpem@40 486 case 0xC80000: // Expansion slot 2
philpem@40 487 case 0xCC0000: // Expansion slot 3
philpem@40 488 case 0xD00000: // Expansion slot 4
philpem@40 489 case 0xD40000: // Expansion slot 5
philpem@40 490 case 0xD80000: // Expansion slot 6
philpem@40 491 case 0xDC0000: // Expansion slot 7
philpem@40 492 fprintf(stderr, "NOTE: RD32 from expansion card space, addr=0x%08X\n", address);
philpem@40 493 break;
philpem@40 494 }
philpem@40 495 break;
philpem@40 496 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 497 case 0xF00000:
philpem@40 498 switch (address & 0x070000) {
philpem@40 499 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@40 500 break;
philpem@40 501 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@59 502 ENFORCE_SIZE(bits, address, 16, "FDC REGISTERS");
philpem@59 503 return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
philpem@40 504 break;
philpem@40 505 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 506 break;
philpem@40 507 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 508 break;
philpem@40 509 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 510 switch (address & 0x077000) {
philpem@40 511 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@44 512 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@40 513 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 514 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@44 515 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@44 516 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@44 517 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@44 518 // All write-only registers... TODO: bus error?
philpem@44 519 handled = true;
philpem@40 520 break;
philpem@44 521 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
philpem@40 522 break;
philpem@40 523 }
philpem@40 524 break;
philpem@40 525 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 526 break;
philpem@40 527 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 528 switch (address & 0x07F000) {
philpem@40 529 default:
philpem@40 530 break;
philpem@40 531 }
philpem@40 532 break;
philpem@40 533 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@40 534 break;
philpem@40 535 }
philpem@40 536 }
philpem@40 537 }
philpem@64 538
philpem@64 539 LOG_NOT_HANDLED_R(bits);
philpem@64 540
philpem@59 541 return data;
philpem@59 542 }/*}}}*/
philpem@40 543
philpem@59 544
philpem@59 545 /********************************************************
philpem@59 546 * m68k memory read/write support functions for Musashi
philpem@59 547 ********************************************************/
philpem@59 548
philpem@59 549 /**
philpem@59 550 * @brief Read M68K memory, 32-bit
philpem@59 551 */
philpem@59 552 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
philpem@59 553 {
philpem@59 554 uint32_t data = 0xFFFFFFFF;
philpem@59 555
philpem@59 556 // If ROMLMAP is set, force system to access ROM
philpem@59 557 if (!state.romlmap)
philpem@59 558 address |= 0x800000;
philpem@59 559
philpem@59 560 // Check access permissions
philpem@59 561 ACCESS_CHECK_RD(address, 32);
philpem@59 562
philpem@59 563 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@59 564 // ROM access
philpem@60 565 return RD32(state.rom, address, ROM_SIZE - 1);
philpem@60 566 } else if (address <= 0x3fffff) {
philpem@59 567 // RAM access
philpem@60 568 uint32_t newAddr = mapAddr(address, false);
philpem@63 569 if (newAddr <= 0x1fffff) {
philpem@60 570 return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 571 } else {
philpem@63 572 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
philpem@63 573 return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 574 else
philpem@63 575 return 0xffffffff;
philpem@63 576 }
philpem@59 577 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@59 578 // I/O register space, zone A
philpem@59 579 switch (address & 0x0F0000) {
philpem@59 580 case 0x000000: // Map RAM access
philpem@59 581 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
philpem@60 582 return RD32(state.map, address, 0x7FF);
philpem@59 583 break;
philpem@59 584 case 0x020000: // Video RAM
philpem@59 585 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@60 586 return RD32(state.vram, address, 0x7FFF);
philpem@59 587 break;
philpem@59 588 default:
philpem@60 589 return IoRead(address, 32);
philpem@59 590 }
philpem@59 591 } else {
philpem@60 592 return IoRead(address, 32);
philpem@59 593 }
philpem@59 594
philpem@40 595 return data;
philpem@59 596 }/*}}}*/
philpem@40 597
philpem@40 598 /**
philpem@40 599 * @brief Read M68K memory, 16-bit
philpem@40 600 */
philpem@59 601 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
philpem@40 602 {
philpem@40 603 uint16_t data = 0xFFFF;
philpem@40 604
philpem@40 605 // If ROMLMAP is set, force system to access ROM
philpem@40 606 if (!state.romlmap)
philpem@40 607 address |= 0x800000;
philpem@40 608
philpem@40 609 // Check access permissions
philpem@40 610 ACCESS_CHECK_RD(address, 16);
philpem@40 611
philpem@40 612 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 613 // ROM access
philpem@40 614 data = RD16(state.rom, address, ROM_SIZE - 1);
philpem@60 615 } else if (address <= 0x3fffff) {
philpem@40 616 // RAM access
philpem@60 617 uint32_t newAddr = mapAddr(address, false);
philpem@63 618 if (newAddr <= 0x1fffff) {
philpem@60 619 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 620 } else {
philpem@63 621 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
philpem@63 622 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 623 else
philpem@63 624 return 0xffff;
philpem@63 625 }
philpem@40 626 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 627 // I/O register space, zone A
philpem@40 628 switch (address & 0x0F0000) {
philpem@40 629 case 0x000000: // Map RAM access
philpem@40 630 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 631 data = RD16(state.map, address, 0x7FF);
philpem@40 632 break;
philpem@40 633 case 0x020000: // Video RAM
philpem@40 634 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 635 data = RD16(state.vram, address, 0x7FFF);
philpem@40 636 break;
philpem@59 637 default:
philpem@59 638 data = IoRead(address, 16);
philpem@40 639 }
philpem@59 640 } else {
philpem@59 641 data = IoRead(address, 16);
philpem@40 642 }
philpem@40 643
philpem@40 644 return data;
philpem@59 645 }/*}}}*/
philpem@40 646
philpem@40 647 /**
philpem@40 648 * @brief Read M68K memory, 8-bit
philpem@40 649 */
philpem@59 650 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
philpem@40 651 {
philpem@40 652 uint8_t data = 0xFF;
philpem@40 653
philpem@40 654 // If ROMLMAP is set, force system to access ROM
philpem@40 655 if (!state.romlmap)
philpem@40 656 address |= 0x800000;
philpem@40 657
philpem@40 658 // Check access permissions
philpem@40 659 ACCESS_CHECK_RD(address, 8);
philpem@40 660
philpem@40 661 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 662 // ROM access
philpem@40 663 data = RD8(state.rom, address, ROM_SIZE - 1);
philpem@60 664 } else if (address <= 0x3fffff) {
philpem@40 665 // RAM access
philpem@60 666 uint32_t newAddr = mapAddr(address, false);
philpem@63 667 if (newAddr <= 0x1fffff) {
philpem@60 668 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 669 } else {
philpem@63 670 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
philpem@63 671 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 672 else
philpem@63 673 return 0xff;
philpem@63 674 }
philpem@40 675 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 676 // I/O register space, zone A
philpem@40 677 switch (address & 0x0F0000) {
philpem@40 678 case 0x000000: // Map RAM access
philpem@40 679 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 680 data = RD8(state.map, address, 0x7FF);
philpem@40 681 break;
philpem@40 682 case 0x020000: // Video RAM
philpem@40 683 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 684 data = RD8(state.vram, address, 0x7FFF);
philpem@40 685 break;
philpem@59 686 default:
philpem@59 687 data = IoRead(address, 8);
philpem@40 688 }
philpem@59 689 } else {
philpem@59 690 data = IoRead(address, 8);
philpem@40 691 }
philpem@40 692
philpem@40 693 return data;
philpem@59 694 }/*}}}*/
philpem@40 695
philpem@40 696 /**
philpem@40 697 * @brief Write M68K memory, 32-bit
philpem@40 698 */
philpem@59 699 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
philpem@40 700 {
philpem@40 701 // If ROMLMAP is set, force system to access ROM
philpem@40 702 if (!state.romlmap)
philpem@40 703 address |= 0x800000;
philpem@40 704
philpem@40 705 // Check access permissions
philpem@40 706 ACCESS_CHECK_WR(address, 32);
philpem@40 707
philpem@40 708 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 709 // ROM access
philpem@60 710 } else if (address <= 0x3FFFFF) {
philpem@40 711 // RAM access
philpem@60 712 uint32_t newAddr = mapAddr(address, true);
philpem@63 713 if (newAddr <= 0x1fffff) {
philpem@60 714 WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@63 715 } else {
philpem@63 716 // WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@63 717 }
philpem@40 718 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 719 // I/O register space, zone A
philpem@40 720 switch (address & 0x0F0000) {
philpem@40 721 case 0x000000: // Map RAM access
philpem@59 722 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 723 WR32(state.map, address, 0x7FF, value);
philpem@40 724 break;
philpem@40 725 case 0x020000: // Video RAM
philpem@59 726 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 727 WR32(state.vram, address, 0x7FFF, value);
philpem@40 728 break;
philpem@59 729 default:
philpem@59 730 IoWrite(address, value, 32);
philpem@40 731 }
philpem@59 732 } else {
philpem@59 733 IoWrite(address, value, 32);
philpem@40 734 }
philpem@59 735 }/*}}}*/
philpem@40 736
philpem@40 737 /**
philpem@40 738 * @brief Write M68K memory, 16-bit
philpem@40 739 */
philpem@59 740 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
philpem@40 741 {
philpem@40 742 // If ROMLMAP is set, force system to access ROM
philpem@40 743 if (!state.romlmap)
philpem@40 744 address |= 0x800000;
philpem@40 745
philpem@40 746 // Check access permissions
philpem@40 747 ACCESS_CHECK_WR(address, 16);
philpem@40 748
philpem@40 749 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 750 // ROM access
philpem@60 751 } else if (address <= 0x3FFFFF) {
philpem@40 752 // RAM access
philpem@60 753 uint32_t newAddr = mapAddr(address, true);
philpem@63 754 if (newAddr <= 0x1fffff) {
philpem@60 755 WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@63 756 } else {
philpem@63 757 // WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@63 758 }
philpem@40 759 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 760 // I/O register space, zone A
philpem@40 761 switch (address & 0x0F0000) {
philpem@40 762 case 0x000000: // Map RAM access
philpem@40 763 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 764 WR16(state.map, address, 0x7FF, value);
philpem@40 765 break;
philpem@40 766 case 0x020000: // Video RAM
philpem@40 767 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 768 WR16(state.vram, address, 0x7FFF, value);
philpem@40 769 break;
philpem@59 770 default:
philpem@59 771 IoWrite(address, value, 16);
philpem@40 772 }
philpem@59 773 } else {
philpem@59 774 IoWrite(address, value, 16);
philpem@40 775 }
philpem@59 776 }/*}}}*/
philpem@40 777
philpem@40 778 /**
philpem@40 779 * @brief Write M68K memory, 8-bit
philpem@40 780 */
philpem@59 781 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
philpem@40 782 {
philpem@40 783 // If ROMLMAP is set, force system to access ROM
philpem@40 784 if (!state.romlmap)
philpem@40 785 address |= 0x800000;
philpem@40 786
philpem@40 787 // Check access permissions
philpem@40 788 ACCESS_CHECK_WR(address, 8);
philpem@40 789
philpem@40 790 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 791 // ROM access (read only!)
philpem@60 792 } else if (address <= 0x3FFFFF) {
philpem@40 793 // RAM access
philpem@60 794 uint32_t newAddr = mapAddr(address, true);
philpem@63 795 if (newAddr <= 0x1fffff) {
philpem@60 796 WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@63 797 } else {
philpem@63 798 // WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@63 799 }
philpem@40 800 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 801 // I/O register space, zone A
philpem@40 802 switch (address & 0x0F0000) {
philpem@40 803 case 0x000000: // Map RAM access
philpem@59 804 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 805 WR8(state.map, address, 0x7FF, value);
philpem@40 806 break;
philpem@40 807 case 0x020000: // Video RAM
philpem@59 808 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 809 WR8(state.vram, address, 0x7FFF, value);
philpem@40 810 break;
philpem@59 811 default:
philpem@59 812 IoWrite(address, value, 8);
philpem@40 813 }
philpem@59 814 } else {
philpem@59 815 IoWrite(address, value, 8);
philpem@40 816 }
philpem@59 817 }/*}}}*/
philpem@40 818
philpem@40 819
philpem@40 820 // for the disassembler
philpem@40 821 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
philpem@40 822 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
philpem@40 823 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }
philpem@40 824