src/memory.c

Tue, 28 Dec 2010 19:10:36 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Tue, 28 Dec 2010 19:10:36 +0000
changeset 68
58318104858b
parent 66
8ca92162fa89
child 70
5bbe76e71698
permissions
-rw-r--r--

fix UDS/LDS in bus error handling for 16/32-bit accesses

philpem@40 1 #include <stdio.h>
philpem@40 2 #include <stdlib.h>
philpem@40 3 #include <stdint.h>
philpem@40 4 #include <stdbool.h>
philpem@59 5 #include <assert.h>
philpem@40 6 #include "musashi/m68k.h"
philpem@40 7 #include "state.h"
philpem@40 8 #include "memory.h"
philpem@40 9
philpem@40 10 /******************
philpem@40 11 * Memory mapping
philpem@40 12 ******************/
philpem@40 13
philpem@40 14 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
philpem@40 15
philpem@59 16 uint32_t mapAddr(uint32_t addr, bool writing)/*{{{*/
philpem@40 17 {
philpem@40 18 if (addr < 0x400000) {
philpem@40 19 // RAM access. Check against the Map RAM
philpem@40 20 // Start by getting the original page address
philpem@40 21 uint16_t page = (addr >> 12) & 0x3FF;
philpem@40 22
philpem@40 23 // Look it up in the map RAM and get the physical page address
philpem@40 24 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@40 25
philpem@40 26 // Update the Page Status bits
philpem@40 27 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
philpem@40 28 if (pagebits != 0) {
philpem@40 29 if (writing)
philpem@40 30 state.map[page*2] |= 0x60; // Page written to (dirty)
philpem@40 31 else
philpem@40 32 state.map[page*2] |= 0x40; // Page accessed but not written
philpem@40 33 }
philpem@40 34
philpem@40 35 // Return the address with the new physical page spliced in
philpem@40 36 return (new_page_addr << 12) + (addr & 0xFFF);
philpem@40 37 } else {
philpem@40 38 // I/O, VRAM or MapRAM space; no mapping is performed or required
philpem@40 39 // TODO: assert here?
philpem@40 40 return addr;
philpem@40 41 }
philpem@59 42 }/*}}}*/
philpem@40 43
philpem@59 44 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)/*{{{*/
philpem@40 45 {
philpem@40 46 // Are we in Supervisor mode?
philpem@40 47 if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
philpem@40 48 // Yes. We can do anything we like.
philpem@40 49 return MEM_ALLOWED;
philpem@40 50
philpem@40 51 // If we're here, then we must be in User mode.
philpem@40 52 // Check that the user didn't access memory outside of the RAM area
philpem@40 53 if (addr >= 0x400000)
philpem@40 54 return MEM_UIE;
philpem@40 55
philpem@40 56 // This leaves us with Page Fault checking. Get the page bits for this page.
philpem@40 57 uint16_t page = (addr >> 12) & 0x3FF;
philpem@40 58 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
philpem@40 59
philpem@40 60 // Check page is present
philpem@40 61 if ((pagebits & 0x03) == 0)
philpem@40 62 return MEM_PAGEFAULT;
philpem@40 63
philpem@40 64 // User attempt to access the kernel
philpem@40 65 // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
philpem@40 66 if (((addr >> 19) & 0x0F) == 0)
philpem@40 67 return MEM_KERNEL;
philpem@40 68
philpem@40 69 // Check page is write enabled
philpem@68 70 if (writing && ((pagebits & 0x04) == 0))
philpem@40 71 return MEM_PAGE_NO_WE;
philpem@40 72
philpem@40 73 // Page access allowed.
philpem@40 74 return MEM_ALLOWED;
philpem@59 75 }/*}}}*/
philpem@40 76
philpem@40 77 #undef MAPRAM
philpem@40 78
philpem@40 79
philpem@40 80 /********************************************************
philpem@40 81 * m68k memory read/write support functions for Musashi
philpem@40 82 ********************************************************/
philpem@40 83
philpem@40 84 /**
philpem@40 85 * @brief Check memory access permissions for a write operation.
philpem@40 86 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
philpem@40 87 * gcc throws warnings when you have a return-with-value in a void
philpem@40 88 * function, even if the return-with-value is completely unreachable.
philpem@40 89 * Similarly it doesn't like it if you have a return without a value
philpem@40 90 * in a non-void function, even if it's impossible to ever reach the
philpem@40 91 * return-with-no-value. UGH!
philpem@40 92 */
philpem@59 93 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
philpem@59 94 #define ACCESS_CHECK_WR(address, bits) \
philpem@59 95 do { \
philpem@40 96 bool fault = false; \
philpem@40 97 /* MEM_STATUS st; */ \
philpem@40 98 switch (checkMemoryAccess(address, true)) { \
philpem@40 99 case MEM_ALLOWED: \
philpem@40 100 /* Access allowed */ \
philpem@40 101 break; \
philpem@40 102 case MEM_PAGEFAULT: \
philpem@40 103 /* Page fault */ \
philpem@44 104 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0); \
philpem@40 105 fault = true; \
philpem@40 106 break; \
philpem@40 107 case MEM_UIE: \
philpem@40 108 /* User access to memory above 4MB */ \
philpem@44 109 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0); \
philpem@40 110 fault = true; \
philpem@40 111 break; \
philpem@40 112 case MEM_KERNEL: \
philpem@40 113 case MEM_PAGE_NO_WE: \
philpem@40 114 /* kernel access or page not write enabled */ \
philpem@68 115 /* FIXME: which regs need setting? */ \
philpem@40 116 fault = true; \
philpem@40 117 break; \
philpem@40 118 } \
philpem@40 119 \
philpem@40 120 if (fault) { \
philpem@40 121 if (bits >= 16) \
philpem@68 122 state.bsr0 = 0x7C00; \
philpem@40 123 else \
philpem@40 124 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
philpem@40 125 state.bsr0 |= (address >> 16); \
philpem@40 126 state.bsr1 = address & 0xffff; \
philpem@40 127 printf("ERR: BusError WR\n"); \
philpem@40 128 m68k_pulse_bus_error(); \
philpem@40 129 return; \
philpem@40 130 } \
philpem@40 131 } while (false)
philpem@59 132 /*}}}*/
philpem@40 133
philpem@40 134 /**
philpem@40 135 * @brief Check memory access permissions for a read operation.
philpem@40 136 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
philpem@40 137 * gcc throws warnings when you have a return-with-value in a void
philpem@40 138 * function, even if the return-with-value is completely unreachable.
philpem@40 139 * Similarly it doesn't like it if you have a return without a value
philpem@40 140 * in a non-void function, even if it's impossible to ever reach the
philpem@40 141 * return-with-no-value. UGH!
philpem@40 142 */
philpem@59 143 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
philpem@59 144 #define ACCESS_CHECK_RD(address, bits) \
philpem@59 145 do { \
philpem@40 146 bool fault = false; \
philpem@40 147 /* MEM_STATUS st; */ \
philpem@40 148 switch (checkMemoryAccess(address, false)) { \
philpem@40 149 case MEM_ALLOWED: \
philpem@40 150 /* Access allowed */ \
philpem@40 151 break; \
philpem@40 152 case MEM_PAGEFAULT: \
philpem@40 153 /* Page fault */ \
philpem@44 154 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0); \
philpem@40 155 fault = true; \
philpem@40 156 break; \
philpem@40 157 case MEM_UIE: \
philpem@40 158 /* User access to memory above 4MB */ \
philpem@44 159 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0); \
philpem@40 160 fault = true; \
philpem@40 161 break; \
philpem@40 162 case MEM_KERNEL: \
philpem@40 163 case MEM_PAGE_NO_WE: \
philpem@40 164 /* kernel access or page not write enabled */ \
philpem@68 165 /* FIXME: which regs need setting? */ \
philpem@40 166 fault = true; \
philpem@40 167 break; \
philpem@40 168 } \
philpem@40 169 \
philpem@40 170 if (fault) { \
philpem@40 171 if (bits >= 16) \
philpem@68 172 state.bsr0 = 0x7C00; \
philpem@40 173 else \
philpem@40 174 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
philpem@40 175 state.bsr0 |= (address >> 16); \
philpem@40 176 state.bsr1 = address & 0xffff; \
philpem@40 177 printf("ERR: BusError RD\n"); \
philpem@40 178 m68k_pulse_bus_error(); \
philpem@40 179 return 0xFFFFFFFF; \
philpem@40 180 } \
philpem@40 181 } while (false)
philpem@59 182 /*}}}*/
philpem@40 183
philpem@40 184 // Logging macros
philpem@59 185 #define LOG_NOT_HANDLED_R(bits) \
philpem@64 186 if (!handled) printf("unhandled read%02d, addr=0x%08X\n", bits, address);
philpem@40 187
philpem@59 188 #define LOG_NOT_HANDLED_W(bits) \
philpem@64 189 if (!handled) printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
philpem@59 190
philpem@59 191 /********************************************************
philpem@59 192 * I/O read/write functions
philpem@59 193 ********************************************************/
philpem@40 194
philpem@40 195 /**
philpem@59 196 * Issue a warning if a read operation is made with an invalid size
philpem@40 197 */
philpem@66 198 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
philpem@40 199 {
philpem@59 200 assert((bits == 8) || (bits == 16) || (bits == 32));
philpem@59 201 if ((bits & allowed) == 0) {
philpem@66 202 printf("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
philpem@59 203 }
philpem@59 204 }
philpem@59 205
philpem@66 206 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
philpem@66 207 {
philpem@66 208 ENFORCE_SIZE(bits, address, true, allowed, regname);
philpem@66 209 }
philpem@66 210
philpem@66 211 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
philpem@66 212 {
philpem@66 213 ENFORCE_SIZE(bits, address, false, allowed, regname);
philpem@66 214 }
philpem@66 215
philpem@59 216 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
philpem@59 217 {
philpem@40 218 bool handled = false;
philpem@40 219
philpem@59 220 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 221 // I/O register space, zone A
philpem@40 222 switch (address & 0x0F0000) {
philpem@40 223 case 0x010000: // General Status Register
philpem@59 224 if (bits == 16)
philpem@59 225 state.genstat = (data & 0xffff);
philpem@59 226 else if (bits == 8) {
philpem@59 227 if (address & 0)
philpem@59 228 state.genstat = data;
philpem@59 229 else
philpem@59 230 state.genstat = data << 8;
philpem@59 231 }
philpem@40 232 handled = true;
philpem@40 233 break;
philpem@40 234 case 0x030000: // Bus Status Register 0
philpem@40 235 break;
philpem@40 236 case 0x040000: // Bus Status Register 1
philpem@40 237 break;
philpem@40 238 case 0x050000: // Phone status
philpem@40 239 break;
philpem@40 240 case 0x060000: // DMA Count
philpem@66 241 ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
philpem@59 242 state.dma_count = (data & 0x3FFF);
philpem@59 243 state.idmarw = ((data & 0x4000) == 0x4000);
philpem@59 244 state.dmaen = ((data & 0x8000) == 0x8000);
philpem@59 245 // This handles the "dummy DMA transfer" mentioned in the docs
philpem@59 246 // TODO: access check, peripheral access
philpem@59 247 if (!state.idmarw)
philpem@60 248 WR32(state.base_ram, mapAddr(address, true), state.base_ram_size - 1, 0xDEAD);
philpem@59 249 state.dma_count++;
philpem@59 250 handled = true;
philpem@59 251 break;
philpem@59 252 case 0x070000: // Line Printer Status Register
philpem@59 253 break;
philpem@59 254 case 0x080000: // Real Time Clock
philpem@59 255 break;
philpem@59 256 case 0x090000: // Phone registers
philpem@59 257 switch (address & 0x0FF000) {
philpem@59 258 case 0x090000: // Handset relay
philpem@59 259 case 0x098000:
philpem@59 260 break;
philpem@59 261 case 0x091000: // Line select 2
philpem@59 262 case 0x099000:
philpem@59 263 break;
philpem@59 264 case 0x092000: // Hook relay 1
philpem@59 265 case 0x09A000:
philpem@59 266 break;
philpem@59 267 case 0x093000: // Hook relay 2
philpem@59 268 case 0x09B000:
philpem@59 269 break;
philpem@59 270 case 0x094000: // Line 1 hold
philpem@59 271 case 0x09C000:
philpem@59 272 break;
philpem@59 273 case 0x095000: // Line 2 hold
philpem@59 274 case 0x09D000:
philpem@59 275 break;
philpem@59 276 case 0x096000: // Line 1 A-lead
philpem@59 277 case 0x09E000:
philpem@59 278 break;
philpem@59 279 case 0x097000: // Line 2 A-lead
philpem@59 280 case 0x09F000:
philpem@59 281 break;
philpem@59 282 }
philpem@59 283 break;
philpem@59 284 case 0x0A0000: // Miscellaneous Control Register
philpem@66 285 ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
philpem@59 286 // TODO: handle the ctrl bits properly
philpem@59 287 // TODO: &0x8000 --> dismiss 60hz intr
philpem@59 288 state.dma_reading = (data & 0x4000);
philpem@59 289 state.leds = (~data & 0xF00) >> 8;
philpem@59 290 printf("LEDs: %s %s %s %s\n",
philpem@59 291 (state.leds & 8) ? "R" : "-",
philpem@59 292 (state.leds & 4) ? "G" : "-",
philpem@59 293 (state.leds & 2) ? "Y" : "-",
philpem@59 294 (state.leds & 1) ? "R" : "-");
philpem@59 295 handled = true;
philpem@59 296 break;
philpem@59 297 case 0x0B0000: // TM/DIALWR
philpem@59 298 break;
philpem@59 299 case 0x0C0000: // Clear Status Register
philpem@59 300 state.genstat = 0xFFFF;
philpem@59 301 state.bsr0 = 0xFFFF;
philpem@59 302 state.bsr1 = 0xFFFF;
philpem@59 303 handled = true;
philpem@59 304 break;
philpem@59 305 case 0x0D0000: // DMA Address Register
philpem@59 306 if (address & 0x004000) {
philpem@59 307 // A14 high -- set most significant bits
philpem@59 308 state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
philpem@59 309 } else {
philpem@59 310 // A14 low -- set least significant bits
philpem@59 311 state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
philpem@59 312 }
philpem@59 313 handled = true;
philpem@59 314 break;
philpem@59 315 case 0x0E0000: // Disk Control Register
philpem@66 316 ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
philpem@59 317 // B7 = FDD controller reset
philpem@59 318 if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
philpem@59 319 // B6 = drive 0 select -- TODO
philpem@59 320 // B5 = motor enable -- TODO
philpem@59 321 // B4 = HDD controller reset -- TODO
philpem@59 322 // B3 = HDD0 select -- TODO
philpem@59 323 // B2,1,0 = HDD0 head select
philpem@59 324 handled = true;
philpem@59 325 break;
philpem@59 326 case 0x0F0000: // Line Printer Data Register
philpem@59 327 break;
philpem@59 328 }
philpem@59 329 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@59 330 // I/O register space, zone B
philpem@59 331 switch (address & 0xF00000) {
philpem@59 332 case 0xC00000: // Expansion slots
philpem@59 333 case 0xD00000:
philpem@59 334 switch (address & 0xFC0000) {
philpem@59 335 case 0xC00000: // Expansion slot 0
philpem@59 336 case 0xC40000: // Expansion slot 1
philpem@59 337 case 0xC80000: // Expansion slot 2
philpem@59 338 case 0xCC0000: // Expansion slot 3
philpem@59 339 case 0xD00000: // Expansion slot 4
philpem@59 340 case 0xD40000: // Expansion slot 5
philpem@59 341 case 0xD80000: // Expansion slot 6
philpem@59 342 case 0xDC0000: // Expansion slot 7
philpem@59 343 fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
philpem@59 344 handled = true;
philpem@59 345 break;
philpem@59 346 }
philpem@59 347 break;
philpem@59 348 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@59 349 case 0xF00000:
philpem@59 350 switch (address & 0x070000) {
philpem@59 351 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@59 352 break;
philpem@59 353 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@66 354 ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");
philpem@59 355 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
philpem@59 356 handled = true;
philpem@59 357 break;
philpem@59 358 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@59 359 break;
philpem@59 360 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@59 361 break;
philpem@59 362 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@59 363 switch (address & 0x077000) {
philpem@59 364 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@59 365 break;
philpem@59 366 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@66 367 ENFORCE_SIZE_W(bits, address, 16, "PIE");
philpem@59 368 state.pie = ((data & 0x8000) == 0x8000);
philpem@59 369 handled = true;
philpem@59 370 break;
philpem@59 371 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@59 372 break;
philpem@59 373 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@66 374 ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
philpem@59 375 state.romlmap = ((data & 0x8000) == 0x8000);
philpem@59 376 handled = true;
philpem@59 377 break;
philpem@59 378 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@66 379 ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
philpem@59 380 break;
philpem@59 381 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@66 382 ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
philpem@59 383 break;
philpem@59 384 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@66 385 ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
philpem@59 386 break;
philpem@59 387 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@66 388 ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
philpem@59 389 break;
philpem@59 390 }
philpem@59 391 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@59 392 break;
philpem@59 393 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@59 394 switch (address & 0x07F000) {
philpem@59 395 default:
philpem@59 396 break;
philpem@59 397 }
philpem@59 398 break;
philpem@59 399 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@59 400 break;
philpem@59 401 }
philpem@59 402 }
philpem@59 403 }
philpem@64 404
philpem@64 405 LOG_NOT_HANDLED_W(bits);
philpem@59 406 }/*}}}*/
philpem@59 407
philpem@59 408 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
philpem@59 409 {
philpem@59 410 bool handled = false;
philpem@59 411 uint32_t data = 0xFFFFFFFF;
philpem@59 412
philpem@59 413 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@59 414 // I/O register space, zone A
philpem@59 415 switch (address & 0x0F0000) {
philpem@59 416 case 0x010000: // General Status Register
philpem@66 417 ENFORCE_SIZE_R(bits, address, 16, "GENSTAT");
philpem@59 418 return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
philpem@59 419 break;
philpem@59 420 case 0x030000: // Bus Status Register 0
philpem@66 421 ENFORCE_SIZE_R(bits, address, 16, "BSR0");
philpem@59 422 return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
philpem@59 423 break;
philpem@59 424 case 0x040000: // Bus Status Register 1
philpem@66 425 ENFORCE_SIZE_R(bits, address, 16, "BSR1");
philpem@59 426 return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
philpem@59 427 break;
philpem@59 428 case 0x050000: // Phone status
philpem@66 429 ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
philpem@59 430 break;
philpem@59 431 case 0x060000: // DMA Count
philpem@55 432 // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
philpem@55 433 // Bit 14 is always unused, so leave it set
philpem@66 434 ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
philpem@59 435 return (state.dma_count & 0x3fff) | 0xC000;
philpem@40 436 break;
philpem@40 437 case 0x070000: // Line Printer Status Register
philpem@53 438 data = 0x00120012; // no parity error, no line printer error, no irqs from FDD or HDD
philpem@53 439 data |= (state.fdc_ctx.irql) ? 0x00080008 : 0; // FIXME! HACKHACKHACK! shouldn't peek inside FDC structs like this
philpem@59 440 return data;
philpem@40 441 break;
philpem@40 442 case 0x080000: // Real Time Clock
philpem@59 443 printf("READ NOTIMP: Realtime Clock\n");
philpem@40 444 break;
philpem@40 445 case 0x090000: // Phone registers
philpem@40 446 switch (address & 0x0FF000) {
philpem@40 447 case 0x090000: // Handset relay
philpem@40 448 case 0x098000:
philpem@40 449 break;
philpem@40 450 case 0x091000: // Line select 2
philpem@40 451 case 0x099000:
philpem@40 452 break;
philpem@40 453 case 0x092000: // Hook relay 1
philpem@40 454 case 0x09A000:
philpem@40 455 break;
philpem@40 456 case 0x093000: // Hook relay 2
philpem@40 457 case 0x09B000:
philpem@40 458 break;
philpem@40 459 case 0x094000: // Line 1 hold
philpem@40 460 case 0x09C000:
philpem@40 461 break;
philpem@40 462 case 0x095000: // Line 2 hold
philpem@40 463 case 0x09D000:
philpem@40 464 break;
philpem@40 465 case 0x096000: // Line 1 A-lead
philpem@40 466 case 0x09E000:
philpem@40 467 break;
philpem@40 468 case 0x097000: // Line 2 A-lead
philpem@40 469 case 0x09F000:
philpem@40 470 break;
philpem@40 471 }
philpem@40 472 break;
philpem@46 473 case 0x0A0000: // Miscellaneous Control Register -- write only!
philpem@46 474 handled = true;
philpem@40 475 break;
philpem@40 476 case 0x0B0000: // TM/DIALWR
philpem@40 477 break;
philpem@46 478 case 0x0C0000: // Clear Status Register -- write only!
philpem@43 479 handled = true;
philpem@40 480 break;
philpem@40 481 case 0x0D0000: // DMA Address Register
philpem@40 482 break;
philpem@40 483 case 0x0E0000: // Disk Control Register
philpem@40 484 break;
philpem@40 485 case 0x0F0000: // Line Printer Data Register
philpem@40 486 break;
philpem@40 487 }
philpem@40 488 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 489 // I/O register space, zone B
philpem@40 490 switch (address & 0xF00000) {
philpem@40 491 case 0xC00000: // Expansion slots
philpem@40 492 case 0xD00000:
philpem@40 493 switch (address & 0xFC0000) {
philpem@40 494 case 0xC00000: // Expansion slot 0
philpem@40 495 case 0xC40000: // Expansion slot 1
philpem@40 496 case 0xC80000: // Expansion slot 2
philpem@40 497 case 0xCC0000: // Expansion slot 3
philpem@40 498 case 0xD00000: // Expansion slot 4
philpem@40 499 case 0xD40000: // Expansion slot 5
philpem@40 500 case 0xD80000: // Expansion slot 6
philpem@40 501 case 0xDC0000: // Expansion slot 7
philpem@65 502 fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
philpem@65 503 handled = true;
philpem@40 504 break;
philpem@40 505 }
philpem@40 506 break;
philpem@40 507 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 508 case 0xF00000:
philpem@40 509 switch (address & 0x070000) {
philpem@40 510 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@40 511 break;
philpem@40 512 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@66 513 ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");
philpem@59 514 return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
philpem@40 515 break;
philpem@40 516 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 517 break;
philpem@40 518 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 519 break;
philpem@40 520 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 521 switch (address & 0x077000) {
philpem@40 522 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@44 523 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@40 524 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 525 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@44 526 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@44 527 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@44 528 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@44 529 // All write-only registers... TODO: bus error?
philpem@44 530 handled = true;
philpem@40 531 break;
philpem@44 532 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
philpem@40 533 break;
philpem@40 534 }
philpem@40 535 break;
philpem@40 536 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 537 break;
philpem@40 538 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 539 switch (address & 0x07F000) {
philpem@40 540 default:
philpem@40 541 break;
philpem@40 542 }
philpem@40 543 break;
philpem@40 544 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@40 545 break;
philpem@40 546 }
philpem@40 547 }
philpem@40 548 }
philpem@64 549
philpem@64 550 LOG_NOT_HANDLED_R(bits);
philpem@64 551
philpem@59 552 return data;
philpem@59 553 }/*}}}*/
philpem@40 554
philpem@59 555
philpem@59 556 /********************************************************
philpem@59 557 * m68k memory read/write support functions for Musashi
philpem@59 558 ********************************************************/
philpem@59 559
philpem@59 560 /**
philpem@59 561 * @brief Read M68K memory, 32-bit
philpem@59 562 */
philpem@59 563 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
philpem@59 564 {
philpem@59 565 uint32_t data = 0xFFFFFFFF;
philpem@59 566
philpem@59 567 // If ROMLMAP is set, force system to access ROM
philpem@59 568 if (!state.romlmap)
philpem@59 569 address |= 0x800000;
philpem@59 570
philpem@59 571 // Check access permissions
philpem@59 572 ACCESS_CHECK_RD(address, 32);
philpem@59 573
philpem@59 574 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@59 575 // ROM access
philpem@60 576 return RD32(state.rom, address, ROM_SIZE - 1);
philpem@60 577 } else if (address <= 0x3fffff) {
philpem@59 578 // RAM access
philpem@60 579 uint32_t newAddr = mapAddr(address, false);
philpem@63 580 if (newAddr <= 0x1fffff) {
philpem@60 581 return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 582 } else {
philpem@63 583 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
philpem@63 584 return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 585 else
philpem@63 586 return 0xffffffff;
philpem@63 587 }
philpem@59 588 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@59 589 // I/O register space, zone A
philpem@59 590 switch (address & 0x0F0000) {
philpem@59 591 case 0x000000: // Map RAM access
philpem@59 592 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
philpem@60 593 return RD32(state.map, address, 0x7FF);
philpem@59 594 break;
philpem@59 595 case 0x020000: // Video RAM
philpem@59 596 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@60 597 return RD32(state.vram, address, 0x7FFF);
philpem@59 598 break;
philpem@59 599 default:
philpem@60 600 return IoRead(address, 32);
philpem@59 601 }
philpem@59 602 } else {
philpem@60 603 return IoRead(address, 32);
philpem@59 604 }
philpem@59 605
philpem@40 606 return data;
philpem@59 607 }/*}}}*/
philpem@40 608
philpem@40 609 /**
philpem@40 610 * @brief Read M68K memory, 16-bit
philpem@40 611 */
philpem@59 612 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
philpem@40 613 {
philpem@40 614 uint16_t data = 0xFFFF;
philpem@40 615
philpem@40 616 // If ROMLMAP is set, force system to access ROM
philpem@40 617 if (!state.romlmap)
philpem@40 618 address |= 0x800000;
philpem@40 619
philpem@40 620 // Check access permissions
philpem@40 621 ACCESS_CHECK_RD(address, 16);
philpem@40 622
philpem@40 623 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 624 // ROM access
philpem@40 625 data = RD16(state.rom, address, ROM_SIZE - 1);
philpem@60 626 } else if (address <= 0x3fffff) {
philpem@40 627 // RAM access
philpem@60 628 uint32_t newAddr = mapAddr(address, false);
philpem@63 629 if (newAddr <= 0x1fffff) {
philpem@60 630 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 631 } else {
philpem@63 632 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
philpem@63 633 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 634 else
philpem@63 635 return 0xffff;
philpem@63 636 }
philpem@40 637 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 638 // I/O register space, zone A
philpem@40 639 switch (address & 0x0F0000) {
philpem@40 640 case 0x000000: // Map RAM access
philpem@40 641 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 642 data = RD16(state.map, address, 0x7FF);
philpem@40 643 break;
philpem@40 644 case 0x020000: // Video RAM
philpem@40 645 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 646 data = RD16(state.vram, address, 0x7FFF);
philpem@40 647 break;
philpem@59 648 default:
philpem@59 649 data = IoRead(address, 16);
philpem@40 650 }
philpem@59 651 } else {
philpem@59 652 data = IoRead(address, 16);
philpem@40 653 }
philpem@40 654
philpem@40 655 return data;
philpem@59 656 }/*}}}*/
philpem@40 657
philpem@40 658 /**
philpem@40 659 * @brief Read M68K memory, 8-bit
philpem@40 660 */
philpem@59 661 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
philpem@40 662 {
philpem@40 663 uint8_t data = 0xFF;
philpem@40 664
philpem@40 665 // If ROMLMAP is set, force system to access ROM
philpem@40 666 if (!state.romlmap)
philpem@40 667 address |= 0x800000;
philpem@40 668
philpem@40 669 // Check access permissions
philpem@40 670 ACCESS_CHECK_RD(address, 8);
philpem@40 671
philpem@40 672 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 673 // ROM access
philpem@40 674 data = RD8(state.rom, address, ROM_SIZE - 1);
philpem@60 675 } else if (address <= 0x3fffff) {
philpem@40 676 // RAM access
philpem@60 677 uint32_t newAddr = mapAddr(address, false);
philpem@63 678 if (newAddr <= 0x1fffff) {
philpem@60 679 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 680 } else {
philpem@63 681 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
philpem@63 682 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 683 else
philpem@63 684 return 0xff;
philpem@63 685 }
philpem@40 686 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 687 // I/O register space, zone A
philpem@40 688 switch (address & 0x0F0000) {
philpem@40 689 case 0x000000: // Map RAM access
philpem@40 690 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 691 data = RD8(state.map, address, 0x7FF);
philpem@40 692 break;
philpem@40 693 case 0x020000: // Video RAM
philpem@40 694 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 695 data = RD8(state.vram, address, 0x7FFF);
philpem@40 696 break;
philpem@59 697 default:
philpem@59 698 data = IoRead(address, 8);
philpem@40 699 }
philpem@59 700 } else {
philpem@59 701 data = IoRead(address, 8);
philpem@40 702 }
philpem@40 703
philpem@40 704 return data;
philpem@59 705 }/*}}}*/
philpem@40 706
philpem@40 707 /**
philpem@40 708 * @brief Write M68K memory, 32-bit
philpem@40 709 */
philpem@59 710 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
philpem@40 711 {
philpem@40 712 // If ROMLMAP is set, force system to access ROM
philpem@40 713 if (!state.romlmap)
philpem@40 714 address |= 0x800000;
philpem@40 715
philpem@40 716 // Check access permissions
philpem@40 717 ACCESS_CHECK_WR(address, 32);
philpem@40 718
philpem@40 719 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 720 // ROM access
philpem@60 721 } else if (address <= 0x3FFFFF) {
philpem@40 722 // RAM access
philpem@60 723 uint32_t newAddr = mapAddr(address, true);
philpem@63 724 if (newAddr <= 0x1fffff) {
philpem@60 725 WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@63 726 } else {
philpem@65 727 WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@63 728 }
philpem@40 729 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 730 // I/O register space, zone A
philpem@40 731 switch (address & 0x0F0000) {
philpem@40 732 case 0x000000: // Map RAM access
philpem@59 733 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 734 WR32(state.map, address, 0x7FF, value);
philpem@40 735 break;
philpem@40 736 case 0x020000: // Video RAM
philpem@59 737 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 738 WR32(state.vram, address, 0x7FFF, value);
philpem@40 739 break;
philpem@59 740 default:
philpem@59 741 IoWrite(address, value, 32);
philpem@40 742 }
philpem@59 743 } else {
philpem@59 744 IoWrite(address, value, 32);
philpem@40 745 }
philpem@59 746 }/*}}}*/
philpem@40 747
philpem@40 748 /**
philpem@40 749 * @brief Write M68K memory, 16-bit
philpem@40 750 */
philpem@59 751 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
philpem@40 752 {
philpem@40 753 // If ROMLMAP is set, force system to access ROM
philpem@40 754 if (!state.romlmap)
philpem@40 755 address |= 0x800000;
philpem@40 756
philpem@40 757 // Check access permissions
philpem@40 758 ACCESS_CHECK_WR(address, 16);
philpem@40 759
philpem@40 760 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 761 // ROM access
philpem@60 762 } else if (address <= 0x3FFFFF) {
philpem@40 763 // RAM access
philpem@60 764 uint32_t newAddr = mapAddr(address, true);
philpem@63 765 if (newAddr <= 0x1fffff) {
philpem@60 766 WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@63 767 } else {
philpem@65 768 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@63 769 }
philpem@40 770 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 771 // I/O register space, zone A
philpem@40 772 switch (address & 0x0F0000) {
philpem@40 773 case 0x000000: // Map RAM access
philpem@40 774 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 775 WR16(state.map, address, 0x7FF, value);
philpem@40 776 break;
philpem@40 777 case 0x020000: // Video RAM
philpem@40 778 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 779 WR16(state.vram, address, 0x7FFF, value);
philpem@40 780 break;
philpem@59 781 default:
philpem@59 782 IoWrite(address, value, 16);
philpem@40 783 }
philpem@59 784 } else {
philpem@59 785 IoWrite(address, value, 16);
philpem@40 786 }
philpem@59 787 }/*}}}*/
philpem@40 788
philpem@40 789 /**
philpem@40 790 * @brief Write M68K memory, 8-bit
philpem@40 791 */
philpem@59 792 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
philpem@40 793 {
philpem@40 794 // If ROMLMAP is set, force system to access ROM
philpem@40 795 if (!state.romlmap)
philpem@40 796 address |= 0x800000;
philpem@40 797
philpem@40 798 // Check access permissions
philpem@40 799 ACCESS_CHECK_WR(address, 8);
philpem@40 800
philpem@40 801 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 802 // ROM access (read only!)
philpem@60 803 } else if (address <= 0x3FFFFF) {
philpem@40 804 // RAM access
philpem@60 805 uint32_t newAddr = mapAddr(address, true);
philpem@63 806 if (newAddr <= 0x1fffff) {
philpem@60 807 WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@63 808 } else {
philpem@65 809 WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@63 810 }
philpem@40 811 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 812 // I/O register space, zone A
philpem@40 813 switch (address & 0x0F0000) {
philpem@40 814 case 0x000000: // Map RAM access
philpem@59 815 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 816 WR8(state.map, address, 0x7FF, value);
philpem@40 817 break;
philpem@40 818 case 0x020000: // Video RAM
philpem@59 819 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 820 WR8(state.vram, address, 0x7FFF, value);
philpem@40 821 break;
philpem@59 822 default:
philpem@59 823 IoWrite(address, value, 8);
philpem@40 824 }
philpem@59 825 } else {
philpem@59 826 IoWrite(address, value, 8);
philpem@40 827 }
philpem@59 828 }/*}}}*/
philpem@40 829
philpem@40 830
philpem@40 831 // for the disassembler
philpem@40 832 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
philpem@40 833 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
philpem@40 834 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }
philpem@40 835