src/memory.c

Fri, 12 Apr 2013 12:36:28 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Fri, 12 Apr 2013 12:36:28 +0100
branch
experimental_memory_mapper_v2
changeset 141
8460d432606f
parent 140
1e4c45b144c4
child 144
609707511166
permissions
-rw-r--r--

Make mapper debug logic more verbose (but disable by default)

philpem@40 1 #include <stdio.h>
philpem@40 2 #include <stdlib.h>
philpem@40 3 #include <stdint.h>
philpem@40 4 #include <stdbool.h>
philpem@59 5 #include <assert.h>
philpem@40 6 #include "musashi/m68k.h"
philpem@40 7 #include "state.h"
philpem@100 8 #include "utils.h"
philpem@40 9 #include "memory.h"
philpem@40 10
philpem@119 11 // The value which will be returned if the CPU attempts to read from empty memory
philpem@119 12 // TODO (FIXME?) - need to figure out if R/W ops wrap around. This seems to appease the UNIX kernel and P4TEST.
philpem@119 13 #define EMPTY 0xFFFFFFFFUL
philpem@129 14 //#define EMPTY 0x55555555UL
philpem@129 15 //#define EMPTY 0x00000000UL
philpem@119 16
philpem@40 17 /******************
philpem@40 18 * Memory mapping
philpem@40 19 ******************/
philpem@40 20
philpem@128 21 /// Set a page bit
philpem@133 22 #define MAP_SET_PAGEBIT(addr, bit) state.map[(MAP_ADDR_TO_PAGE(addr))*2] |= ((uint8_t)bit << 2)
philpem@128 23 /// Clear a page bit
philpem@133 24 #define MAP_CLR_PAGEBIT(addr, bit) state.map[(MAP_ADDR_TO_PAGE(addr))*2] &= ~((uint8_t)bit << 2)
philpem@40 25
philpem@40 26
philpem@40 27 /********************************************************
philpem@40 28 * m68k memory read/write support functions for Musashi
philpem@40 29 ********************************************************/
philpem@40 30
philpem@40 31 /**
philpem@40 32 * @brief Check memory access permissions for a write operation.
philpem@40 33 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
philpem@40 34 * gcc throws warnings when you have a return-with-value in a void
philpem@40 35 * function, even if the return-with-value is completely unreachable.
philpem@40 36 * Similarly it doesn't like it if you have a return without a value
philpem@40 37 * in a non-void function, even if it's impossible to ever reach the
philpem@40 38 * return-with-no-value. UGH!
philpem@40 39 */
philpem@59 40 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
philpem@59 41 #define ACCESS_CHECK_WR(address, bits) \
philpem@59 42 do { \
philpem@128 43 if (access_check_cpu(address, bits, true)) { \
philpem@40 44 return; \
philpem@40 45 } \
philpem@70 46 } while (0)
philpem@59 47 /*}}}*/
philpem@40 48
philpem@40 49 /**
philpem@40 50 * @brief Check memory access permissions for a read operation.
philpem@40 51 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
philpem@40 52 * gcc throws warnings when you have a return-with-value in a void
philpem@40 53 * function, even if the return-with-value is completely unreachable.
philpem@40 54 * Similarly it doesn't like it if you have a return without a value
philpem@40 55 * in a non-void function, even if it's impossible to ever reach the
philpem@40 56 * return-with-no-value. UGH!
philpem@40 57 */
philpem@59 58 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
philpem@59 59 #define ACCESS_CHECK_RD(address, bits) \
philpem@59 60 do { \
philpem@128 61 if (access_check_cpu(address, bits, false)) { \
philpem@128 62 if (bits == 32) \
philpem@128 63 return EMPTY & 0xFFFFFFFF; \
philpem@40 64 else \
philpem@128 65 return EMPTY & ((1UL << bits)-1); \
philpem@40 66 } \
philpem@70 67 } while (0)
philpem@59 68 /*}}}*/
philpem@40 69
philpem@128 70
philpem@128 71 /**
philpem@128 72 * Update the page bits for a given memory address
philpem@128 73 *
philpem@128 74 * @param addr Memory address being accessed
philpem@128 75 * @param l7intr Set to <i>true</i> if a level-seven interrupt has been
philpem@128 76 * signalled (even if <b>ENABLE ERROR</b> isn't set).
philpem@128 77 * @param write Set to <i>true</i> if the address is being written to.
philpem@128 78 */
philpem@128 79 static void update_page_bits(uint32_t addr, bool l7intr, bool write)
philpem@112 80 {
philpem@128 81 bool ps0_state = false;
philpem@128 82
philpem@128 83 // Don't try and update pagebits for non-RAM addresses
philpem@128 84 if (addr > 0x3FFFFF)
philpem@128 85 return;
philpem@128 86
philpem@128 87 if (l7intr) {
philpem@128 88 // if (!(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
philpem@128 89 // FIXME FUCKUP The ruddy TRM is wrong AGAIN! If above line is uncommented, Really Bad Things Happen.
philpem@128 90 if ((MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
philpem@128 91 // Level 7 interrupt, PS0 clear, PS1 don't-care. Set PS0.
philpem@128 92 ps0_state = true;
philpem@128 93 }
philpem@128 94 } else {
philpem@128 95 // No L7 interrupt
philpem@128 96 if ((write && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && (MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) ||
philpem@140 97 (write && (MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) ||
philpem@140 98 ( (MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && (MAP_PAGEBITS(addr) & PAGE_BIT_PS0))) /* NOTE -- Once again, this case was missing from the PAL equations in the TRM... */
philpem@128 99 {
philpem@128 100 // No L7 interrupt, PS[1:0] = 0b01, write
philpem@128 101 // No L7 interrupt, PS[1:0] = 0b10, write
philpem@128 102 ps0_state = true;
philpem@128 103 }
philpem@128 104 }
philpem@112 105
philpem@128 106 #ifdef MAPRAM_BIT_TEST
philpem@128 107 LOG("Starting Mapram Bit Test");
philpem@128 108 state.map[0] = state.map[1] = 0;
philpem@128 109 LOG("Start = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 110 MAP_SET_PAGEBIT(0, PAGE_BIT_WE);
philpem@128 111 LOG("Set WE = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 112 MAP_SET_PAGEBIT(0, PAGE_BIT_PS1);
philpem@128 113 LOG("Set PS1 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 114 MAP_SET_PAGEBIT(0, PAGE_BIT_PS0);
philpem@128 115 LOG("Set PS0 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 116
philpem@128 117 MAP_CLR_PAGEBIT(0, PAGE_BIT_WE);
philpem@128 118 LOG("Clr WE = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 119 MAP_CLR_PAGEBIT(0, PAGE_BIT_PS1);
philpem@128 120 LOG("Clr PS1 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 121 MAP_CLR_PAGEBIT(0, PAGE_BIT_PS0);
philpem@128 122 LOG("Clr PS0 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 123 exit(-1);
philpem@128 124 #endif
philpem@128 125
philpem@141 126 #ifdef MAPRAM_DEBUG_MESSAGES
philpem@128 127 uint16_t old_pagebits = MAP_PAGEBITS(addr);
philpem@141 128 #endif
philpem@112 129
philpem@128 130 // PS1 is always set on access
philpem@128 131 MAP_SET_PAGEBIT(addr, PAGE_BIT_PS1);
philpem@128 132
philpem@141 133 #ifdef MAPRAM_DEBUG_MESSAGES
philpem@128 134 uint16_t new_pagebit1 = MAP_PAGEBITS(addr);
philpem@141 135 #endif
philpem@128 136
philpem@128 137 // Update PS0
philpem@128 138 if (ps0_state) {
philpem@128 139 MAP_SET_PAGEBIT(addr, PAGE_BIT_PS0);
philpem@128 140 } else {
philpem@128 141 MAP_CLR_PAGEBIT(addr, PAGE_BIT_PS0);
philpem@128 142 }
philpem@112 143
philpem@141 144 #ifdef MAPRAM_DEBUG_MESSAGES
philpem@128 145 uint16_t new_pagebit2 = MAP_PAGEBITS(addr);
philpem@128 146 switch (addr) {
philpem@128 147 case 0x000000:
philpem@128 148 case 0x001000:
philpem@128 149 case 0x002000:
philpem@128 150 case 0x003000:
philpem@128 151 case 0x004000:
philpem@128 152 case 0x033000:
philpem@128 153 case 0x034000:
philpem@128 154 case 0x035000:
philpem@141 155 LOG("Addr %08X %s MapNew %04X Page %04X -- Pagebit update -- ps0 %d, old %s%s => %s%s => %s%s",
philpem@141 156 addr,
philpem@141 157 write ? "Wr" : "Rd",
philpem@141 158 MAPRAM_ADDR(addr),
philpem@141 159 MAP_ADDR_TO_PAGE(addr),
philpem@141 160 ps0_state,
philpem@141 161 old_pagebits & PAGE_BIT_PS0 ? "PS0" : "",
philpem@141 162 old_pagebits & PAGE_BIT_PS1 ? "PS1" : "",
philpem@141 163 new_pagebit1 & PAGE_BIT_PS0 ? "PS0" : "",
philpem@141 164 new_pagebit1 & PAGE_BIT_PS1 ? "PS1" : "",
philpem@141 165 new_pagebit2 & PAGE_BIT_PS0 ? "PS0" : "",
philpem@141 166 new_pagebit2 & PAGE_BIT_PS1 ? "PS1" : ""
philpem@141 167 );
philpem@128 168 default:
philpem@112 169 break;
philpem@112 170 }
philpem@141 171 #endif // MAPRAM_DEBUG_MESSAGES
philpem@128 172 }
philpem@128 173
philpem@128 174 bool access_check_dma(void)
philpem@128 175 {
philpem@128 176 // TODO FIXME BUGBUG Sanity check - Make sure DMAC is only accessing RAM addresses
philpem@128 177
philpem@128 178 // DMA access check -- make sure the page is mapped in
philpem@128 179 if (!(MAP_PAGEBITS(state.dma_address) & PAGE_BIT_PS0) && !(MAP_PAGEBITS(state.dma_address) & PAGE_BIT_PS1)) {
philpem@128 180 // DMA access to page which is not mapped in.
philpem@128 181 // Level 7 interrupt, page fault, DMA invoked
philpem@128 182 state.genstat = 0xABFF
philpem@128 183 | (state.dma_reading ? 0x4000 : 0)
philpem@128 184 | (state.pie ? 0x0400 : 0);
philpem@128 185
philpem@128 186 // XXX: Check all this stuff.
philpem@112 187 state.bsr0 = 0x3C00;
philpem@112 188 state.bsr0 |= (state.dma_address >> 16);
philpem@112 189 state.bsr1 = state.dma_address & 0xffff;
philpem@128 190
philpem@128 191 // Update page bits for this transfer
philpem@128 192 update_page_bits(state.dma_address, true, !state.dma_reading);
philpem@128 193
philpem@128 194 // XXX: is this right?
philpem@128 195 // Fire a Level 7 interrupt
philpem@128 196 /*if (state.ee)*/ m68k_set_irq(7);
philpem@128 197
philpem@128 198 LOG("BUS ERROR FROM DMA: genstat=%04X, bsr0=%04X, bsr1=%04X\n", state.genstat, state.bsr0, state.bsr1);
philpem@128 199 return false;
philpem@128 200 } else {
philpem@128 201 // No errors. Just update the page bits.
philpem@128 202 update_page_bits(state.dma_address, false, !state.dma_reading);
philpem@128 203 return true;
philpem@112 204 }
philpem@128 205 }
philpem@128 206
philpem@128 207 /**
philpem@128 208 * Check memory access permissions for a CPU memory access.
philpem@128 209 *
philpem@128 210 * @param addr Virtual memory address being accessed (from CPU address bus).
philpem@128 211 * @param bits Word size of this transfer (8, 16 or 32 bits).
philpem@128 212 * @param write <i>true</i> if this is a write operation, <i>false</i> if it is a read operation.
philpem@128 213 * @return <i>true</i> if the access was denied and a level-7 interrupt and/or bus error raised.
philpem@128 214 * <i>false</i> if the access was allowed.
philpem@128 215 */
philpem@128 216 bool access_check_cpu(uint32_t addr, int bits, bool write)
philpem@128 217 {
philpem@128 218 bool supervisor = (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000);
philpem@128 219 bool fault = false;
philpem@128 220
philpem@128 221 // TODO FIXME BUGBUG? Do we need to check for supervisor access here?
philpem@128 222 if ((addr >= 0x000000) && (addr <= 0x3FFFFF) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
philpem@128 223 // (A) Page Fault -- user access to page which is not mapped in
philpem@128 224 // Level 7 Interrupt, Bus Error, regs=PAGEFAULT
philpem@128 225 if (write) {
philpem@128 226 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0);
philpem@128 227 } else {
philpem@128 228 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0);
philpem@128 229 }
philpem@128 230 fault = true;
philpem@128 231 } else if (!supervisor && (addr >= 0x000000) && (addr <= 0x07FFFF)) {
philpem@128 232 // (B) User attempted to access the kernel
philpem@128 233 // Level 7 Interrupt, Bus Error, regs=KERNEL
philpem@128 234 if (write) {
philpem@128 235 // XXX: BUGBUG? Is this correct?
philpem@128 236 state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0);
philpem@128 237 } else {
philpem@128 238 state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0);
philpem@128 239 }
philpem@128 240 fault = true;
philpem@128 241 } else if (!supervisor && write && (addr >= 0x000000) && (addr <= 0x3FFFFF) && !(MAP_PAGEBITS(addr) & PAGE_BIT_WE)) {
philpem@128 242 // (C) User attempted to write to a page which is not write enabled
philpem@128 243 // Level 7 Interrupt, Bus Error, regs=WRITE_EN
philpem@128 244 if (write) {
philpem@128 245 // XXX: BUGBUG? Is this correct?
philpem@128 246 state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0);
philpem@128 247 } else {
philpem@128 248 state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0);
philpem@128 249 }
philpem@128 250 fault = true;
philpem@128 251 } else if (!supervisor && (addr >= 0x400000) && (addr <= 0xFFFFFF)) {
philpem@128 252 // (D) UIE - user I/O exception
philpem@128 253 // Bus Error only, regs=UIE
philpem@128 254 if (write) {
philpem@128 255 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0);
philpem@128 256 } else {
philpem@128 257 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0);
philpem@128 258 }
philpem@128 259 fault = true;
philpem@128 260 }
philpem@128 261
philpem@128 262 // Update the page bits first
philpem@128 263 update_page_bits(addr, fault, write);
philpem@128 264
philpem@128 265 if (fault) {
philpem@128 266 if (bits >= 16)
philpem@128 267 state.bsr0 = 0x7C00;
philpem@128 268 else
philpem@128 269 state.bsr0 = (addr & 1) ? 0x7E00 : 0x7D00;
philpem@128 270 // FIXME? Physical or virtual address here?
philpem@128 271 state.bsr0 |= (addr >> 16);
philpem@128 272 state.bsr1 = addr & 0xffff;
philpem@128 273
philpem@128 274 LOG("CPU Bus Error or L7Intr while %s, vaddr %08X, map %08X, pagebits 0x%02X bsr0=%04X bsr1=%04X genstat=%04X",
philpem@128 275 write ? "writing" : "reading", addr,
philpem@128 276 MAPRAM_ADDR(addr & 0x3fffff),
philpem@128 277 MAP_PAGEBITS(addr & 0x3fffff),
philpem@128 278 state.bsr0, state.bsr1, state.genstat);
philpem@128 279
philpem@128 280 // FIXME? BUGBUG? Does EE disable one or both of these?
philpem@128 281 // /*if (state.ee)*/ m68k_set_irq(7);
philpem@128 282 /*if (state.ee)*/ m68k_pulse_bus_error();
philpem@128 283 }
philpem@128 284
philpem@128 285 return fault;
philpem@112 286 }
philpem@112 287
philpem@40 288 // Logging macros
philpem@59 289 #define LOG_NOT_HANDLED_R(bits) \
philpem@128 290 if (!handled) fprintf(stderr, "unhandled read%02d, addr=0x%08X\n", bits, address);
philpem@40 291
philpem@59 292 #define LOG_NOT_HANDLED_W(bits) \
philpem@128 293 if (!handled) fprintf(stderr, "unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
philpem@59 294
philpem@59 295 /********************************************************
philpem@59 296 * I/O read/write functions
philpem@59 297 ********************************************************/
philpem@40 298
philpem@40 299 /**
philpem@59 300 * Issue a warning if a read operation is made with an invalid size
philpem@40 301 */
philpem@66 302 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
philpem@40 303 {
philpem@59 304 assert((bits == 8) || (bits == 16) || (bits == 32));
philpem@59 305 if ((bits & allowed) == 0) {
philpem@128 306 LOG("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
philpem@59 307 }
philpem@59 308 }
philpem@59 309
philpem@66 310 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
philpem@40 311 {
philpem@66 312 ENFORCE_SIZE(bits, address, true, allowed, regname);
philpem@66 313 }
philpem@66 314
philpem@66 315 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
philpem@66 316 {
philpem@66 317 ENFORCE_SIZE(bits, address, false, allowed, regname);
philpem@66 318 }
philpem@66 319
philpem@59 320 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
philpem@59 321 {
philpem@40 322 bool handled = false;
philpem@40 323
philpem@59 324 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 325 // I/O register space, zone A
philpem@40 326 switch (address & 0x0F0000) {
philpem@40 327 case 0x010000: // General Status Register
philpem@59 328 if (bits == 16)
philpem@59 329 state.genstat = (data & 0xffff);
philpem@59 330 else if (bits == 8) {
philpem@59 331 if (address & 0)
philpem@59 332 state.genstat = data;
philpem@59 333 else
philpem@59 334 state.genstat = data << 8;
philpem@59 335 }
philpem@40 336 handled = true;
philpem@40 337 break;
philpem@40 338 case 0x030000: // Bus Status Register 0
philpem@40 339 break;
philpem@40 340 case 0x040000: // Bus Status Register 1
philpem@40 341 break;
philpem@40 342 case 0x050000: // Phone status
philpem@40 343 break;
philpem@40 344 case 0x060000: // DMA Count
philpem@66 345 ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
philpem@59 346 state.dma_count = (data & 0x3FFF);
philpem@59 347 state.idmarw = ((data & 0x4000) == 0x4000);
philpem@59 348 state.dmaen = ((data & 0x8000) == 0x8000);
philpem@59 349 // This handles the "dummy DMA transfer" mentioned in the docs
philpem@112 350 // disabled because it causes the floppy test to fail
philpem@112 351 #if 0
philpem@112 352 if (!state.idmarw){
philpem@112 353 if (access_check_dma(true)){
philpem@112 354 uint32_t newAddr = mapAddr(state.dma_address, true);
philpem@112 355 // RAM access
philpem@112 356 if (newAddr <= 0x1fffff)
philpem@112 357 WR16(state.base_ram, newAddr, state.base_ram_size - 1, 0xFF);
philpem@112 358 else if (address <= 0x3FFFFF)
philpem@112 359 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, 0xFF);
philpem@112 360 }
philpem@112 361 }
philpem@112 362 #endif
philpem@59 363 state.dma_count++;
philpem@53 364 handled = true;
philpem@40 365 break;
philpem@40 366 case 0x070000: // Line Printer Status Register
philpem@40 367 break;
philpem@40 368 case 0x080000: // Real Time Clock
philpem@128 369 LOGS("REAL TIME CLOCK WRITE");
philpem@40 370 break;
philpem@40 371 case 0x090000: // Phone registers
philpem@40 372 switch (address & 0x0FF000) {
philpem@40 373 case 0x090000: // Handset relay
philpem@40 374 case 0x098000:
philpem@40 375 break;
philpem@40 376 case 0x091000: // Line select 2
philpem@40 377 case 0x099000:
philpem@40 378 break;
philpem@40 379 case 0x092000: // Hook relay 1
philpem@40 380 case 0x09A000:
philpem@40 381 break;
philpem@40 382 case 0x093000: // Hook relay 2
philpem@40 383 case 0x09B000:
philpem@40 384 break;
philpem@40 385 case 0x094000: // Line 1 hold
philpem@40 386 case 0x09C000:
philpem@40 387 break;
philpem@40 388 case 0x095000: // Line 2 hold
philpem@40 389 case 0x09D000:
philpem@40 390 break;
philpem@40 391 case 0x096000: // Line 1 A-lead
philpem@40 392 case 0x09E000:
philpem@40 393 break;
philpem@40 394 case 0x097000: // Line 2 A-lead
philpem@40 395 case 0x09F000:
philpem@40 396 break;
philpem@40 397 }
philpem@40 398 break;
philpem@59 399 case 0x0A0000: // Miscellaneous Control Register
philpem@66 400 ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
philpem@59 401 // TODO: handle the ctrl bits properly
philpem@97 402 if (data & 0x8000){
philpem@97 403 state.timer_enabled = 1;
philpem@97 404 }else{
philpem@97 405 state.timer_enabled = 0;
philpem@97 406 state.timer_asserted = 0;
philpem@97 407 }
philpem@59 408 state.dma_reading = (data & 0x4000);
philpem@72 409 if (state.leds != ((~data & 0xF00) >> 8)) {
philpem@72 410 state.leds = (~data & 0xF00) >> 8;
philpem@117 411 #ifdef SHOW_LEDS
philpem@72 412 printf("LEDs: %s %s %s %s\n",
philpem@72 413 (state.leds & 8) ? "R" : "-",
philpem@72 414 (state.leds & 4) ? "G" : "-",
philpem@72 415 (state.leds & 2) ? "Y" : "-",
philpem@72 416 (state.leds & 1) ? "R" : "-");
philpem@117 417 #endif
philpem@72 418 }
philpem@46 419 handled = true;
philpem@40 420 break;
philpem@40 421 case 0x0B0000: // TM/DIALWR
philpem@40 422 break;
philpem@59 423 case 0x0C0000: // Clear Status Register
philpem@59 424 state.genstat = 0xFFFF;
philpem@59 425 state.bsr0 = 0xFFFF;
philpem@59 426 state.bsr1 = 0xFFFF;
philpem@43 427 handled = true;
philpem@40 428 break;
philpem@40 429 case 0x0D0000: // DMA Address Register
philpem@59 430 if (address & 0x004000) {
philpem@59 431 // A14 high -- set most significant bits
philpem@59 432 state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
philpem@59 433 } else {
philpem@59 434 // A14 low -- set least significant bits
philpem@59 435 state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
philpem@59 436 }
philpem@59 437 handled = true;
philpem@40 438 break;
philpem@40 439 case 0x0E0000: // Disk Control Register
philpem@112 440 {
philpem@112 441 bool fd_selected;
philpem@112 442 bool hd_selected;
philpem@112 443 ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
philpem@112 444 // B7 = FDD controller reset
philpem@112 445 if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
philpem@112 446 // B6 = drive 0 select
philpem@112 447 fd_selected = (data & 0x40) != 0;
philpem@112 448 // B5 = motor enable -- TODO
philpem@112 449 // B4 = HDD controller reset
philpem@112 450 if ((data & 0x10) == 0) wd2010_reset(&state.hdc_ctx);
philpem@112 451 // B3 = HDD0 select
philpem@112 452 hd_selected = (data & 0x08) != 0;
philpem@112 453 // B2,1,0 = HDD0 head select -- TODO?
philpem@112 454 if (hd_selected && !state.hd_selected){
philpem@112 455 state.fd_selected = false;
philpem@112 456 state.hd_selected = true;
philpem@112 457 }else if (fd_selected && !state.fd_selected){
philpem@112 458 state.hd_selected = false;
philpem@112 459 state.fd_selected = true;
philpem@112 460 }
philpem@112 461 handled = true;
philpem@112 462 break;
philpem@112 463 }
philpem@40 464 case 0x0F0000: // Line Printer Data Register
philpem@40 465 break;
philpem@40 466 }
philpem@40 467 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 468 // I/O register space, zone B
philpem@40 469 switch (address & 0xF00000) {
philpem@40 470 case 0xC00000: // Expansion slots
philpem@40 471 case 0xD00000:
philpem@40 472 switch (address & 0xFC0000) {
philpem@40 473 case 0xC00000: // Expansion slot 0
philpem@40 474 case 0xC40000: // Expansion slot 1
philpem@40 475 case 0xC80000: // Expansion slot 2
philpem@40 476 case 0xCC0000: // Expansion slot 3
philpem@40 477 case 0xD00000: // Expansion slot 4
philpem@40 478 case 0xD40000: // Expansion slot 5
philpem@40 479 case 0xD80000: // Expansion slot 6
philpem@40 480 case 0xDC0000: // Expansion slot 7
philpem@59 481 fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
philpem@59 482 handled = true;
philpem@40 483 break;
philpem@40 484 }
philpem@40 485 break;
philpem@40 486 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 487 case 0xF00000:
philpem@40 488 switch (address & 0x070000) {
philpem@112 489 case 0x000000: // [ef][08]xxxx ==> WD2010 hard disc controller
philpem@112 490 wd2010_write_reg(&state.hdc_ctx, (address >> 1) & 7, data);
philpem@112 491 handled = true;
philpem@40 492 break;
philpem@40 493 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@112 494 /*ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");*/
philpem@59 495 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
philpem@52 496 handled = true;
philpem@40 497 break;
philpem@40 498 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@116 499 // MCR2 - UNIX PC Rev. P5.1 HDD head select b3 and potential HDD#2 select
philpem@116 500 wd2010_write_reg(&state.hdc_ctx, UNIXPC_REG_MCR2, data);
philpem@116 501 handled = true;
philpem@40 502 break;
philpem@40 503 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@128 504 LOGS("REAL TIME CLOCK DATA WRITE");
philpem@40 505 break;
philpem@40 506 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 507 switch (address & 0x077000) {
philpem@40 508 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@102 509 // Error Enable. If =0, Level7 intrs and bus errors are masked.
philpem@102 510 ENFORCE_SIZE_W(bits, address, 16, "EE");
philpem@102 511 state.ee = ((data & 0x8000) == 0x8000);
philpem@102 512 handled = true;
philpem@59 513 break;
philpem@44 514 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@66 515 ENFORCE_SIZE_W(bits, address, 16, "PIE");
philpem@59 516 state.pie = ((data & 0x8000) == 0x8000);
philpem@59 517 handled = true;
philpem@59 518 break;
philpem@40 519 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@59 520 break;
philpem@40 521 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@66 522 ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
philpem@59 523 state.romlmap = ((data & 0x8000) == 0x8000);
philpem@44 524 handled = true;
philpem@40 525 break;
philpem@59 526 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@66 527 ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
philpem@59 528 break;
philpem@59 529 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@66 530 ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
philpem@59 531 break;
philpem@59 532 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@66 533 ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
philpem@59 534 break;
philpem@59 535 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@66 536 ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
philpem@40 537 break;
philpem@40 538 }
philpem@40 539 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 540 break;
philpem@40 541 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 542 switch (address & 0x07F000) {
philpem@40 543 default:
philpem@40 544 break;
philpem@40 545 }
philpem@40 546 break;
philpem@40 547 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@84 548 // TODO: figure out which sizes are valid (probably just 8 and 16)
philpem@84 549 // ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER");
philpem@93 550 if (bits == 8) {
philpem@128 551 #ifdef LOG_KEYBOARD_WRITES
philpem@128 552 LOG("KBD WR %02X => %02X\n", (address >> 1) & 3, data);
philpem@128 553 #endif
philpem@93 554 keyboard_write(&state.kbd, (address >> 1) & 3, data);
philpem@93 555 handled = true;
philpem@93 556 } else if (bits == 16) {
philpem@128 557 #ifdef LOG_KEYBOARD_WRITES
philpem@128 558 LOG("KBD WR %02X => %04X\n", (address >> 1) & 3, data);
philpem@128 559 #endif
philpem@93 560 keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8);
philpem@93 561 handled = true;
philpem@93 562 }
philpem@40 563 break;
philpem@40 564 }
philpem@40 565 }
philpem@40 566 }
philpem@40 567
philpem@64 568 LOG_NOT_HANDLED_W(bits);
philpem@59 569 }/*}}}*/
philpem@40 570
philpem@59 571 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
philpem@59 572 {
philpem@59 573 bool handled = false;
philpem@119 574 uint32_t data = EMPTY & 0xFFFFFFFF;
philpem@40 575
philpem@59 576 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 577 // I/O register space, zone A
philpem@40 578 switch (address & 0x0F0000) {
philpem@40 579 case 0x010000: // General Status Register
philpem@116 580 /* ENFORCE_SIZE_R(bits, address, 16, "GENSTAT"); */
philpem@116 581 if (bits == 32) {
philpem@116 582 return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
philpem@116 583 } else if (bits == 16) {
philpem@116 584 return (uint16_t)state.genstat;
philpem@116 585 } else {
philpem@116 586 return (uint8_t)(state.genstat & 0xff);
philpem@116 587 }
philpem@40 588 break;
philpem@40 589 case 0x030000: // Bus Status Register 0
philpem@66 590 ENFORCE_SIZE_R(bits, address, 16, "BSR0");
philpem@59 591 return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
philpem@40 592 break;
philpem@40 593 case 0x040000: // Bus Status Register 1
philpem@66 594 ENFORCE_SIZE_R(bits, address, 16, "BSR1");
philpem@59 595 return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
philpem@40 596 break;
philpem@40 597 case 0x050000: // Phone status
philpem@66 598 ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
philpem@40 599 break;
philpem@40 600 case 0x060000: // DMA Count
philpem@55 601 // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
philpem@55 602 // Bit 14 is always unused, so leave it set
philpem@66 603 ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
philpem@59 604 return (state.dma_count & 0x3fff) | 0xC000;
philpem@40 605 break;
philpem@40 606 case 0x070000: // Line Printer Status Register
philpem@53 607 data = 0x00120012; // no parity error, no line printer error, no irqs from FDD or HDD
philpem@78 608 data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0;
philpem@112 609 data |= wd2010_get_irq(&state.hdc_ctx) ? 0x00040004 : 0;
philpem@59 610 return data;
philpem@40 611 break;
philpem@40 612 case 0x080000: // Real Time Clock
philpem@128 613 LOGS("REAL TIME CLOCK READ");
philpem@40 614 break;
philpem@40 615 case 0x090000: // Phone registers
philpem@40 616 switch (address & 0x0FF000) {
philpem@40 617 case 0x090000: // Handset relay
philpem@40 618 case 0x098000:
philpem@40 619 break;
philpem@40 620 case 0x091000: // Line select 2
philpem@40 621 case 0x099000:
philpem@40 622 break;
philpem@40 623 case 0x092000: // Hook relay 1
philpem@40 624 case 0x09A000:
philpem@40 625 break;
philpem@40 626 case 0x093000: // Hook relay 2
philpem@40 627 case 0x09B000:
philpem@40 628 break;
philpem@40 629 case 0x094000: // Line 1 hold
philpem@40 630 case 0x09C000:
philpem@40 631 break;
philpem@40 632 case 0x095000: // Line 2 hold
philpem@40 633 case 0x09D000:
philpem@40 634 break;
philpem@40 635 case 0x096000: // Line 1 A-lead
philpem@40 636 case 0x09E000:
philpem@40 637 break;
philpem@40 638 case 0x097000: // Line 2 A-lead
philpem@40 639 case 0x09F000:
philpem@40 640 break;
philpem@40 641 }
philpem@40 642 break;
philpem@46 643 case 0x0A0000: // Miscellaneous Control Register -- write only!
philpem@46 644 handled = true;
philpem@40 645 break;
philpem@40 646 case 0x0B0000: // TM/DIALWR
philpem@40 647 break;
philpem@46 648 case 0x0C0000: // Clear Status Register -- write only!
philpem@43 649 handled = true;
philpem@40 650 break;
philpem@40 651 case 0x0D0000: // DMA Address Register
philpem@40 652 break;
philpem@40 653 case 0x0E0000: // Disk Control Register
philpem@40 654 break;
philpem@40 655 case 0x0F0000: // Line Printer Data Register
philpem@40 656 break;
philpem@40 657 }
philpem@40 658 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 659 // I/O register space, zone B
philpem@40 660 switch (address & 0xF00000) {
philpem@40 661 case 0xC00000: // Expansion slots
philpem@40 662 case 0xD00000:
philpem@40 663 switch (address & 0xFC0000) {
philpem@40 664 case 0xC00000: // Expansion slot 0
philpem@40 665 case 0xC40000: // Expansion slot 1
philpem@40 666 case 0xC80000: // Expansion slot 2
philpem@40 667 case 0xCC0000: // Expansion slot 3
philpem@40 668 case 0xD00000: // Expansion slot 4
philpem@40 669 case 0xD40000: // Expansion slot 5
philpem@40 670 case 0xD80000: // Expansion slot 6
philpem@40 671 case 0xDC0000: // Expansion slot 7
philpem@65 672 fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
philpem@65 673 handled = true;
philpem@40 674 break;
philpem@40 675 }
philpem@40 676 break;
philpem@40 677 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 678 case 0xF00000:
philpem@40 679 switch (address & 0x070000) {
philpem@40 680 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@112 681 return (wd2010_read_reg(&state.hdc_ctx, (address >> 1) & 7));
philpem@112 682
philpem@40 683 break;
philpem@40 684 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@112 685 /*ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");*/
philpem@59 686 return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
philpem@40 687 break;
philpem@40 688 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 689 break;
philpem@40 690 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@128 691 LOGS("REAL TIME CLOCK DATA READ");
philpem@40 692 break;
philpem@40 693 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 694 switch (address & 0x077000) {
philpem@40 695 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@44 696 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@40 697 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 698 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@40 699 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@40 700 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@40 701 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@44 702 // All write-only registers... TODO: bus error?
philpem@44 703 handled = true;
philpem@40 704 break;
philpem@44 705 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
philpem@40 706 break;
philpem@40 707 }
philpem@40 708 break;
philpem@40 709 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 710 break;
philpem@40 711 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 712 switch (address & 0x07F000) {
philpem@40 713 default:
philpem@40 714 break;
philpem@40 715 }
philpem@40 716 break;
philpem@40 717 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@84 718 // TODO: figure out which sizes are valid (probably just 8 and 16)
philpem@84 719 //ENFORCE_SIZE_R(bits, address, 16, "KEYBOARD CONTROLLER");
philpem@84 720 {
philpem@93 721 if (bits == 8) {
philpem@93 722 return keyboard_read(&state.kbd, (address >> 1) & 3);
philpem@93 723 } else {
philpem@93 724 return keyboard_read(&state.kbd, (address >> 1) & 3) << 8;
philpem@93 725 }
philpem@84 726 return data;
philpem@84 727 }
philpem@40 728 break;
philpem@40 729 }
philpem@40 730 }
philpem@40 731 }
philpem@40 732
philpem@64 733 LOG_NOT_HANDLED_R(bits);
philpem@64 734
philpem@59 735 return data;
philpem@59 736 }/*}}}*/
philpem@40 737
philpem@59 738
philpem@59 739 /********************************************************
philpem@59 740 * m68k memory read/write support functions for Musashi
philpem@59 741 ********************************************************/
philpem@59 742
philpem@59 743 /**
philpem@59 744 * @brief Read M68K memory, 32-bit
philpem@59 745 */
philpem@59 746 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
philpem@59 747 {
philpem@119 748 uint32_t data = EMPTY & 0xFFFFFFFF;
philpem@59 749
philpem@59 750 // If ROMLMAP is set, force system to access ROM
philpem@59 751 if (!state.romlmap)
philpem@59 752 address |= 0x800000;
philpem@59 753
philpem@59 754 // Check access permissions
philpem@59 755 ACCESS_CHECK_RD(address, 32);
philpem@59 756
philpem@59 757 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@59 758 // ROM access
philpem@60 759 return RD32(state.rom, address, ROM_SIZE - 1);
philpem@60 760 } else if (address <= 0x3fffff) {
philpem@59 761 // RAM access
philpem@128 762 uint32_t newAddr = MAP_ADDR(address);
philpem@128 763
philpem@63 764 if (newAddr <= 0x1fffff) {
philpem@129 765 // Base memory wraps around
philpem@129 766 return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 767 } else {
philpem@119 768 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@63 769 return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 770 else
philpem@119 771 return EMPTY & 0xffffffff;
philpem@63 772 }
philpem@59 773 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@59 774 // I/O register space, zone A
philpem@59 775 switch (address & 0x0F0000) {
philpem@59 776 case 0x000000: // Map RAM access
philpem@59 777 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
philpem@60 778 return RD32(state.map, address, 0x7FF);
philpem@59 779 break;
philpem@59 780 case 0x020000: // Video RAM
philpem@59 781 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@60 782 return RD32(state.vram, address, 0x7FFF);
philpem@59 783 break;
philpem@59 784 default:
philpem@60 785 return IoRead(address, 32);
philpem@59 786 }
philpem@59 787 } else {
philpem@60 788 return IoRead(address, 32);
philpem@59 789 }
philpem@59 790
philpem@40 791 return data;
philpem@59 792 }/*}}}*/
philpem@40 793
philpem@40 794 /**
philpem@40 795 * @brief Read M68K memory, 16-bit
philpem@40 796 */
philpem@59 797 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
philpem@40 798 {
philpem@119 799 uint16_t data = EMPTY & 0xFFFF;
philpem@40 800
philpem@40 801 // If ROMLMAP is set, force system to access ROM
philpem@40 802 if (!state.romlmap)
philpem@40 803 address |= 0x800000;
philpem@40 804
philpem@40 805 // Check access permissions
philpem@40 806 ACCESS_CHECK_RD(address, 16);
philpem@40 807
philpem@40 808 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 809 // ROM access
philpem@40 810 data = RD16(state.rom, address, ROM_SIZE - 1);
philpem@60 811 } else if (address <= 0x3fffff) {
philpem@40 812 // RAM access
philpem@128 813 uint32_t newAddr = MAP_ADDR(address);
philpem@128 814
philpem@63 815 if (newAddr <= 0x1fffff) {
philpem@129 816 // Base memory wraps around
philpem@129 817 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 818 } else {
philpem@119 819 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@63 820 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 821 else
philpem@119 822 return EMPTY & 0xffff;
philpem@63 823 }
philpem@40 824 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 825 // I/O register space, zone A
philpem@40 826 switch (address & 0x0F0000) {
philpem@40 827 case 0x000000: // Map RAM access
philpem@40 828 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 829 data = RD16(state.map, address, 0x7FF);
philpem@40 830 break;
philpem@40 831 case 0x020000: // Video RAM
philpem@40 832 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 833 data = RD16(state.vram, address, 0x7FFF);
philpem@40 834 break;
philpem@59 835 default:
philpem@59 836 data = IoRead(address, 16);
philpem@40 837 }
philpem@59 838 } else {
philpem@59 839 data = IoRead(address, 16);
philpem@40 840 }
philpem@40 841
philpem@40 842 return data;
philpem@59 843 }/*}}}*/
philpem@40 844
philpem@40 845 /**
philpem@40 846 * @brief Read M68K memory, 8-bit
philpem@40 847 */
philpem@59 848 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
philpem@40 849 {
philpem@119 850 uint8_t data = EMPTY & 0xFF;
philpem@40 851
philpem@40 852 // If ROMLMAP is set, force system to access ROM
philpem@40 853 if (!state.romlmap)
philpem@40 854 address |= 0x800000;
philpem@40 855
philpem@40 856 // Check access permissions
philpem@40 857 ACCESS_CHECK_RD(address, 8);
philpem@40 858
philpem@40 859 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 860 // ROM access
philpem@40 861 data = RD8(state.rom, address, ROM_SIZE - 1);
philpem@60 862 } else if (address <= 0x3fffff) {
philpem@40 863 // RAM access
philpem@128 864 uint32_t newAddr = MAP_ADDR(address);
philpem@128 865
philpem@63 866 if (newAddr <= 0x1fffff) {
philpem@129 867 // Base memory wraps around
philpem@129 868 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 869 } else {
philpem@119 870 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@63 871 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 872 else
philpem@119 873 return EMPTY & 0xff;
philpem@63 874 }
philpem@40 875 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 876 // I/O register space, zone A
philpem@40 877 switch (address & 0x0F0000) {
philpem@40 878 case 0x000000: // Map RAM access
philpem@40 879 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 880 data = RD8(state.map, address, 0x7FF);
philpem@40 881 break;
philpem@40 882 case 0x020000: // Video RAM
philpem@40 883 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 884 data = RD8(state.vram, address, 0x7FFF);
philpem@40 885 break;
philpem@59 886 default:
philpem@59 887 data = IoRead(address, 8);
philpem@40 888 }
philpem@59 889 } else {
philpem@59 890 data = IoRead(address, 8);
philpem@40 891 }
philpem@40 892
philpem@40 893 return data;
philpem@59 894 }/*}}}*/
philpem@40 895
philpem@40 896 /**
philpem@40 897 * @brief Write M68K memory, 32-bit
philpem@40 898 */
philpem@59 899 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
philpem@40 900 {
philpem@40 901 // If ROMLMAP is set, force system to access ROM
philpem@40 902 if (!state.romlmap)
philpem@40 903 address |= 0x800000;
philpem@40 904
philpem@40 905 // Check access permissions
philpem@40 906 ACCESS_CHECK_WR(address, 32);
philpem@40 907
philpem@40 908 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 909 // ROM access
philpem@60 910 } else if (address <= 0x3FFFFF) {
philpem@40 911 // RAM access
philpem@128 912 uint32_t newAddr = MAP_ADDR(address);
philpem@128 913
philpem@119 914 if (newAddr <= 0x1fffff) {
philpem@119 915 if (newAddr < state.base_ram_size) {
philpem@119 916 WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@119 917 }
philpem@119 918 } else {
philpem@119 919 if ((newAddr - 0x200000) < state.exp_ram_size) {
philpem@119 920 WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@119 921 }
philpem@119 922 }
philpem@40 923 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 924 // I/O register space, zone A
philpem@40 925 switch (address & 0x0F0000) {
philpem@40 926 case 0x000000: // Map RAM access
philpem@105 927 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X\n", address);
philpem@40 928 WR32(state.map, address, 0x7FF, value);
philpem@40 929 break;
philpem@40 930 case 0x020000: // Video RAM
philpem@105 931 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 932 WR32(state.vram, address, 0x7FFF, value);
philpem@40 933 break;
philpem@59 934 default:
philpem@59 935 IoWrite(address, value, 32);
philpem@40 936 }
philpem@59 937 } else {
philpem@59 938 IoWrite(address, value, 32);
philpem@40 939 }
philpem@59 940 }/*}}}*/
philpem@40 941
philpem@40 942 /**
philpem@40 943 * @brief Write M68K memory, 16-bit
philpem@40 944 */
philpem@59 945 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
philpem@40 946 {
philpem@40 947 // If ROMLMAP is set, force system to access ROM
philpem@40 948 if (!state.romlmap)
philpem@40 949 address |= 0x800000;
philpem@40 950
philpem@40 951 // Check access permissions
philpem@40 952 ACCESS_CHECK_WR(address, 16);
philpem@40 953
philpem@40 954 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 955 // ROM access
philpem@60 956 } else if (address <= 0x3FFFFF) {
philpem@40 957 // RAM access
philpem@128 958 uint32_t newAddr = MAP_ADDR(address);
philpem@112 959
philpem@119 960 if (newAddr <= 0x1fffff) {
philpem@119 961 if (newAddr < state.base_ram_size) {
philpem@119 962 WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@119 963 }
philpem@119 964 } else {
philpem@119 965 if ((newAddr - 0x200000) < state.exp_ram_size) {
philpem@119 966 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@119 967 }
philpem@119 968 }
philpem@40 969 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 970 // I/O register space, zone A
philpem@40 971 switch (address & 0x0F0000) {
philpem@40 972 case 0x000000: // Map RAM access
philpem@40 973 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 974 WR16(state.map, address, 0x7FF, value);
philpem@40 975 break;
philpem@40 976 case 0x020000: // Video RAM
philpem@40 977 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 978 WR16(state.vram, address, 0x7FFF, value);
philpem@40 979 break;
philpem@59 980 default:
philpem@59 981 IoWrite(address, value, 16);
philpem@40 982 }
philpem@59 983 } else {
philpem@59 984 IoWrite(address, value, 16);
philpem@40 985 }
philpem@59 986 }/*}}}*/
philpem@40 987
philpem@40 988 /**
philpem@40 989 * @brief Write M68K memory, 8-bit
philpem@40 990 */
philpem@59 991 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
philpem@40 992 {
philpem@40 993 // If ROMLMAP is set, force system to access ROM
philpem@40 994 if (!state.romlmap)
philpem@40 995 address |= 0x800000;
philpem@40 996
philpem@40 997 // Check access permissions
philpem@40 998 ACCESS_CHECK_WR(address, 8);
philpem@40 999
philpem@40 1000 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 1001 // ROM access (read only!)
philpem@60 1002 } else if (address <= 0x3FFFFF) {
philpem@40 1003 // RAM access
philpem@128 1004 uint32_t newAddr = MAP_ADDR(address);
philpem@128 1005
philpem@119 1006 if (newAddr <= 0x1fffff) {
philpem@119 1007 if (newAddr < state.base_ram_size) {
philpem@119 1008 WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@119 1009 }
philpem@119 1010 } else {
philpem@119 1011 if ((newAddr - 0x200000) < state.exp_ram_size) {
philpem@119 1012 WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@119 1013 }
philpem@119 1014 }
philpem@40 1015 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 1016 // I/O register space, zone A
philpem@40 1017 switch (address & 0x0F0000) {
philpem@40 1018 case 0x000000: // Map RAM access
philpem@59 1019 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 1020 WR8(state.map, address, 0x7FF, value);
philpem@40 1021 break;
philpem@40 1022 case 0x020000: // Video RAM
philpem@59 1023 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 1024 WR8(state.vram, address, 0x7FFF, value);
philpem@40 1025 break;
philpem@59 1026 default:
philpem@59 1027 IoWrite(address, value, 8);
philpem@40 1028 }
philpem@59 1029 } else {
philpem@59 1030 IoWrite(address, value, 8);
philpem@40 1031 }
philpem@59 1032 }/*}}}*/
philpem@40 1033
philpem@40 1034
philpem@40 1035 // for the disassembler
philpem@121 1036 uint32_t m68k_read_disassembler_32(uint32_t addr)
philpem@121 1037 {
philpem@121 1038 if (addr < 0x400000) {
philpem@128 1039 // XXX FIXME BUGBUG update this to use the new mapper macros!
philpem@121 1040 uint16_t page = (addr >> 12) & 0x3FF;
philpem@121 1041 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@121 1042 uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
philpem@121 1043 if (newAddr <= 0x1fffff) {
philpem@121 1044 if (newAddr >= state.base_ram_size)
philpem@121 1045 return EMPTY;
philpem@121 1046 else
philpem@121 1047 return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@121 1048 } else {
philpem@121 1049 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@121 1050 return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@121 1051 else
philpem@121 1052 return EMPTY;
philpem@121 1053 }
philpem@121 1054 } else {
philpem@128 1055 LOG("WARNING: Disassembler RD32 out of range 0x%08X\n", addr);
philpem@121 1056 return EMPTY;
philpem@121 1057 }
philpem@121 1058 }
philpem@40 1059
philpem@121 1060 uint32_t m68k_read_disassembler_16(uint32_t addr)
philpem@121 1061 {
philpem@121 1062 if (addr < 0x400000) {
philpem@121 1063 uint16_t page = (addr >> 12) & 0x3FF;
philpem@121 1064 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@121 1065 uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
philpem@121 1066 if (newAddr <= 0x1fffff) {
philpem@121 1067 if (newAddr >= state.base_ram_size)
philpem@121 1068 return EMPTY & 0xffff;
philpem@121 1069 else
philpem@121 1070 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@121 1071 } else {
philpem@121 1072 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@121 1073 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@121 1074 else
philpem@121 1075 return EMPTY & 0xffff;
philpem@121 1076 }
philpem@121 1077 } else {
philpem@128 1078 LOG("WARNING: Disassembler RD16 out of range 0x%08X\n", addr);
philpem@121 1079 return EMPTY & 0xffff;
philpem@121 1080 }
philpem@121 1081 }
philpem@121 1082
philpem@121 1083 uint32_t m68k_read_disassembler_8 (uint32_t addr)
philpem@121 1084 {
philpem@121 1085 if (addr < 0x400000) {
philpem@121 1086 uint16_t page = (addr >> 12) & 0x3FF;
philpem@121 1087 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@121 1088 uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
philpem@121 1089 if (newAddr <= 0x1fffff) {
philpem@121 1090 if (newAddr >= state.base_ram_size)
philpem@121 1091 return EMPTY & 0xff;
philpem@121 1092 else
philpem@121 1093 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@121 1094 } else {
philpem@121 1095 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@121 1096 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@121 1097 else
philpem@121 1098 return EMPTY & 0xff;
philpem@121 1099 }
philpem@121 1100 } else {
philpem@128 1101 LOG("WARNING: Disassembler RD8 out of range 0x%08X\n", addr);
philpem@121 1102 return EMPTY & 0xff;
philpem@121 1103 }
philpem@121 1104 }
philpem@121 1105