src/memory.c

Wed, 13 Mar 2013 00:40:42 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Wed, 13 Mar 2013 00:40:42 +0000
branch
experimental_memory_mapper_v2
changeset 133
84ed5ec1d1e0
parent 132
8a7dc9b5b1db
child 140
1e4c45b144c4
permissions
-rw-r--r--

use MAP_ADDR_TO_PAGE for memory mapping

philpem@40 1 #include <stdio.h>
philpem@40 2 #include <stdlib.h>
philpem@40 3 #include <stdint.h>
philpem@40 4 #include <stdbool.h>
philpem@59 5 #include <assert.h>
philpem@40 6 #include "musashi/m68k.h"
philpem@40 7 #include "state.h"
philpem@100 8 #include "utils.h"
philpem@40 9 #include "memory.h"
philpem@40 10
philpem@119 11 // The value which will be returned if the CPU attempts to read from empty memory
philpem@119 12 // TODO (FIXME?) - need to figure out if R/W ops wrap around. This seems to appease the UNIX kernel and P4TEST.
philpem@119 13 #define EMPTY 0xFFFFFFFFUL
philpem@129 14 //#define EMPTY 0x55555555UL
philpem@129 15 //#define EMPTY 0x00000000UL
philpem@119 16
philpem@40 17 /******************
philpem@40 18 * Memory mapping
philpem@40 19 ******************/
philpem@40 20
philpem@128 21 /// Set a page bit
philpem@133 22 #define MAP_SET_PAGEBIT(addr, bit) state.map[(MAP_ADDR_TO_PAGE(addr))*2] |= ((uint8_t)bit << 2)
philpem@128 23 /// Clear a page bit
philpem@133 24 #define MAP_CLR_PAGEBIT(addr, bit) state.map[(MAP_ADDR_TO_PAGE(addr))*2] &= ~((uint8_t)bit << 2)
philpem@40 25
philpem@40 26
philpem@40 27 /********************************************************
philpem@40 28 * m68k memory read/write support functions for Musashi
philpem@40 29 ********************************************************/
philpem@40 30
philpem@40 31 /**
philpem@40 32 * @brief Check memory access permissions for a write operation.
philpem@40 33 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
philpem@40 34 * gcc throws warnings when you have a return-with-value in a void
philpem@40 35 * function, even if the return-with-value is completely unreachable.
philpem@40 36 * Similarly it doesn't like it if you have a return without a value
philpem@40 37 * in a non-void function, even if it's impossible to ever reach the
philpem@40 38 * return-with-no-value. UGH!
philpem@40 39 */
philpem@59 40 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
philpem@59 41 #define ACCESS_CHECK_WR(address, bits) \
philpem@59 42 do { \
philpem@128 43 if (access_check_cpu(address, bits, true)) { \
philpem@40 44 return; \
philpem@40 45 } \
philpem@70 46 } while (0)
philpem@59 47 /*}}}*/
philpem@40 48
philpem@40 49 /**
philpem@40 50 * @brief Check memory access permissions for a read operation.
philpem@40 51 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
philpem@40 52 * gcc throws warnings when you have a return-with-value in a void
philpem@40 53 * function, even if the return-with-value is completely unreachable.
philpem@40 54 * Similarly it doesn't like it if you have a return without a value
philpem@40 55 * in a non-void function, even if it's impossible to ever reach the
philpem@40 56 * return-with-no-value. UGH!
philpem@40 57 */
philpem@59 58 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
philpem@59 59 #define ACCESS_CHECK_RD(address, bits) \
philpem@59 60 do { \
philpem@128 61 if (access_check_cpu(address, bits, false)) { \
philpem@128 62 if (bits == 32) \
philpem@128 63 return EMPTY & 0xFFFFFFFF; \
philpem@40 64 else \
philpem@128 65 return EMPTY & ((1UL << bits)-1); \
philpem@40 66 } \
philpem@70 67 } while (0)
philpem@59 68 /*}}}*/
philpem@40 69
philpem@128 70
philpem@128 71 /**
philpem@128 72 * Update the page bits for a given memory address
philpem@128 73 *
philpem@128 74 * @param addr Memory address being accessed
philpem@128 75 * @param l7intr Set to <i>true</i> if a level-seven interrupt has been
philpem@128 76 * signalled (even if <b>ENABLE ERROR</b> isn't set).
philpem@128 77 * @param write Set to <i>true</i> if the address is being written to.
philpem@128 78 */
philpem@128 79 static void update_page_bits(uint32_t addr, bool l7intr, bool write)
philpem@112 80 {
philpem@128 81 bool ps0_state = false;
philpem@128 82
philpem@128 83 // Don't try and update pagebits for non-RAM addresses
philpem@128 84 if (addr > 0x3FFFFF)
philpem@128 85 return;
philpem@128 86
philpem@128 87 if (l7intr) {
philpem@128 88 // if (!(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
philpem@128 89 // FIXME FUCKUP The ruddy TRM is wrong AGAIN! If above line is uncommented, Really Bad Things Happen.
philpem@128 90 if ((MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
philpem@128 91 // Level 7 interrupt, PS0 clear, PS1 don't-care. Set PS0.
philpem@128 92 ps0_state = true;
philpem@128 93 }
philpem@128 94 } else {
philpem@128 95 // No L7 interrupt
philpem@128 96 if ((write && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && (MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) ||
philpem@128 97 (write && (MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)))
philpem@128 98 {
philpem@128 99 // No L7 interrupt, PS[1:0] = 0b01, write
philpem@128 100 // No L7 interrupt, PS[1:0] = 0b10, write
philpem@128 101 ps0_state = true;
philpem@128 102 }
philpem@128 103 }
philpem@112 104
philpem@128 105 #ifdef MAPRAM_BIT_TEST
philpem@128 106 LOG("Starting Mapram Bit Test");
philpem@128 107 state.map[0] = state.map[1] = 0;
philpem@128 108 LOG("Start = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 109 MAP_SET_PAGEBIT(0, PAGE_BIT_WE);
philpem@128 110 LOG("Set WE = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 111 MAP_SET_PAGEBIT(0, PAGE_BIT_PS1);
philpem@128 112 LOG("Set PS1 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 113 MAP_SET_PAGEBIT(0, PAGE_BIT_PS0);
philpem@128 114 LOG("Set PS0 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 115
philpem@128 116 MAP_CLR_PAGEBIT(0, PAGE_BIT_WE);
philpem@128 117 LOG("Clr WE = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 118 MAP_CLR_PAGEBIT(0, PAGE_BIT_PS1);
philpem@128 119 LOG("Clr PS1 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 120 MAP_CLR_PAGEBIT(0, PAGE_BIT_PS0);
philpem@128 121 LOG("Clr PS0 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
philpem@128 122 exit(-1);
philpem@128 123 #endif
philpem@128 124
philpem@128 125 uint16_t old_pagebits = MAP_PAGEBITS(addr);
philpem@112 126
philpem@128 127 // PS1 is always set on access
philpem@128 128 MAP_SET_PAGEBIT(addr, PAGE_BIT_PS1);
philpem@128 129
philpem@128 130 uint16_t new_pagebit1 = MAP_PAGEBITS(addr);
philpem@128 131
philpem@128 132 // Update PS0
philpem@128 133 if (ps0_state) {
philpem@128 134 MAP_SET_PAGEBIT(addr, PAGE_BIT_PS0);
philpem@128 135 } else {
philpem@128 136 MAP_CLR_PAGEBIT(addr, PAGE_BIT_PS0);
philpem@128 137 }
philpem@112 138
philpem@128 139 uint16_t new_pagebit2 = MAP_PAGEBITS(addr);
philpem@128 140 switch (addr) {
philpem@128 141 case 0x000000:
philpem@128 142 case 0x001000:
philpem@128 143 case 0x002000:
philpem@128 144 case 0x003000:
philpem@128 145 case 0x004000:
philpem@128 146 case 0x033000:
philpem@128 147 case 0x034000:
philpem@128 148 case 0x035000:
philpem@128 149 LOG("Addr %08X MapNew %04X Pagebit update -- ps0 %d, %02X => %02X => %02X", addr, MAPRAM_ADDR(addr), ps0_state, old_pagebits, new_pagebit1, new_pagebit2);
philpem@128 150 default:
philpem@112 151 break;
philpem@112 152 }
philpem@128 153 }
philpem@128 154
philpem@128 155 bool access_check_dma(void)
philpem@128 156 {
philpem@128 157 // TODO FIXME BUGBUG Sanity check - Make sure DMAC is only accessing RAM addresses
philpem@128 158
philpem@128 159 // DMA access check -- make sure the page is mapped in
philpem@128 160 if (!(MAP_PAGEBITS(state.dma_address) & PAGE_BIT_PS0) && !(MAP_PAGEBITS(state.dma_address) & PAGE_BIT_PS1)) {
philpem@128 161 // DMA access to page which is not mapped in.
philpem@128 162 // Level 7 interrupt, page fault, DMA invoked
philpem@128 163 state.genstat = 0xABFF
philpem@128 164 | (state.dma_reading ? 0x4000 : 0)
philpem@128 165 | (state.pie ? 0x0400 : 0);
philpem@128 166
philpem@128 167 // XXX: Check all this stuff.
philpem@112 168 state.bsr0 = 0x3C00;
philpem@112 169 state.bsr0 |= (state.dma_address >> 16);
philpem@112 170 state.bsr1 = state.dma_address & 0xffff;
philpem@128 171
philpem@128 172 // Update page bits for this transfer
philpem@128 173 update_page_bits(state.dma_address, true, !state.dma_reading);
philpem@128 174
philpem@128 175 // XXX: is this right?
philpem@128 176 // Fire a Level 7 interrupt
philpem@128 177 /*if (state.ee)*/ m68k_set_irq(7);
philpem@128 178
philpem@128 179 LOG("BUS ERROR FROM DMA: genstat=%04X, bsr0=%04X, bsr1=%04X\n", state.genstat, state.bsr0, state.bsr1);
philpem@128 180 return false;
philpem@128 181 } else {
philpem@128 182 // No errors. Just update the page bits.
philpem@128 183 update_page_bits(state.dma_address, false, !state.dma_reading);
philpem@128 184 return true;
philpem@112 185 }
philpem@128 186 }
philpem@128 187
philpem@128 188 /**
philpem@128 189 * Check memory access permissions for a CPU memory access.
philpem@128 190 *
philpem@128 191 * @param addr Virtual memory address being accessed (from CPU address bus).
philpem@128 192 * @param bits Word size of this transfer (8, 16 or 32 bits).
philpem@128 193 * @param write <i>true</i> if this is a write operation, <i>false</i> if it is a read operation.
philpem@128 194 * @return <i>true</i> if the access was denied and a level-7 interrupt and/or bus error raised.
philpem@128 195 * <i>false</i> if the access was allowed.
philpem@128 196 */
philpem@128 197 bool access_check_cpu(uint32_t addr, int bits, bool write)
philpem@128 198 {
philpem@128 199 bool supervisor = (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000);
philpem@128 200 bool fault = false;
philpem@128 201
philpem@128 202 // TODO FIXME BUGBUG? Do we need to check for supervisor access here?
philpem@128 203 if ((addr >= 0x000000) && (addr <= 0x3FFFFF) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
philpem@128 204 // (A) Page Fault -- user access to page which is not mapped in
philpem@128 205 // Level 7 Interrupt, Bus Error, regs=PAGEFAULT
philpem@128 206 if (write) {
philpem@128 207 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0);
philpem@128 208 } else {
philpem@128 209 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0);
philpem@128 210 }
philpem@128 211 fault = true;
philpem@128 212 } else if (!supervisor && (addr >= 0x000000) && (addr <= 0x07FFFF)) {
philpem@128 213 // (B) User attempted to access the kernel
philpem@128 214 // Level 7 Interrupt, Bus Error, regs=KERNEL
philpem@128 215 if (write) {
philpem@128 216 // XXX: BUGBUG? Is this correct?
philpem@128 217 state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0);
philpem@128 218 } else {
philpem@128 219 state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0);
philpem@128 220 }
philpem@128 221 fault = true;
philpem@128 222 } else if (!supervisor && write && (addr >= 0x000000) && (addr <= 0x3FFFFF) && !(MAP_PAGEBITS(addr) & PAGE_BIT_WE)) {
philpem@128 223 // (C) User attempted to write to a page which is not write enabled
philpem@128 224 // Level 7 Interrupt, Bus Error, regs=WRITE_EN
philpem@128 225 if (write) {
philpem@128 226 // XXX: BUGBUG? Is this correct?
philpem@128 227 state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0);
philpem@128 228 } else {
philpem@128 229 state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0);
philpem@128 230 }
philpem@128 231 fault = true;
philpem@128 232 } else if (!supervisor && (addr >= 0x400000) && (addr <= 0xFFFFFF)) {
philpem@128 233 // (D) UIE - user I/O exception
philpem@128 234 // Bus Error only, regs=UIE
philpem@128 235 if (write) {
philpem@128 236 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0);
philpem@128 237 } else {
philpem@128 238 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0);
philpem@128 239 }
philpem@128 240 fault = true;
philpem@128 241 }
philpem@128 242
philpem@128 243 // Update the page bits first
philpem@128 244 update_page_bits(addr, fault, write);
philpem@128 245
philpem@128 246 if (fault) {
philpem@128 247 if (bits >= 16)
philpem@128 248 state.bsr0 = 0x7C00;
philpem@128 249 else
philpem@128 250 state.bsr0 = (addr & 1) ? 0x7E00 : 0x7D00;
philpem@128 251 // FIXME? Physical or virtual address here?
philpem@128 252 state.bsr0 |= (addr >> 16);
philpem@128 253 state.bsr1 = addr & 0xffff;
philpem@128 254
philpem@128 255 LOG("CPU Bus Error or L7Intr while %s, vaddr %08X, map %08X, pagebits 0x%02X bsr0=%04X bsr1=%04X genstat=%04X",
philpem@128 256 write ? "writing" : "reading", addr,
philpem@128 257 MAPRAM_ADDR(addr & 0x3fffff),
philpem@128 258 MAP_PAGEBITS(addr & 0x3fffff),
philpem@128 259 state.bsr0, state.bsr1, state.genstat);
philpem@128 260
philpem@128 261 // FIXME? BUGBUG? Does EE disable one or both of these?
philpem@128 262 // /*if (state.ee)*/ m68k_set_irq(7);
philpem@128 263 /*if (state.ee)*/ m68k_pulse_bus_error();
philpem@128 264 }
philpem@128 265
philpem@128 266 return fault;
philpem@112 267 }
philpem@112 268
philpem@40 269 // Logging macros
philpem@59 270 #define LOG_NOT_HANDLED_R(bits) \
philpem@128 271 if (!handled) fprintf(stderr, "unhandled read%02d, addr=0x%08X\n", bits, address);
philpem@40 272
philpem@59 273 #define LOG_NOT_HANDLED_W(bits) \
philpem@128 274 if (!handled) fprintf(stderr, "unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
philpem@59 275
philpem@59 276 /********************************************************
philpem@59 277 * I/O read/write functions
philpem@59 278 ********************************************************/
philpem@40 279
philpem@40 280 /**
philpem@59 281 * Issue a warning if a read operation is made with an invalid size
philpem@40 282 */
philpem@66 283 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
philpem@40 284 {
philpem@59 285 assert((bits == 8) || (bits == 16) || (bits == 32));
philpem@59 286 if ((bits & allowed) == 0) {
philpem@128 287 LOG("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
philpem@59 288 }
philpem@59 289 }
philpem@59 290
philpem@66 291 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
philpem@40 292 {
philpem@66 293 ENFORCE_SIZE(bits, address, true, allowed, regname);
philpem@66 294 }
philpem@66 295
philpem@66 296 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
philpem@66 297 {
philpem@66 298 ENFORCE_SIZE(bits, address, false, allowed, regname);
philpem@66 299 }
philpem@66 300
philpem@59 301 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
philpem@59 302 {
philpem@40 303 bool handled = false;
philpem@40 304
philpem@59 305 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 306 // I/O register space, zone A
philpem@40 307 switch (address & 0x0F0000) {
philpem@40 308 case 0x010000: // General Status Register
philpem@59 309 if (bits == 16)
philpem@59 310 state.genstat = (data & 0xffff);
philpem@59 311 else if (bits == 8) {
philpem@59 312 if (address & 0)
philpem@59 313 state.genstat = data;
philpem@59 314 else
philpem@59 315 state.genstat = data << 8;
philpem@59 316 }
philpem@40 317 handled = true;
philpem@40 318 break;
philpem@40 319 case 0x030000: // Bus Status Register 0
philpem@40 320 break;
philpem@40 321 case 0x040000: // Bus Status Register 1
philpem@40 322 break;
philpem@40 323 case 0x050000: // Phone status
philpem@40 324 break;
philpem@40 325 case 0x060000: // DMA Count
philpem@66 326 ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
philpem@59 327 state.dma_count = (data & 0x3FFF);
philpem@59 328 state.idmarw = ((data & 0x4000) == 0x4000);
philpem@59 329 state.dmaen = ((data & 0x8000) == 0x8000);
philpem@59 330 // This handles the "dummy DMA transfer" mentioned in the docs
philpem@112 331 // disabled because it causes the floppy test to fail
philpem@112 332 #if 0
philpem@112 333 if (!state.idmarw){
philpem@112 334 if (access_check_dma(true)){
philpem@112 335 uint32_t newAddr = mapAddr(state.dma_address, true);
philpem@112 336 // RAM access
philpem@112 337 if (newAddr <= 0x1fffff)
philpem@112 338 WR16(state.base_ram, newAddr, state.base_ram_size - 1, 0xFF);
philpem@112 339 else if (address <= 0x3FFFFF)
philpem@112 340 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, 0xFF);
philpem@112 341 }
philpem@112 342 }
philpem@112 343 #endif
philpem@59 344 state.dma_count++;
philpem@53 345 handled = true;
philpem@40 346 break;
philpem@40 347 case 0x070000: // Line Printer Status Register
philpem@40 348 break;
philpem@40 349 case 0x080000: // Real Time Clock
philpem@128 350 LOGS("REAL TIME CLOCK WRITE");
philpem@40 351 break;
philpem@40 352 case 0x090000: // Phone registers
philpem@40 353 switch (address & 0x0FF000) {
philpem@40 354 case 0x090000: // Handset relay
philpem@40 355 case 0x098000:
philpem@40 356 break;
philpem@40 357 case 0x091000: // Line select 2
philpem@40 358 case 0x099000:
philpem@40 359 break;
philpem@40 360 case 0x092000: // Hook relay 1
philpem@40 361 case 0x09A000:
philpem@40 362 break;
philpem@40 363 case 0x093000: // Hook relay 2
philpem@40 364 case 0x09B000:
philpem@40 365 break;
philpem@40 366 case 0x094000: // Line 1 hold
philpem@40 367 case 0x09C000:
philpem@40 368 break;
philpem@40 369 case 0x095000: // Line 2 hold
philpem@40 370 case 0x09D000:
philpem@40 371 break;
philpem@40 372 case 0x096000: // Line 1 A-lead
philpem@40 373 case 0x09E000:
philpem@40 374 break;
philpem@40 375 case 0x097000: // Line 2 A-lead
philpem@40 376 case 0x09F000:
philpem@40 377 break;
philpem@40 378 }
philpem@40 379 break;
philpem@59 380 case 0x0A0000: // Miscellaneous Control Register
philpem@66 381 ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
philpem@59 382 // TODO: handle the ctrl bits properly
philpem@97 383 if (data & 0x8000){
philpem@97 384 state.timer_enabled = 1;
philpem@97 385 }else{
philpem@97 386 state.timer_enabled = 0;
philpem@97 387 state.timer_asserted = 0;
philpem@97 388 }
philpem@59 389 state.dma_reading = (data & 0x4000);
philpem@72 390 if (state.leds != ((~data & 0xF00) >> 8)) {
philpem@72 391 state.leds = (~data & 0xF00) >> 8;
philpem@117 392 #ifdef SHOW_LEDS
philpem@72 393 printf("LEDs: %s %s %s %s\n",
philpem@72 394 (state.leds & 8) ? "R" : "-",
philpem@72 395 (state.leds & 4) ? "G" : "-",
philpem@72 396 (state.leds & 2) ? "Y" : "-",
philpem@72 397 (state.leds & 1) ? "R" : "-");
philpem@117 398 #endif
philpem@72 399 }
philpem@46 400 handled = true;
philpem@40 401 break;
philpem@40 402 case 0x0B0000: // TM/DIALWR
philpem@40 403 break;
philpem@59 404 case 0x0C0000: // Clear Status Register
philpem@59 405 state.genstat = 0xFFFF;
philpem@59 406 state.bsr0 = 0xFFFF;
philpem@59 407 state.bsr1 = 0xFFFF;
philpem@43 408 handled = true;
philpem@40 409 break;
philpem@40 410 case 0x0D0000: // DMA Address Register
philpem@59 411 if (address & 0x004000) {
philpem@59 412 // A14 high -- set most significant bits
philpem@59 413 state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
philpem@59 414 } else {
philpem@59 415 // A14 low -- set least significant bits
philpem@59 416 state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
philpem@59 417 }
philpem@59 418 handled = true;
philpem@40 419 break;
philpem@40 420 case 0x0E0000: // Disk Control Register
philpem@112 421 {
philpem@112 422 bool fd_selected;
philpem@112 423 bool hd_selected;
philpem@112 424 ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
philpem@112 425 // B7 = FDD controller reset
philpem@112 426 if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
philpem@112 427 // B6 = drive 0 select
philpem@112 428 fd_selected = (data & 0x40) != 0;
philpem@112 429 // B5 = motor enable -- TODO
philpem@112 430 // B4 = HDD controller reset
philpem@112 431 if ((data & 0x10) == 0) wd2010_reset(&state.hdc_ctx);
philpem@112 432 // B3 = HDD0 select
philpem@112 433 hd_selected = (data & 0x08) != 0;
philpem@112 434 // B2,1,0 = HDD0 head select -- TODO?
philpem@112 435 if (hd_selected && !state.hd_selected){
philpem@112 436 state.fd_selected = false;
philpem@112 437 state.hd_selected = true;
philpem@112 438 }else if (fd_selected && !state.fd_selected){
philpem@112 439 state.hd_selected = false;
philpem@112 440 state.fd_selected = true;
philpem@112 441 }
philpem@112 442 handled = true;
philpem@112 443 break;
philpem@112 444 }
philpem@40 445 case 0x0F0000: // Line Printer Data Register
philpem@40 446 break;
philpem@40 447 }
philpem@40 448 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 449 // I/O register space, zone B
philpem@40 450 switch (address & 0xF00000) {
philpem@40 451 case 0xC00000: // Expansion slots
philpem@40 452 case 0xD00000:
philpem@40 453 switch (address & 0xFC0000) {
philpem@40 454 case 0xC00000: // Expansion slot 0
philpem@40 455 case 0xC40000: // Expansion slot 1
philpem@40 456 case 0xC80000: // Expansion slot 2
philpem@40 457 case 0xCC0000: // Expansion slot 3
philpem@40 458 case 0xD00000: // Expansion slot 4
philpem@40 459 case 0xD40000: // Expansion slot 5
philpem@40 460 case 0xD80000: // Expansion slot 6
philpem@40 461 case 0xDC0000: // Expansion slot 7
philpem@59 462 fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
philpem@59 463 handled = true;
philpem@40 464 break;
philpem@40 465 }
philpem@40 466 break;
philpem@40 467 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 468 case 0xF00000:
philpem@40 469 switch (address & 0x070000) {
philpem@112 470 case 0x000000: // [ef][08]xxxx ==> WD2010 hard disc controller
philpem@112 471 wd2010_write_reg(&state.hdc_ctx, (address >> 1) & 7, data);
philpem@112 472 handled = true;
philpem@40 473 break;
philpem@40 474 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@112 475 /*ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");*/
philpem@59 476 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
philpem@52 477 handled = true;
philpem@40 478 break;
philpem@40 479 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@116 480 // MCR2 - UNIX PC Rev. P5.1 HDD head select b3 and potential HDD#2 select
philpem@116 481 wd2010_write_reg(&state.hdc_ctx, UNIXPC_REG_MCR2, data);
philpem@116 482 handled = true;
philpem@40 483 break;
philpem@40 484 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@128 485 LOGS("REAL TIME CLOCK DATA WRITE");
philpem@40 486 break;
philpem@40 487 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 488 switch (address & 0x077000) {
philpem@40 489 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@102 490 // Error Enable. If =0, Level7 intrs and bus errors are masked.
philpem@102 491 ENFORCE_SIZE_W(bits, address, 16, "EE");
philpem@102 492 state.ee = ((data & 0x8000) == 0x8000);
philpem@102 493 handled = true;
philpem@59 494 break;
philpem@44 495 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@66 496 ENFORCE_SIZE_W(bits, address, 16, "PIE");
philpem@59 497 state.pie = ((data & 0x8000) == 0x8000);
philpem@59 498 handled = true;
philpem@59 499 break;
philpem@40 500 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@59 501 break;
philpem@40 502 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@66 503 ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
philpem@59 504 state.romlmap = ((data & 0x8000) == 0x8000);
philpem@44 505 handled = true;
philpem@40 506 break;
philpem@59 507 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@66 508 ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
philpem@59 509 break;
philpem@59 510 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@66 511 ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
philpem@59 512 break;
philpem@59 513 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@66 514 ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
philpem@59 515 break;
philpem@59 516 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@66 517 ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
philpem@40 518 break;
philpem@40 519 }
philpem@40 520 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 521 break;
philpem@40 522 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 523 switch (address & 0x07F000) {
philpem@40 524 default:
philpem@40 525 break;
philpem@40 526 }
philpem@40 527 break;
philpem@40 528 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@84 529 // TODO: figure out which sizes are valid (probably just 8 and 16)
philpem@84 530 // ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER");
philpem@93 531 if (bits == 8) {
philpem@128 532 #ifdef LOG_KEYBOARD_WRITES
philpem@128 533 LOG("KBD WR %02X => %02X\n", (address >> 1) & 3, data);
philpem@128 534 #endif
philpem@93 535 keyboard_write(&state.kbd, (address >> 1) & 3, data);
philpem@93 536 handled = true;
philpem@93 537 } else if (bits == 16) {
philpem@128 538 #ifdef LOG_KEYBOARD_WRITES
philpem@128 539 LOG("KBD WR %02X => %04X\n", (address >> 1) & 3, data);
philpem@128 540 #endif
philpem@93 541 keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8);
philpem@93 542 handled = true;
philpem@93 543 }
philpem@40 544 break;
philpem@40 545 }
philpem@40 546 }
philpem@40 547 }
philpem@40 548
philpem@64 549 LOG_NOT_HANDLED_W(bits);
philpem@59 550 }/*}}}*/
philpem@40 551
philpem@59 552 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
philpem@59 553 {
philpem@59 554 bool handled = false;
philpem@119 555 uint32_t data = EMPTY & 0xFFFFFFFF;
philpem@40 556
philpem@59 557 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 558 // I/O register space, zone A
philpem@40 559 switch (address & 0x0F0000) {
philpem@40 560 case 0x010000: // General Status Register
philpem@116 561 /* ENFORCE_SIZE_R(bits, address, 16, "GENSTAT"); */
philpem@116 562 if (bits == 32) {
philpem@116 563 return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
philpem@116 564 } else if (bits == 16) {
philpem@116 565 return (uint16_t)state.genstat;
philpem@116 566 } else {
philpem@116 567 return (uint8_t)(state.genstat & 0xff);
philpem@116 568 }
philpem@40 569 break;
philpem@40 570 case 0x030000: // Bus Status Register 0
philpem@66 571 ENFORCE_SIZE_R(bits, address, 16, "BSR0");
philpem@59 572 return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
philpem@40 573 break;
philpem@40 574 case 0x040000: // Bus Status Register 1
philpem@66 575 ENFORCE_SIZE_R(bits, address, 16, "BSR1");
philpem@59 576 return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
philpem@40 577 break;
philpem@40 578 case 0x050000: // Phone status
philpem@66 579 ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
philpem@40 580 break;
philpem@40 581 case 0x060000: // DMA Count
philpem@55 582 // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
philpem@55 583 // Bit 14 is always unused, so leave it set
philpem@66 584 ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
philpem@59 585 return (state.dma_count & 0x3fff) | 0xC000;
philpem@40 586 break;
philpem@40 587 case 0x070000: // Line Printer Status Register
philpem@53 588 data = 0x00120012; // no parity error, no line printer error, no irqs from FDD or HDD
philpem@78 589 data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0;
philpem@112 590 data |= wd2010_get_irq(&state.hdc_ctx) ? 0x00040004 : 0;
philpem@59 591 return data;
philpem@40 592 break;
philpem@40 593 case 0x080000: // Real Time Clock
philpem@128 594 LOGS("REAL TIME CLOCK READ");
philpem@40 595 break;
philpem@40 596 case 0x090000: // Phone registers
philpem@40 597 switch (address & 0x0FF000) {
philpem@40 598 case 0x090000: // Handset relay
philpem@40 599 case 0x098000:
philpem@40 600 break;
philpem@40 601 case 0x091000: // Line select 2
philpem@40 602 case 0x099000:
philpem@40 603 break;
philpem@40 604 case 0x092000: // Hook relay 1
philpem@40 605 case 0x09A000:
philpem@40 606 break;
philpem@40 607 case 0x093000: // Hook relay 2
philpem@40 608 case 0x09B000:
philpem@40 609 break;
philpem@40 610 case 0x094000: // Line 1 hold
philpem@40 611 case 0x09C000:
philpem@40 612 break;
philpem@40 613 case 0x095000: // Line 2 hold
philpem@40 614 case 0x09D000:
philpem@40 615 break;
philpem@40 616 case 0x096000: // Line 1 A-lead
philpem@40 617 case 0x09E000:
philpem@40 618 break;
philpem@40 619 case 0x097000: // Line 2 A-lead
philpem@40 620 case 0x09F000:
philpem@40 621 break;
philpem@40 622 }
philpem@40 623 break;
philpem@46 624 case 0x0A0000: // Miscellaneous Control Register -- write only!
philpem@46 625 handled = true;
philpem@40 626 break;
philpem@40 627 case 0x0B0000: // TM/DIALWR
philpem@40 628 break;
philpem@46 629 case 0x0C0000: // Clear Status Register -- write only!
philpem@43 630 handled = true;
philpem@40 631 break;
philpem@40 632 case 0x0D0000: // DMA Address Register
philpem@40 633 break;
philpem@40 634 case 0x0E0000: // Disk Control Register
philpem@40 635 break;
philpem@40 636 case 0x0F0000: // Line Printer Data Register
philpem@40 637 break;
philpem@40 638 }
philpem@40 639 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 640 // I/O register space, zone B
philpem@40 641 switch (address & 0xF00000) {
philpem@40 642 case 0xC00000: // Expansion slots
philpem@40 643 case 0xD00000:
philpem@40 644 switch (address & 0xFC0000) {
philpem@40 645 case 0xC00000: // Expansion slot 0
philpem@40 646 case 0xC40000: // Expansion slot 1
philpem@40 647 case 0xC80000: // Expansion slot 2
philpem@40 648 case 0xCC0000: // Expansion slot 3
philpem@40 649 case 0xD00000: // Expansion slot 4
philpem@40 650 case 0xD40000: // Expansion slot 5
philpem@40 651 case 0xD80000: // Expansion slot 6
philpem@40 652 case 0xDC0000: // Expansion slot 7
philpem@65 653 fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
philpem@65 654 handled = true;
philpem@40 655 break;
philpem@40 656 }
philpem@40 657 break;
philpem@40 658 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 659 case 0xF00000:
philpem@40 660 switch (address & 0x070000) {
philpem@40 661 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@112 662 return (wd2010_read_reg(&state.hdc_ctx, (address >> 1) & 7));
philpem@112 663
philpem@40 664 break;
philpem@40 665 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@112 666 /*ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");*/
philpem@59 667 return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
philpem@40 668 break;
philpem@40 669 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 670 break;
philpem@40 671 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@128 672 LOGS("REAL TIME CLOCK DATA READ");
philpem@40 673 break;
philpem@40 674 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 675 switch (address & 0x077000) {
philpem@40 676 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@44 677 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@40 678 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 679 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@40 680 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@40 681 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@40 682 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@44 683 // All write-only registers... TODO: bus error?
philpem@44 684 handled = true;
philpem@40 685 break;
philpem@44 686 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
philpem@40 687 break;
philpem@40 688 }
philpem@40 689 break;
philpem@40 690 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 691 break;
philpem@40 692 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 693 switch (address & 0x07F000) {
philpem@40 694 default:
philpem@40 695 break;
philpem@40 696 }
philpem@40 697 break;
philpem@40 698 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@84 699 // TODO: figure out which sizes are valid (probably just 8 and 16)
philpem@84 700 //ENFORCE_SIZE_R(bits, address, 16, "KEYBOARD CONTROLLER");
philpem@84 701 {
philpem@93 702 if (bits == 8) {
philpem@93 703 return keyboard_read(&state.kbd, (address >> 1) & 3);
philpem@93 704 } else {
philpem@93 705 return keyboard_read(&state.kbd, (address >> 1) & 3) << 8;
philpem@93 706 }
philpem@84 707 return data;
philpem@84 708 }
philpem@40 709 break;
philpem@40 710 }
philpem@40 711 }
philpem@40 712 }
philpem@40 713
philpem@64 714 LOG_NOT_HANDLED_R(bits);
philpem@64 715
philpem@59 716 return data;
philpem@59 717 }/*}}}*/
philpem@40 718
philpem@59 719
philpem@59 720 /********************************************************
philpem@59 721 * m68k memory read/write support functions for Musashi
philpem@59 722 ********************************************************/
philpem@59 723
philpem@59 724 /**
philpem@59 725 * @brief Read M68K memory, 32-bit
philpem@59 726 */
philpem@59 727 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
philpem@59 728 {
philpem@119 729 uint32_t data = EMPTY & 0xFFFFFFFF;
philpem@59 730
philpem@59 731 // If ROMLMAP is set, force system to access ROM
philpem@59 732 if (!state.romlmap)
philpem@59 733 address |= 0x800000;
philpem@59 734
philpem@59 735 // Check access permissions
philpem@59 736 ACCESS_CHECK_RD(address, 32);
philpem@59 737
philpem@59 738 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@59 739 // ROM access
philpem@60 740 return RD32(state.rom, address, ROM_SIZE - 1);
philpem@60 741 } else if (address <= 0x3fffff) {
philpem@59 742 // RAM access
philpem@128 743 uint32_t newAddr = MAP_ADDR(address);
philpem@128 744
philpem@63 745 if (newAddr <= 0x1fffff) {
philpem@129 746 // Base memory wraps around
philpem@129 747 return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 748 } else {
philpem@119 749 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@63 750 return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 751 else
philpem@119 752 return EMPTY & 0xffffffff;
philpem@63 753 }
philpem@59 754 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@59 755 // I/O register space, zone A
philpem@59 756 switch (address & 0x0F0000) {
philpem@59 757 case 0x000000: // Map RAM access
philpem@59 758 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
philpem@60 759 return RD32(state.map, address, 0x7FF);
philpem@59 760 break;
philpem@59 761 case 0x020000: // Video RAM
philpem@59 762 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@60 763 return RD32(state.vram, address, 0x7FFF);
philpem@59 764 break;
philpem@59 765 default:
philpem@60 766 return IoRead(address, 32);
philpem@59 767 }
philpem@59 768 } else {
philpem@60 769 return IoRead(address, 32);
philpem@59 770 }
philpem@59 771
philpem@40 772 return data;
philpem@59 773 }/*}}}*/
philpem@40 774
philpem@40 775 /**
philpem@40 776 * @brief Read M68K memory, 16-bit
philpem@40 777 */
philpem@59 778 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
philpem@40 779 {
philpem@119 780 uint16_t data = EMPTY & 0xFFFF;
philpem@40 781
philpem@40 782 // If ROMLMAP is set, force system to access ROM
philpem@40 783 if (!state.romlmap)
philpem@40 784 address |= 0x800000;
philpem@40 785
philpem@40 786 // Check access permissions
philpem@40 787 ACCESS_CHECK_RD(address, 16);
philpem@40 788
philpem@40 789 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 790 // ROM access
philpem@40 791 data = RD16(state.rom, address, ROM_SIZE - 1);
philpem@60 792 } else if (address <= 0x3fffff) {
philpem@40 793 // RAM access
philpem@128 794 uint32_t newAddr = MAP_ADDR(address);
philpem@128 795
philpem@63 796 if (newAddr <= 0x1fffff) {
philpem@129 797 // Base memory wraps around
philpem@129 798 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 799 } else {
philpem@119 800 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@63 801 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 802 else
philpem@119 803 return EMPTY & 0xffff;
philpem@63 804 }
philpem@40 805 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 806 // I/O register space, zone A
philpem@40 807 switch (address & 0x0F0000) {
philpem@40 808 case 0x000000: // Map RAM access
philpem@40 809 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 810 data = RD16(state.map, address, 0x7FF);
philpem@40 811 break;
philpem@40 812 case 0x020000: // Video RAM
philpem@40 813 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 814 data = RD16(state.vram, address, 0x7FFF);
philpem@40 815 break;
philpem@59 816 default:
philpem@59 817 data = IoRead(address, 16);
philpem@40 818 }
philpem@59 819 } else {
philpem@59 820 data = IoRead(address, 16);
philpem@40 821 }
philpem@40 822
philpem@40 823 return data;
philpem@59 824 }/*}}}*/
philpem@40 825
philpem@40 826 /**
philpem@40 827 * @brief Read M68K memory, 8-bit
philpem@40 828 */
philpem@59 829 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
philpem@40 830 {
philpem@119 831 uint8_t data = EMPTY & 0xFF;
philpem@40 832
philpem@40 833 // If ROMLMAP is set, force system to access ROM
philpem@40 834 if (!state.romlmap)
philpem@40 835 address |= 0x800000;
philpem@40 836
philpem@40 837 // Check access permissions
philpem@40 838 ACCESS_CHECK_RD(address, 8);
philpem@40 839
philpem@40 840 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 841 // ROM access
philpem@40 842 data = RD8(state.rom, address, ROM_SIZE - 1);
philpem@60 843 } else if (address <= 0x3fffff) {
philpem@40 844 // RAM access
philpem@128 845 uint32_t newAddr = MAP_ADDR(address);
philpem@128 846
philpem@63 847 if (newAddr <= 0x1fffff) {
philpem@129 848 // Base memory wraps around
philpem@129 849 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 850 } else {
philpem@119 851 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@63 852 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 853 else
philpem@119 854 return EMPTY & 0xff;
philpem@63 855 }
philpem@40 856 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 857 // I/O register space, zone A
philpem@40 858 switch (address & 0x0F0000) {
philpem@40 859 case 0x000000: // Map RAM access
philpem@40 860 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 861 data = RD8(state.map, address, 0x7FF);
philpem@40 862 break;
philpem@40 863 case 0x020000: // Video RAM
philpem@40 864 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 865 data = RD8(state.vram, address, 0x7FFF);
philpem@40 866 break;
philpem@59 867 default:
philpem@59 868 data = IoRead(address, 8);
philpem@40 869 }
philpem@59 870 } else {
philpem@59 871 data = IoRead(address, 8);
philpem@40 872 }
philpem@40 873
philpem@40 874 return data;
philpem@59 875 }/*}}}*/
philpem@40 876
philpem@40 877 /**
philpem@40 878 * @brief Write M68K memory, 32-bit
philpem@40 879 */
philpem@59 880 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
philpem@40 881 {
philpem@40 882 // If ROMLMAP is set, force system to access ROM
philpem@40 883 if (!state.romlmap)
philpem@40 884 address |= 0x800000;
philpem@40 885
philpem@40 886 // Check access permissions
philpem@40 887 ACCESS_CHECK_WR(address, 32);
philpem@40 888
philpem@40 889 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 890 // ROM access
philpem@60 891 } else if (address <= 0x3FFFFF) {
philpem@40 892 // RAM access
philpem@128 893 uint32_t newAddr = MAP_ADDR(address);
philpem@128 894
philpem@119 895 if (newAddr <= 0x1fffff) {
philpem@119 896 if (newAddr < state.base_ram_size) {
philpem@119 897 WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@119 898 }
philpem@119 899 } else {
philpem@119 900 if ((newAddr - 0x200000) < state.exp_ram_size) {
philpem@119 901 WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@119 902 }
philpem@119 903 }
philpem@40 904 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 905 // I/O register space, zone A
philpem@40 906 switch (address & 0x0F0000) {
philpem@40 907 case 0x000000: // Map RAM access
philpem@105 908 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X\n", address);
philpem@40 909 WR32(state.map, address, 0x7FF, value);
philpem@40 910 break;
philpem@40 911 case 0x020000: // Video RAM
philpem@105 912 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 913 WR32(state.vram, address, 0x7FFF, value);
philpem@40 914 break;
philpem@59 915 default:
philpem@59 916 IoWrite(address, value, 32);
philpem@40 917 }
philpem@59 918 } else {
philpem@59 919 IoWrite(address, value, 32);
philpem@40 920 }
philpem@59 921 }/*}}}*/
philpem@40 922
philpem@40 923 /**
philpem@40 924 * @brief Write M68K memory, 16-bit
philpem@40 925 */
philpem@59 926 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
philpem@40 927 {
philpem@40 928 // If ROMLMAP is set, force system to access ROM
philpem@40 929 if (!state.romlmap)
philpem@40 930 address |= 0x800000;
philpem@40 931
philpem@40 932 // Check access permissions
philpem@40 933 ACCESS_CHECK_WR(address, 16);
philpem@40 934
philpem@40 935 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 936 // ROM access
philpem@60 937 } else if (address <= 0x3FFFFF) {
philpem@40 938 // RAM access
philpem@128 939 uint32_t newAddr = MAP_ADDR(address);
philpem@112 940
philpem@119 941 if (newAddr <= 0x1fffff) {
philpem@119 942 if (newAddr < state.base_ram_size) {
philpem@119 943 WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@119 944 }
philpem@119 945 } else {
philpem@119 946 if ((newAddr - 0x200000) < state.exp_ram_size) {
philpem@119 947 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@119 948 }
philpem@119 949 }
philpem@40 950 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 951 // I/O register space, zone A
philpem@40 952 switch (address & 0x0F0000) {
philpem@40 953 case 0x000000: // Map RAM access
philpem@40 954 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 955 WR16(state.map, address, 0x7FF, value);
philpem@40 956 break;
philpem@40 957 case 0x020000: // Video RAM
philpem@40 958 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 959 WR16(state.vram, address, 0x7FFF, value);
philpem@40 960 break;
philpem@59 961 default:
philpem@59 962 IoWrite(address, value, 16);
philpem@40 963 }
philpem@59 964 } else {
philpem@59 965 IoWrite(address, value, 16);
philpem@40 966 }
philpem@59 967 }/*}}}*/
philpem@40 968
philpem@40 969 /**
philpem@40 970 * @brief Write M68K memory, 8-bit
philpem@40 971 */
philpem@59 972 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
philpem@40 973 {
philpem@40 974 // If ROMLMAP is set, force system to access ROM
philpem@40 975 if (!state.romlmap)
philpem@40 976 address |= 0x800000;
philpem@40 977
philpem@40 978 // Check access permissions
philpem@40 979 ACCESS_CHECK_WR(address, 8);
philpem@40 980
philpem@40 981 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 982 // ROM access (read only!)
philpem@60 983 } else if (address <= 0x3FFFFF) {
philpem@40 984 // RAM access
philpem@128 985 uint32_t newAddr = MAP_ADDR(address);
philpem@128 986
philpem@119 987 if (newAddr <= 0x1fffff) {
philpem@119 988 if (newAddr < state.base_ram_size) {
philpem@119 989 WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@119 990 }
philpem@119 991 } else {
philpem@119 992 if ((newAddr - 0x200000) < state.exp_ram_size) {
philpem@119 993 WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@119 994 }
philpem@119 995 }
philpem@40 996 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 997 // I/O register space, zone A
philpem@40 998 switch (address & 0x0F0000) {
philpem@40 999 case 0x000000: // Map RAM access
philpem@59 1000 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 1001 WR8(state.map, address, 0x7FF, value);
philpem@40 1002 break;
philpem@40 1003 case 0x020000: // Video RAM
philpem@59 1004 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 1005 WR8(state.vram, address, 0x7FFF, value);
philpem@40 1006 break;
philpem@59 1007 default:
philpem@59 1008 IoWrite(address, value, 8);
philpem@40 1009 }
philpem@59 1010 } else {
philpem@59 1011 IoWrite(address, value, 8);
philpem@40 1012 }
philpem@59 1013 }/*}}}*/
philpem@40 1014
philpem@40 1015
philpem@40 1016 // for the disassembler
philpem@121 1017 uint32_t m68k_read_disassembler_32(uint32_t addr)
philpem@121 1018 {
philpem@121 1019 if (addr < 0x400000) {
philpem@128 1020 // XXX FIXME BUGBUG update this to use the new mapper macros!
philpem@121 1021 uint16_t page = (addr >> 12) & 0x3FF;
philpem@121 1022 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@121 1023 uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
philpem@121 1024 if (newAddr <= 0x1fffff) {
philpem@121 1025 if (newAddr >= state.base_ram_size)
philpem@121 1026 return EMPTY;
philpem@121 1027 else
philpem@121 1028 return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@121 1029 } else {
philpem@121 1030 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@121 1031 return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@121 1032 else
philpem@121 1033 return EMPTY;
philpem@121 1034 }
philpem@121 1035 } else {
philpem@128 1036 LOG("WARNING: Disassembler RD32 out of range 0x%08X\n", addr);
philpem@121 1037 return EMPTY;
philpem@121 1038 }
philpem@121 1039 }
philpem@40 1040
philpem@121 1041 uint32_t m68k_read_disassembler_16(uint32_t addr)
philpem@121 1042 {
philpem@121 1043 if (addr < 0x400000) {
philpem@121 1044 uint16_t page = (addr >> 12) & 0x3FF;
philpem@121 1045 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@121 1046 uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
philpem@121 1047 if (newAddr <= 0x1fffff) {
philpem@121 1048 if (newAddr >= state.base_ram_size)
philpem@121 1049 return EMPTY & 0xffff;
philpem@121 1050 else
philpem@121 1051 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@121 1052 } else {
philpem@121 1053 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@121 1054 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@121 1055 else
philpem@121 1056 return EMPTY & 0xffff;
philpem@121 1057 }
philpem@121 1058 } else {
philpem@128 1059 LOG("WARNING: Disassembler RD16 out of range 0x%08X\n", addr);
philpem@121 1060 return EMPTY & 0xffff;
philpem@121 1061 }
philpem@121 1062 }
philpem@121 1063
philpem@121 1064 uint32_t m68k_read_disassembler_8 (uint32_t addr)
philpem@121 1065 {
philpem@121 1066 if (addr < 0x400000) {
philpem@121 1067 uint16_t page = (addr >> 12) & 0x3FF;
philpem@121 1068 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@121 1069 uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
philpem@121 1070 if (newAddr <= 0x1fffff) {
philpem@121 1071 if (newAddr >= state.base_ram_size)
philpem@121 1072 return EMPTY & 0xff;
philpem@121 1073 else
philpem@121 1074 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@121 1075 } else {
philpem@121 1076 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@121 1077 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@121 1078 else
philpem@121 1079 return EMPTY & 0xff;
philpem@121 1080 }
philpem@121 1081 } else {
philpem@128 1082 LOG("WARNING: Disassembler RD8 out of range 0x%08X\n", addr);
philpem@121 1083 return EMPTY & 0xff;
philpem@121 1084 }
philpem@121 1085 }
philpem@121 1086