src/memory.c

Mon, 13 Dec 2010 03:00:43 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Mon, 13 Dec 2010 03:00:43 +0000
changeset 56
b3f309d46e97
parent 55
ba6b8e570062
child 57
feb84193a43a
permissions
-rw-r--r--

disable floppy interrupts (to CPU), force HDD int flag on (i.e. command always complete)

philpem@40 1 #include <stdio.h>
philpem@40 2 #include <stdlib.h>
philpem@40 3 #include <stdint.h>
philpem@40 4 #include <stdbool.h>
philpem@40 5 #include "musashi/m68k.h"
philpem@40 6 #include "state.h"
philpem@40 7 #include "memory.h"
philpem@40 8
philpem@40 9 /******************
philpem@40 10 * Memory mapping
philpem@40 11 ******************/
philpem@40 12
philpem@40 13 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
philpem@40 14
philpem@40 15 uint32_t mapAddr(uint32_t addr, bool writing)
philpem@40 16 {
philpem@40 17 if (addr < 0x400000) {
philpem@40 18 // RAM access. Check against the Map RAM
philpem@40 19 // Start by getting the original page address
philpem@40 20 uint16_t page = (addr >> 12) & 0x3FF;
philpem@40 21
philpem@40 22 // Look it up in the map RAM and get the physical page address
philpem@40 23 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@40 24
philpem@40 25 // Update the Page Status bits
philpem@40 26 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
philpem@40 27 if (pagebits != 0) {
philpem@40 28 if (writing)
philpem@40 29 state.map[page*2] |= 0x60; // Page written to (dirty)
philpem@40 30 else
philpem@40 31 state.map[page*2] |= 0x40; // Page accessed but not written
philpem@40 32 }
philpem@40 33
philpem@40 34 // Return the address with the new physical page spliced in
philpem@40 35 return (new_page_addr << 12) + (addr & 0xFFF);
philpem@40 36 } else {
philpem@40 37 // I/O, VRAM or MapRAM space; no mapping is performed or required
philpem@40 38 // TODO: assert here?
philpem@40 39 return addr;
philpem@40 40 }
philpem@40 41 }
philpem@40 42
philpem@40 43 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)
philpem@40 44 {
philpem@40 45 // Are we in Supervisor mode?
philpem@40 46 if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
philpem@40 47 // Yes. We can do anything we like.
philpem@40 48 return MEM_ALLOWED;
philpem@40 49
philpem@40 50 // If we're here, then we must be in User mode.
philpem@40 51 // Check that the user didn't access memory outside of the RAM area
philpem@40 52 if (addr >= 0x400000)
philpem@40 53 return MEM_UIE;
philpem@40 54
philpem@40 55 // This leaves us with Page Fault checking. Get the page bits for this page.
philpem@40 56 uint16_t page = (addr >> 12) & 0x3FF;
philpem@40 57 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
philpem@40 58
philpem@40 59 // Check page is present
philpem@40 60 if ((pagebits & 0x03) == 0)
philpem@40 61 return MEM_PAGEFAULT;
philpem@40 62
philpem@40 63 // User attempt to access the kernel
philpem@40 64 // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
philpem@40 65 if (((addr >> 19) & 0x0F) == 0)
philpem@40 66 return MEM_KERNEL;
philpem@40 67
philpem@40 68 // Check page is write enabled
philpem@40 69 if ((pagebits & 0x04) == 0)
philpem@40 70 return MEM_PAGE_NO_WE;
philpem@40 71
philpem@40 72 // Page access allowed.
philpem@40 73 return MEM_ALLOWED;
philpem@40 74 }
philpem@40 75
philpem@40 76 #undef MAPRAM
philpem@40 77
philpem@40 78
philpem@40 79 /********************************************************
philpem@40 80 * m68k memory read/write support functions for Musashi
philpem@40 81 ********************************************************/
philpem@40 82
philpem@40 83 /**
philpem@40 84 * @brief Check memory access permissions for a write operation.
philpem@40 85 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
philpem@40 86 * gcc throws warnings when you have a return-with-value in a void
philpem@40 87 * function, even if the return-with-value is completely unreachable.
philpem@40 88 * Similarly it doesn't like it if you have a return without a value
philpem@40 89 * in a non-void function, even if it's impossible to ever reach the
philpem@40 90 * return-with-no-value. UGH!
philpem@40 91 */
philpem@40 92 #define ACCESS_CHECK_WR(address, bits) do { \
philpem@40 93 bool fault = false; \
philpem@40 94 /* MEM_STATUS st; */ \
philpem@40 95 switch (checkMemoryAccess(address, true)) { \
philpem@40 96 case MEM_ALLOWED: \
philpem@40 97 /* Access allowed */ \
philpem@40 98 break; \
philpem@40 99 case MEM_PAGEFAULT: \
philpem@40 100 /* Page fault */ \
philpem@44 101 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0); \
philpem@40 102 fault = true; \
philpem@40 103 break; \
philpem@40 104 case MEM_UIE: \
philpem@40 105 /* User access to memory above 4MB */ \
philpem@44 106 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0); \
philpem@40 107 fault = true; \
philpem@40 108 break; \
philpem@40 109 case MEM_KERNEL: \
philpem@40 110 case MEM_PAGE_NO_WE: \
philpem@40 111 /* kernel access or page not write enabled */ \
philpem@40 112 /* TODO: which regs need setting? */ \
philpem@40 113 fault = true; \
philpem@40 114 break; \
philpem@40 115 } \
philpem@40 116 \
philpem@40 117 if (fault) { \
philpem@40 118 if (bits >= 16) \
philpem@40 119 state.bsr0 = 0x7F00; \
philpem@40 120 else \
philpem@40 121 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
philpem@40 122 state.bsr0 |= (address >> 16); \
philpem@40 123 state.bsr1 = address & 0xffff; \
philpem@40 124 printf("ERR: BusError WR\n"); \
philpem@40 125 m68k_pulse_bus_error(); \
philpem@40 126 return; \
philpem@40 127 } \
philpem@40 128 } while (false)
philpem@40 129
philpem@40 130 /**
philpem@40 131 * @brief Check memory access permissions for a read operation.
philpem@40 132 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
philpem@40 133 * gcc throws warnings when you have a return-with-value in a void
philpem@40 134 * function, even if the return-with-value is completely unreachable.
philpem@40 135 * Similarly it doesn't like it if you have a return without a value
philpem@40 136 * in a non-void function, even if it's impossible to ever reach the
philpem@40 137 * return-with-no-value. UGH!
philpem@40 138 */
philpem@40 139 #define ACCESS_CHECK_RD(address, bits) do { \
philpem@40 140 bool fault = false; \
philpem@40 141 /* MEM_STATUS st; */ \
philpem@40 142 switch (checkMemoryAccess(address, false)) { \
philpem@40 143 case MEM_ALLOWED: \
philpem@40 144 /* Access allowed */ \
philpem@40 145 break; \
philpem@40 146 case MEM_PAGEFAULT: \
philpem@40 147 /* Page fault */ \
philpem@44 148 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0); \
philpem@40 149 fault = true; \
philpem@40 150 break; \
philpem@40 151 case MEM_UIE: \
philpem@40 152 /* User access to memory above 4MB */ \
philpem@44 153 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0); \
philpem@40 154 fault = true; \
philpem@40 155 break; \
philpem@40 156 case MEM_KERNEL: \
philpem@40 157 case MEM_PAGE_NO_WE: \
philpem@40 158 /* kernel access or page not write enabled */ \
philpem@40 159 /* TODO: which regs need setting? */ \
philpem@40 160 fault = true; \
philpem@40 161 break; \
philpem@40 162 } \
philpem@40 163 \
philpem@40 164 if (fault) { \
philpem@40 165 if (bits >= 16) \
philpem@40 166 state.bsr0 = 0x7F00; \
philpem@40 167 else \
philpem@40 168 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
philpem@40 169 state.bsr0 |= (address >> 16); \
philpem@40 170 state.bsr1 = address & 0xffff; \
philpem@40 171 printf("ERR: BusError RD\n"); \
philpem@40 172 m68k_pulse_bus_error(); \
philpem@40 173 return 0xFFFFFFFF; \
philpem@40 174 } \
philpem@40 175 } while (false)
philpem@40 176
philpem@40 177 // Logging macros
philpem@40 178 #define LOG_NOT_HANDLED_R(bits) \
philpem@40 179 do { \
philpem@40 180 if (!handled) \
philpem@40 181 printf("unhandled read%02d, addr=0x%08X\n", bits, address); \
philpem@40 182 } while (0);
philpem@40 183
philpem@40 184 #define LOG_NOT_HANDLED_W(bits) \
philpem@40 185 do { \
philpem@40 186 if (!handled) \
philpem@40 187 printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, value); \
philpem@40 188 } while (0);
philpem@40 189
philpem@40 190 /**
philpem@40 191 * @brief Read M68K memory, 32-bit
philpem@40 192 */
philpem@40 193 uint32_t m68k_read_memory_32(uint32_t address)
philpem@40 194 {
philpem@40 195 uint32_t data = 0xFFFFFFFF;
philpem@40 196 bool handled = false;
philpem@40 197
philpem@40 198 // If ROMLMAP is set, force system to access ROM
philpem@40 199 if (!state.romlmap)
philpem@40 200 address |= 0x800000;
philpem@40 201
philpem@40 202 // Check access permissions
philpem@40 203 ACCESS_CHECK_RD(address, 32);
philpem@40 204
philpem@40 205 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 206 // ROM access
philpem@40 207 data = RD32(state.rom, address, ROM_SIZE - 1);
philpem@40 208 handled = true;
philpem@40 209 } else if (address <= (state.ram_size - 1)) {
philpem@40 210 // RAM access
philpem@40 211 data = RD32(state.ram, mapAddr(address, false), state.ram_size - 1);
philpem@40 212 handled = true;
philpem@40 213 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 214 // I/O register space, zone A
philpem@40 215 switch (address & 0x0F0000) {
philpem@40 216 case 0x000000: // Map RAM access
philpem@40 217 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 218 data = RD32(state.map, address, 0x7FF);
philpem@40 219 handled = true;
philpem@40 220 break;
philpem@40 221 case 0x010000: // General Status Register
philpem@40 222 data = ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
philpem@40 223 handled = true;
philpem@40 224 break;
philpem@40 225 case 0x020000: // Video RAM
philpem@40 226 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 227 data = RD32(state.vram, address, 0x7FFF);
philpem@40 228 handled = true;
philpem@40 229 break;
philpem@40 230 case 0x030000: // Bus Status Register 0
philpem@40 231 data = ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
philpem@40 232 handled = true;
philpem@40 233 break;
philpem@40 234 case 0x040000: // Bus Status Register 1
philpem@40 235 data = ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
philpem@40 236 handled = true;
philpem@40 237 break;
philpem@40 238 case 0x050000: // Phone status
philpem@40 239 break;
philpem@40 240 case 0x060000: // DMA Count
philpem@55 241 // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
philpem@55 242 // Bit 14 is always unused, so leave it set
philpem@55 243 data = (state.dma_count & 0x3fff) | 0xC000;
philpem@53 244 handled = true;
philpem@40 245 break;
philpem@40 246 case 0x070000: // Line Printer Status Register
philpem@53 247 data = 0x00120012; // no parity error, no line printer error, no irqs from FDD or HDD
philpem@53 248 data |= (state.fdc_ctx.irql) ? 0x00080008 : 0; // FIXME! HACKHACKHACK! shouldn't peek inside FDC structs like this
philpem@40 249 break;
philpem@40 250 case 0x080000: // Real Time Clock
philpem@40 251 break;
philpem@40 252 case 0x090000: // Phone registers
philpem@40 253 switch (address & 0x0FF000) {
philpem@40 254 case 0x090000: // Handset relay
philpem@40 255 case 0x098000:
philpem@40 256 break;
philpem@40 257 case 0x091000: // Line select 2
philpem@40 258 case 0x099000:
philpem@40 259 break;
philpem@40 260 case 0x092000: // Hook relay 1
philpem@40 261 case 0x09A000:
philpem@40 262 break;
philpem@40 263 case 0x093000: // Hook relay 2
philpem@40 264 case 0x09B000:
philpem@40 265 break;
philpem@40 266 case 0x094000: // Line 1 hold
philpem@40 267 case 0x09C000:
philpem@40 268 break;
philpem@40 269 case 0x095000: // Line 2 hold
philpem@40 270 case 0x09D000:
philpem@40 271 break;
philpem@40 272 case 0x096000: // Line 1 A-lead
philpem@40 273 case 0x09E000:
philpem@40 274 break;
philpem@40 275 case 0x097000: // Line 2 A-lead
philpem@40 276 case 0x09F000:
philpem@40 277 break;
philpem@40 278 }
philpem@40 279 break;
philpem@46 280 case 0x0A0000: // Miscellaneous Control Register -- write only!
philpem@46 281 handled = true;
philpem@40 282 break;
philpem@40 283 case 0x0B0000: // TM/DIALWR
philpem@40 284 break;
philpem@46 285 case 0x0C0000: // Clear Status Register -- write only!
philpem@43 286 handled = true;
philpem@40 287 break;
philpem@40 288 case 0x0D0000: // DMA Address Register
philpem@40 289 break;
philpem@40 290 case 0x0E0000: // Disk Control Register
philpem@40 291 break;
philpem@40 292 case 0x0F0000: // Line Printer Data Register
philpem@40 293 break;
philpem@40 294 }
philpem@40 295 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 296 // I/O register space, zone B
philpem@40 297 switch (address & 0xF00000) {
philpem@40 298 case 0xC00000: // Expansion slots
philpem@40 299 case 0xD00000:
philpem@40 300 switch (address & 0xFC0000) {
philpem@40 301 case 0xC00000: // Expansion slot 0
philpem@40 302 case 0xC40000: // Expansion slot 1
philpem@40 303 case 0xC80000: // Expansion slot 2
philpem@40 304 case 0xCC0000: // Expansion slot 3
philpem@40 305 case 0xD00000: // Expansion slot 4
philpem@40 306 case 0xD40000: // Expansion slot 5
philpem@40 307 case 0xD80000: // Expansion slot 6
philpem@40 308 case 0xDC0000: // Expansion slot 7
philpem@40 309 fprintf(stderr, "NOTE: RD32 from expansion card space, addr=0x%08X\n", address);
philpem@40 310 break;
philpem@40 311 }
philpem@40 312 break;
philpem@40 313 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 314 case 0xF00000:
philpem@40 315 switch (address & 0x070000) {
philpem@40 316 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@40 317 break;
philpem@40 318 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@52 319 data = wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
philpem@53 320 printf("WD279X: rd32 %02X ==> %02X\n", (address >> 1) & 3, data);
philpem@52 321 handled = true;
philpem@40 322 break;
philpem@40 323 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 324 break;
philpem@40 325 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 326 break;
philpem@40 327 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 328 switch (address & 0x077000) {
philpem@40 329 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@44 330 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@40 331 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 332 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@44 333 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@44 334 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@44 335 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@44 336 // All write-only registers... TODO: bus error?
philpem@44 337 handled = true;
philpem@40 338 break;
philpem@44 339 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
philpem@40 340 break;
philpem@40 341 }
philpem@40 342 break;
philpem@40 343 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 344 break;
philpem@40 345 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 346 switch (address & 0x07F000) {
philpem@40 347 default:
philpem@40 348 break;
philpem@40 349 }
philpem@40 350 break;
philpem@40 351 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@40 352 break;
philpem@40 353 }
philpem@40 354 }
philpem@40 355 }
philpem@40 356
philpem@40 357 LOG_NOT_HANDLED_R(32);
philpem@40 358 return data;
philpem@40 359 }
philpem@40 360
philpem@40 361 /**
philpem@40 362 * @brief Read M68K memory, 16-bit
philpem@40 363 */
philpem@40 364 uint32_t m68k_read_memory_16(uint32_t address)
philpem@40 365 {
philpem@40 366 uint16_t data = 0xFFFF;
philpem@40 367 bool handled = false;
philpem@40 368
philpem@40 369 // If ROMLMAP is set, force system to access ROM
philpem@40 370 if (!state.romlmap)
philpem@40 371 address |= 0x800000;
philpem@40 372
philpem@40 373 // Check access permissions
philpem@40 374 ACCESS_CHECK_RD(address, 16);
philpem@40 375
philpem@40 376 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 377 // ROM access
philpem@40 378 data = RD16(state.rom, address, ROM_SIZE - 1);
philpem@40 379 handled = true;
philpem@40 380 } else if (address <= (state.ram_size - 1)) {
philpem@40 381 // RAM access
philpem@40 382 data = RD16(state.ram, mapAddr(address, false), state.ram_size - 1);
philpem@40 383 handled = true;
philpem@40 384 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 385 // I/O register space, zone A
philpem@40 386 switch (address & 0x0F0000) {
philpem@40 387 case 0x000000: // Map RAM access
philpem@40 388 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 389 data = RD16(state.map, address, 0x7FF);
philpem@40 390 handled = true;
philpem@40 391 break;
philpem@40 392 case 0x010000: // General Status Register
philpem@40 393 data = state.genstat;
philpem@40 394 handled = true;
philpem@40 395 break;
philpem@40 396 case 0x020000: // Video RAM
philpem@40 397 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 398 data = RD16(state.vram, address, 0x7FFF);
philpem@40 399 handled = true;
philpem@40 400 break;
philpem@40 401 case 0x030000: // Bus Status Register 0
philpem@40 402 data = state.bsr0;
philpem@40 403 handled = true;
philpem@40 404 break;
philpem@40 405 case 0x040000: // Bus Status Register 1
philpem@40 406 data = state.bsr1;
philpem@40 407 handled = true;
philpem@40 408 break;
philpem@40 409 case 0x050000: // Phone status
philpem@40 410 break;
philpem@40 411 case 0x060000: // DMA Count
philpem@55 412 // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
philpem@55 413 // Bit 14 is always unused, so leave it set
philpem@55 414 data = (state.dma_count & 0x3fff) | 0xC000;
philpem@53 415 handled = true;
philpem@40 416 break;
philpem@40 417 case 0x070000: // Line Printer Status Register
philpem@53 418 data = 0x0012; // no parity error, no line printer error, no irqs from FDD or HDD
philpem@53 419 data |= (state.fdc_ctx.irql) ? 0x0008 : 0; // FIXME! HACKHACKHACK! shouldn't peek inside FDC structs like this
philpem@40 420 break;
philpem@40 421 case 0x080000: // Real Time Clock
philpem@40 422 break;
philpem@40 423 case 0x090000: // Phone registers
philpem@40 424 switch (address & 0x0FF000) {
philpem@40 425 case 0x090000: // Handset relay
philpem@40 426 case 0x098000:
philpem@40 427 break;
philpem@40 428 case 0x091000: // Line select 2
philpem@40 429 case 0x099000:
philpem@40 430 break;
philpem@40 431 case 0x092000: // Hook relay 1
philpem@40 432 case 0x09A000:
philpem@40 433 break;
philpem@40 434 case 0x093000: // Hook relay 2
philpem@40 435 case 0x09B000:
philpem@40 436 break;
philpem@40 437 case 0x094000: // Line 1 hold
philpem@40 438 case 0x09C000:
philpem@40 439 break;
philpem@40 440 case 0x095000: // Line 2 hold
philpem@40 441 case 0x09D000:
philpem@40 442 break;
philpem@40 443 case 0x096000: // Line 1 A-lead
philpem@40 444 case 0x09E000:
philpem@40 445 break;
philpem@40 446 case 0x097000: // Line 2 A-lead
philpem@40 447 case 0x09F000:
philpem@40 448 break;
philpem@40 449 }
philpem@40 450 break;
philpem@46 451 case 0x0A0000: // Miscellaneous Control Register -- write only!
philpem@46 452 handled = true;
philpem@40 453 break;
philpem@40 454 case 0x0B0000: // TM/DIALWR
philpem@40 455 break;
philpem@46 456 case 0x0C0000: // Clear Status Register -- write only!
philpem@43 457 handled = true;
philpem@40 458 break;
philpem@40 459 case 0x0D0000: // DMA Address Register
philpem@40 460 break;
philpem@40 461 case 0x0E0000: // Disk Control Register
philpem@40 462 break;
philpem@40 463 case 0x0F0000: // Line Printer Data Register
philpem@40 464 break;
philpem@40 465 }
philpem@40 466 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 467 // I/O register space, zone B
philpem@40 468 switch (address & 0xF00000) {
philpem@40 469 case 0xC00000: // Expansion slots
philpem@40 470 case 0xD00000:
philpem@40 471 switch (address & 0xFC0000) {
philpem@40 472 case 0xC00000: // Expansion slot 0
philpem@40 473 case 0xC40000: // Expansion slot 1
philpem@40 474 case 0xC80000: // Expansion slot 2
philpem@40 475 case 0xCC0000: // Expansion slot 3
philpem@40 476 case 0xD00000: // Expansion slot 4
philpem@40 477 case 0xD40000: // Expansion slot 5
philpem@40 478 case 0xD80000: // Expansion slot 6
philpem@40 479 case 0xDC0000: // Expansion slot 7
philpem@40 480 fprintf(stderr, "NOTE: RD16 from expansion card space, addr=0x%08X\n", address);
philpem@40 481 break;
philpem@40 482 }
philpem@40 483 break;
philpem@40 484 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 485 case 0xF00000:
philpem@40 486 switch (address & 0x070000) {
philpem@40 487 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@40 488 break;
philpem@40 489 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@52 490 data = wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
philpem@53 491 printf("WD279X: rd16 %02X ==> %02X\n", (address >> 1) & 3, data);
philpem@52 492 handled = true;
philpem@40 493 break;
philpem@40 494 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 495 break;
philpem@40 496 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 497 break;
philpem@40 498 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 499 switch (address & 0x077000) {
philpem@40 500 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@44 501 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@40 502 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 503 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@40 504 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@40 505 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@40 506 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@44 507 // All write-only registers... TODO: bus error?
philpem@44 508 handled = true;
philpem@40 509 break;
philpem@40 510 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@40 511 break;
philpem@40 512 }
philpem@40 513 break;
philpem@40 514 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 515 break;
philpem@40 516 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 517 switch (address & 0x07F000) {
philpem@40 518 default:
philpem@40 519 break;
philpem@40 520 }
philpem@40 521 break;
philpem@40 522 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@40 523 break;
philpem@40 524 }
philpem@40 525 }
philpem@40 526 }
philpem@40 527
philpem@46 528 LOG_NOT_HANDLED_R(16);
philpem@40 529 return data;
philpem@40 530 }
philpem@40 531
philpem@40 532 /**
philpem@40 533 * @brief Read M68K memory, 8-bit
philpem@40 534 */
philpem@40 535 uint32_t m68k_read_memory_8(uint32_t address)
philpem@40 536 {
philpem@40 537 uint8_t data = 0xFF;
philpem@40 538 bool handled = false;
philpem@40 539
philpem@40 540 // If ROMLMAP is set, force system to access ROM
philpem@40 541 if (!state.romlmap)
philpem@40 542 address |= 0x800000;
philpem@40 543
philpem@40 544 // Check access permissions
philpem@40 545 ACCESS_CHECK_RD(address, 8);
philpem@40 546
philpem@40 547 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 548 // ROM access
philpem@40 549 data = RD8(state.rom, address, ROM_SIZE - 1);
philpem@40 550 handled = true;
philpem@40 551 } else if (address <= (state.ram_size - 1)) {
philpem@40 552 // RAM access
philpem@40 553 data = RD8(state.ram, mapAddr(address, false), state.ram_size - 1);
philpem@40 554 handled = true;
philpem@40 555 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 556 // I/O register space, zone A
philpem@40 557 switch (address & 0x0F0000) {
philpem@40 558 case 0x000000: // Map RAM access
philpem@40 559 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 560 data = RD8(state.map, address, 0x7FF);
philpem@40 561 handled = true;
philpem@40 562 break;
philpem@40 563 case 0x010000: // General Status Register
philpem@40 564 if ((address & 1) == 0)
philpem@40 565 data = (state.genstat >> 8) & 0xff;
philpem@40 566 else
philpem@40 567 data = (state.genstat) & 0xff;
philpem@40 568 handled = true;
philpem@40 569 break;
philpem@40 570 case 0x020000: // Video RAM
philpem@40 571 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 572 data = RD8(state.vram, address, 0x7FFF);
philpem@40 573 handled = true;
philpem@40 574 break;
philpem@40 575 case 0x030000: // Bus Status Register 0
philpem@40 576 if ((address & 1) == 0)
philpem@40 577 data = (state.bsr0 >> 8) & 0xff;
philpem@40 578 else
philpem@40 579 data = (state.bsr0) & 0xff;
philpem@40 580 handled = true;
philpem@40 581 break;
philpem@40 582 case 0x040000: // Bus Status Register 1
philpem@40 583 if ((address & 1) == 0)
philpem@40 584 data = (state.bsr1 >> 8) & 0xff;
philpem@40 585 else
philpem@40 586 data = (state.bsr1) & 0xff;
philpem@40 587 handled = true;
philpem@40 588 break;
philpem@40 589 case 0x050000: // Phone status
philpem@40 590 break;
philpem@40 591 case 0x060000: // DMA Count
philpem@53 592 // TODO: how to handle this in 8bit mode?
philpem@40 593 break;
philpem@40 594 case 0x070000: // Line Printer Status Register
philpem@53 595 printf("\tLPSR RD8 fdc irql=%d, irqe=%d\n", state.fdc_ctx.irql, state.fdc_ctx.irqe);
philpem@53 596 if (address & 1) {
philpem@53 597 data = 0x12; // no parity error, no line printer error, no irqs from FDD or HDD
philpem@53 598 data |= (state.fdc_ctx.irql) ? 0x08 : 0; // FIXME! HACKHACKHACK! shouldn't peek inside FDC structs like this
philpem@56 599 data |= 0x04; // HDD interrupt, i.e. command complete -- HACKHACKHACK!
philpem@53 600 } else {
philpem@53 601 data = 0;
philpem@53 602 }
philpem@40 603 break;
philpem@40 604 case 0x080000: // Real Time Clock
philpem@40 605 break;
philpem@40 606 case 0x090000: // Phone registers
philpem@40 607 switch (address & 0x0FF000) {
philpem@40 608 case 0x090000: // Handset relay
philpem@40 609 case 0x098000:
philpem@40 610 break;
philpem@40 611 case 0x091000: // Line select 2
philpem@40 612 case 0x099000:
philpem@40 613 break;
philpem@40 614 case 0x092000: // Hook relay 1
philpem@40 615 case 0x09A000:
philpem@40 616 break;
philpem@40 617 case 0x093000: // Hook relay 2
philpem@40 618 case 0x09B000:
philpem@40 619 break;
philpem@40 620 case 0x094000: // Line 1 hold
philpem@40 621 case 0x09C000:
philpem@40 622 break;
philpem@40 623 case 0x095000: // Line 2 hold
philpem@40 624 case 0x09D000:
philpem@40 625 break;
philpem@40 626 case 0x096000: // Line 1 A-lead
philpem@40 627 case 0x09E000:
philpem@40 628 break;
philpem@40 629 case 0x097000: // Line 2 A-lead
philpem@40 630 case 0x09F000:
philpem@40 631 break;
philpem@40 632 }
philpem@40 633 break;
philpem@46 634 case 0x0A0000: // Miscellaneous Control Register -- write only!
philpem@46 635 handled = true;
philpem@40 636 break;
philpem@40 637 case 0x0B0000: // TM/DIALWR
philpem@40 638 break;
philpem@46 639 case 0x0C0000: // Clear Status Register -- write only!
philpem@43 640 handled = true;
philpem@40 641 break;
philpem@40 642 case 0x0D0000: // DMA Address Register
philpem@40 643 break;
philpem@40 644 case 0x0E0000: // Disk Control Register
philpem@40 645 break;
philpem@40 646 case 0x0F0000: // Line Printer Data Register
philpem@40 647 break;
philpem@40 648 }
philpem@40 649 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 650 // I/O register space, zone B
philpem@40 651 switch (address & 0xF00000) {
philpem@40 652 case 0xC00000: // Expansion slots
philpem@40 653 case 0xD00000:
philpem@40 654 switch (address & 0xFC0000) {
philpem@40 655 case 0xC00000: // Expansion slot 0
philpem@40 656 case 0xC40000: // Expansion slot 1
philpem@40 657 case 0xC80000: // Expansion slot 2
philpem@40 658 case 0xCC0000: // Expansion slot 3
philpem@40 659 case 0xD00000: // Expansion slot 4
philpem@40 660 case 0xD40000: // Expansion slot 5
philpem@40 661 case 0xD80000: // Expansion slot 6
philpem@40 662 case 0xDC0000: // Expansion slot 7
philpem@40 663 fprintf(stderr, "NOTE: RD8 from expansion card space, addr=0x%08X\n", address);
philpem@40 664 break;
philpem@40 665 }
philpem@40 666 break;
philpem@40 667 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 668 case 0xF00000:
philpem@40 669 switch (address & 0x070000) {
philpem@40 670 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@40 671 break;
philpem@40 672 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@52 673 data = wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
philpem@53 674 printf("WD279X: rd8 %02X ==> %02X\n", (address >> 1) & 3, data);
philpem@52 675 handled = true;
philpem@40 676 break;
philpem@40 677 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 678 break;
philpem@40 679 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 680 break;
philpem@40 681 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 682 switch (address & 0x077000) {
philpem@40 683 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@44 684 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@40 685 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 686 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@40 687 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@40 688 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@40 689 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@44 690 // All write-only registers... TODO: bus error?
philpem@44 691 handled = true;
philpem@40 692 break;
philpem@40 693 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@40 694 break;
philpem@40 695 }
philpem@40 696 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 697 break;
philpem@40 698 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 699 switch (address & 0x07F000) {
philpem@40 700 default:
philpem@40 701 break;
philpem@40 702 }
philpem@40 703 break;
philpem@40 704 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@40 705 break;
philpem@40 706 }
philpem@40 707 }
philpem@40 708 }
philpem@40 709
philpem@40 710 LOG_NOT_HANDLED_R(8);
philpem@40 711
philpem@40 712 return data;
philpem@40 713 }
philpem@40 714
philpem@40 715 /**
philpem@40 716 * @brief Write M68K memory, 32-bit
philpem@40 717 */
philpem@40 718 void m68k_write_memory_32(uint32_t address, uint32_t value)
philpem@40 719 {
philpem@40 720 bool handled = false;
philpem@40 721
philpem@40 722 // If ROMLMAP is set, force system to access ROM
philpem@40 723 if (!state.romlmap)
philpem@40 724 address |= 0x800000;
philpem@40 725
philpem@40 726 // Check access permissions
philpem@40 727 ACCESS_CHECK_WR(address, 32);
philpem@40 728
philpem@40 729 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 730 // ROM access
philpem@40 731 handled = true;
philpem@40 732 } else if (address <= (state.ram_size - 1)) {
philpem@40 733 // RAM access
philpem@40 734 WR32(state.ram, mapAddr(address, false), state.ram_size - 1, value);
philpem@40 735 handled = true;
philpem@40 736 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 737 // I/O register space, zone A
philpem@40 738 switch (address & 0x0F0000) {
philpem@40 739 case 0x000000: // Map RAM access
philpem@40 740 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
philpem@40 741 WR32(state.map, address, 0x7FF, value);
philpem@40 742 handled = true;
philpem@40 743 break;
philpem@40 744 case 0x010000: // General Status Register
philpem@40 745 state.genstat = (value & 0xffff);
philpem@40 746 handled = true;
philpem@40 747 break;
philpem@40 748 case 0x020000: // Video RAM
philpem@40 749 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
philpem@40 750 WR32(state.vram, address, 0x7FFF, value);
philpem@40 751 handled = true;
philpem@40 752 break;
philpem@40 753 case 0x030000: // Bus Status Register 0
philpem@40 754 break;
philpem@40 755 case 0x040000: // Bus Status Register 1
philpem@40 756 break;
philpem@40 757 case 0x050000: // Phone status
philpem@40 758 break;
philpem@40 759 case 0x060000: // DMA Count
philpem@53 760 printf("WR32 dmacount %08X\n", value);
philpem@53 761 state.dma_count = (value & 0x3FFF);
philpem@53 762 state.idmarw = ((value & 0x4000) == 0x4000);
philpem@53 763 state.dmaen = ((value & 0x8000) == 0x8000);
philpem@53 764 printf("\tcount %04X, idmarw %d, dmaen %d\n", state.dma_count, state.idmarw, state.dmaen);
philpem@55 765 // This handles the "dummy DMA transfer" mentioned in the docs
philpem@55 766 // TODO: access check, peripheral access
philpem@55 767 if (!state.idmarw)
philpem@55 768 WR32(state.ram, mapAddr(address, false), state.ram_size - 1, 0xDEAD);
philpem@55 769 state.dma_count++;
philpem@53 770 handled = true;
philpem@40 771 break;
philpem@40 772 case 0x070000: // Line Printer Status Register
philpem@40 773 break;
philpem@40 774 case 0x080000: // Real Time Clock
philpem@40 775 break;
philpem@40 776 case 0x090000: // Phone registers
philpem@40 777 switch (address & 0x0FF000) {
philpem@40 778 case 0x090000: // Handset relay
philpem@40 779 case 0x098000:
philpem@40 780 break;
philpem@40 781 case 0x091000: // Line select 2
philpem@40 782 case 0x099000:
philpem@40 783 break;
philpem@40 784 case 0x092000: // Hook relay 1
philpem@40 785 case 0x09A000:
philpem@40 786 break;
philpem@40 787 case 0x093000: // Hook relay 2
philpem@40 788 case 0x09B000:
philpem@40 789 break;
philpem@40 790 case 0x094000: // Line 1 hold
philpem@40 791 case 0x09C000:
philpem@40 792 break;
philpem@40 793 case 0x095000: // Line 2 hold
philpem@40 794 case 0x09D000:
philpem@40 795 break;
philpem@40 796 case 0x096000: // Line 1 A-lead
philpem@40 797 case 0x09E000:
philpem@40 798 break;
philpem@40 799 case 0x097000: // Line 2 A-lead
philpem@40 800 case 0x09F000:
philpem@40 801 break;
philpem@40 802 }
philpem@40 803 break;
philpem@40 804 case 0x0A0000: // Miscellaneous Control Register
philpem@46 805 // TODO: handle the ctrl bits properly
philpem@52 806 // TODO: &0x8000 --> dismiss 60hz intr
philpem@52 807 state.dma_reading = (value & 0x4000);
philpem@46 808 state.leds = (~value & 0xF00) >> 8;
philpem@46 809 printf("LEDs: %s %s %s %s\n",
philpem@46 810 (state.leds & 8) ? "R" : "-",
philpem@46 811 (state.leds & 4) ? "G" : "-",
philpem@46 812 (state.leds & 2) ? "Y" : "-",
philpem@46 813 (state.leds & 1) ? "R" : "-");
philpem@46 814 handled = true;
philpem@40 815 break;
philpem@40 816 case 0x0B0000: // TM/DIALWR
philpem@40 817 break;
philpem@43 818 case 0x0C0000: // Clear Status Register
philpem@43 819 state.genstat = 0xFFFF;
philpem@43 820 state.bsr0 = 0xFFFF;
philpem@43 821 state.bsr1 = 0xFFFF;
philpem@43 822 handled = true;
philpem@40 823 break;
philpem@40 824 case 0x0D0000: // DMA Address Register
philpem@52 825 if (address & 0x004000) {
philpem@52 826 // A14 high -- set most significant bits
philpem@52 827 state.dma_address = (state.dma_address & 0xff) | ((address & 0x3fff) << 7);
philpem@52 828 } else {
philpem@52 829 // A14 low -- set least significant bits
philpem@52 830 state.dma_address = (state.dma_address & 0x3fff00) | (address & 0xff);
philpem@52 831 }
philpem@53 832 printf("WR DMA_ADDR, now %08X\n", state.dma_address);
philpem@53 833 handled = true;
philpem@40 834 break;
philpem@40 835 case 0x0E0000: // Disk Control Register
philpem@52 836 // B7 = FDD controller reset
philpem@52 837 if ((value & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
philpem@52 838 // B6 = drive 0 select -- TODO
philpem@52 839 // B5 = motor enable -- TODO
philpem@52 840 // B4 = HDD controller reset -- TODO
philpem@52 841 // B3 = HDD0 select -- TODO
philpem@52 842 // B2,1,0 = HDD0 head select
philpem@53 843 handled = true;
philpem@40 844 break;
philpem@40 845 case 0x0F0000: // Line Printer Data Register
philpem@40 846 break;
philpem@40 847 }
philpem@40 848 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 849 // I/O register space, zone B
philpem@40 850 switch (address & 0xF00000) {
philpem@40 851 case 0xC00000: // Expansion slots
philpem@40 852 case 0xD00000:
philpem@40 853 switch (address & 0xFC0000) {
philpem@40 854 case 0xC00000: // Expansion slot 0
philpem@40 855 case 0xC40000: // Expansion slot 1
philpem@40 856 case 0xC80000: // Expansion slot 2
philpem@40 857 case 0xCC0000: // Expansion slot 3
philpem@40 858 case 0xD00000: // Expansion slot 4
philpem@40 859 case 0xD40000: // Expansion slot 5
philpem@40 860 case 0xD80000: // Expansion slot 6
philpem@40 861 case 0xDC0000: // Expansion slot 7
philpem@40 862 fprintf(stderr, "NOTE: WR32 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
philpem@40 863 handled = true;
philpem@40 864 break;
philpem@40 865 }
philpem@40 866 break;
philpem@40 867 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 868 case 0xF00000:
philpem@40 869 switch (address & 0x070000) {
philpem@40 870 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@40 871 break;
philpem@40 872 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@53 873 printf("WD279X: wr32 %02X ==> %02X\n", (address >> 1) & 3, value);
philpem@52 874 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, value);
philpem@53 875 handled = true;
philpem@40 876 break;
philpem@40 877 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 878 break;
philpem@40 879 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 880 break;
philpem@40 881 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 882 switch (address & 0x077000) {
philpem@40 883 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@40 884 break;
philpem@44 885 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@44 886 state.pie = ((value & 0x8000) == 0x8000);
philpem@44 887 handled = true;
philpem@40 888 break;
philpem@40 889 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 890 break;
philpem@40 891 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@40 892 state.romlmap = ((value & 0x8000) == 0x8000);
philpem@44 893 handled = true;
philpem@40 894 break;
philpem@40 895 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@40 896 break;
philpem@40 897 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@40 898 break;
philpem@40 899 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@40 900 break;
philpem@40 901 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@40 902 break;
philpem@40 903 }
philpem@40 904 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 905 break;
philpem@40 906 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 907 switch (address & 0x07F000) {
philpem@40 908 default:
philpem@40 909 break;
philpem@40 910 }
philpem@40 911 break;
philpem@40 912 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@40 913 break;
philpem@40 914 }
philpem@40 915 }
philpem@40 916 }
philpem@40 917
philpem@40 918 LOG_NOT_HANDLED_W(32);
philpem@40 919 }
philpem@40 920
philpem@40 921 /**
philpem@40 922 * @brief Write M68K memory, 16-bit
philpem@40 923 */
philpem@40 924 void m68k_write_memory_16(uint32_t address, uint32_t value)
philpem@40 925 {
philpem@40 926 bool handled = false;
philpem@40 927
philpem@40 928 // If ROMLMAP is set, force system to access ROM
philpem@40 929 if (!state.romlmap)
philpem@40 930 address |= 0x800000;
philpem@40 931
philpem@40 932 // Check access permissions
philpem@40 933 ACCESS_CHECK_WR(address, 16);
philpem@40 934
philpem@40 935 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 936 // ROM access
philpem@40 937 handled = true;
philpem@40 938 } else if (address <= (state.ram_size - 1)) {
philpem@40 939 // RAM access
philpem@40 940 WR16(state.ram, mapAddr(address, false), state.ram_size - 1, value);
philpem@40 941 handled = true;
philpem@40 942 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 943 // I/O register space, zone A
philpem@40 944 switch (address & 0x0F0000) {
philpem@40 945 case 0x000000: // Map RAM access
philpem@40 946 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 947 WR16(state.map, address, 0x7FF, value);
philpem@40 948 handled = true;
philpem@40 949 break;
philpem@40 950 case 0x010000: // General Status Register (read only)
philpem@40 951 handled = true;
philpem@40 952 break;
philpem@40 953 case 0x020000: // Video RAM
philpem@40 954 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 955 WR16(state.vram, address, 0x7FFF, value);
philpem@40 956 handled = true;
philpem@40 957 break;
philpem@40 958 case 0x030000: // Bus Status Register 0 (read only)
philpem@40 959 handled = true;
philpem@40 960 break;
philpem@40 961 case 0x040000: // Bus Status Register 1 (read only)
philpem@40 962 handled = true;
philpem@40 963 break;
philpem@40 964 case 0x050000: // Phone status
philpem@40 965 break;
philpem@40 966 case 0x060000: // DMA Count
philpem@53 967 printf("WR16 dmacount %08X\n", value);
philpem@53 968 state.dma_count = (value & 0x3FFF);
philpem@53 969 state.idmarw = ((value & 0x4000) == 0x4000);
philpem@53 970 state.dmaen = ((value & 0x8000) == 0x8000);
philpem@53 971 printf("\tcount %04X, idmarw %d, dmaen %d\n", state.dma_count, state.idmarw, state.dmaen);
philpem@55 972 // This handles the "dummy DMA transfer" mentioned in the docs
philpem@55 973 // TODO: access check, peripheral access
philpem@55 974 if (!state.idmarw)
philpem@55 975 WR32(state.ram, mapAddr(address, false), state.ram_size - 1, 0xDEAD);
philpem@55 976 state.dma_count++;
philpem@53 977 handled = true;
philpem@40 978 break;
philpem@40 979 case 0x070000: // Line Printer Status Register
philpem@40 980 break;
philpem@40 981 case 0x080000: // Real Time Clock
philpem@40 982 break;
philpem@40 983 case 0x090000: // Phone registers
philpem@40 984 switch (address & 0x0FF000) {
philpem@40 985 case 0x090000: // Handset relay
philpem@40 986 case 0x098000:
philpem@40 987 break;
philpem@40 988 case 0x091000: // Line select 2
philpem@40 989 case 0x099000:
philpem@40 990 break;
philpem@40 991 case 0x092000: // Hook relay 1
philpem@40 992 case 0x09A000:
philpem@40 993 break;
philpem@40 994 case 0x093000: // Hook relay 2
philpem@40 995 case 0x09B000:
philpem@40 996 break;
philpem@40 997 case 0x094000: // Line 1 hold
philpem@40 998 case 0x09C000:
philpem@40 999 break;
philpem@40 1000 case 0x095000: // Line 2 hold
philpem@40 1001 case 0x09D000:
philpem@40 1002 break;
philpem@40 1003 case 0x096000: // Line 1 A-lead
philpem@40 1004 case 0x09E000:
philpem@40 1005 break;
philpem@40 1006 case 0x097000: // Line 2 A-lead
philpem@40 1007 case 0x09F000:
philpem@40 1008 break;
philpem@40 1009 }
philpem@40 1010 break;
philpem@40 1011 case 0x0A0000: // Miscellaneous Control Register
philpem@46 1012 // TODO: handle the ctrl bits properly
philpem@52 1013 // TODO: &0x8000 --> dismiss 60hz intr
philpem@52 1014 state.dma_reading = (value & 0x4000);
philpem@46 1015 state.leds = (~value & 0xF00) >> 8;
philpem@46 1016 printf("LEDs: %s %s %s %s\n",
philpem@46 1017 (state.leds & 8) ? "R" : "-",
philpem@46 1018 (state.leds & 4) ? "G" : "-",
philpem@46 1019 (state.leds & 2) ? "Y" : "-",
philpem@46 1020 (state.leds & 1) ? "R" : "-");
philpem@46 1021 handled = true;
philpem@40 1022 break;
philpem@40 1023 case 0x0B0000: // TM/DIALWR
philpem@40 1024 break;
philpem@43 1025 case 0x0C0000: // Clear Status Register
philpem@43 1026 state.genstat = 0xFFFF;
philpem@43 1027 state.bsr0 = 0xFFFF;
philpem@43 1028 state.bsr1 = 0xFFFF;
philpem@43 1029 handled = true;
philpem@40 1030 break;
philpem@40 1031 case 0x0D0000: // DMA Address Register
philpem@52 1032 if (address & 0x004000) {
philpem@52 1033 // A14 high -- set most significant bits
philpem@52 1034 state.dma_address = (state.dma_address & 0xff) | ((address & 0x3fff) << 7);
philpem@52 1035 } else {
philpem@52 1036 // A14 low -- set least significant bits
philpem@52 1037 state.dma_address = (state.dma_address & 0x3fff00) | (address & 0xff);
philpem@52 1038 }
philpem@53 1039 printf("WR DMA_ADDR, now %08X\n", state.dma_address);
philpem@53 1040 handled = true;
philpem@40 1041 break;
philpem@40 1042 case 0x0E0000: // Disk Control Register
philpem@52 1043 // B7 = FDD controller reset
philpem@52 1044 if ((value & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
philpem@52 1045 // B6 = drive 0 select -- TODO
philpem@52 1046 // B5 = motor enable -- TODO
philpem@52 1047 // B4 = HDD controller reset -- TODO
philpem@52 1048 // B3 = HDD0 select -- TODO
philpem@52 1049 // B2,1,0 = HDD0 head select
philpem@53 1050 handled = true;
philpem@40 1051 break;
philpem@40 1052 case 0x0F0000: // Line Printer Data Register
philpem@40 1053 break;
philpem@40 1054 }
philpem@40 1055 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 1056 // I/O register space, zone B
philpem@40 1057 switch (address & 0xF00000) {
philpem@40 1058 case 0xC00000: // Expansion slots
philpem@40 1059 case 0xD00000:
philpem@40 1060 switch (address & 0xFC0000) {
philpem@40 1061 case 0xC00000: // Expansion slot 0
philpem@40 1062 case 0xC40000: // Expansion slot 1
philpem@40 1063 case 0xC80000: // Expansion slot 2
philpem@40 1064 case 0xCC0000: // Expansion slot 3
philpem@40 1065 case 0xD00000: // Expansion slot 4
philpem@40 1066 case 0xD40000: // Expansion slot 5
philpem@40 1067 case 0xD80000: // Expansion slot 6
philpem@40 1068 case 0xDC0000: // Expansion slot 7
philpem@40 1069 fprintf(stderr, "NOTE: WR16 to expansion card space, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 1070 break;
philpem@40 1071 }
philpem@40 1072 break;
philpem@40 1073 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 1074 case 0xF00000:
philpem@40 1075 switch (address & 0x070000) {
philpem@40 1076 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@40 1077 break;
philpem@40 1078 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@53 1079 printf("WD279X: wr16 %02X ==> %02X\n", (address >> 1) & 3, value);
philpem@52 1080 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, value);
philpem@53 1081 handled = true;
philpem@40 1082 break;
philpem@40 1083 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 1084 break;
philpem@40 1085 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 1086 break;
philpem@40 1087 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 1088 switch (address & 0x077000) {
philpem@40 1089 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@40 1090 break;
philpem@44 1091 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@44 1092 state.pie = ((value & 0x8000) == 0x8000);
philpem@44 1093 handled = true;
philpem@40 1094 break;
philpem@40 1095 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 1096 break;
philpem@40 1097 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@40 1098 state.romlmap = ((value & 0x8000) == 0x8000);
philpem@40 1099 handled = true;
philpem@40 1100 break;
philpem@40 1101 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@40 1102 break;
philpem@40 1103 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@40 1104 break;
philpem@40 1105 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@40 1106 break;
philpem@40 1107 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@40 1108 break;
philpem@40 1109 }
philpem@40 1110 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 1111 break;
philpem@40 1112 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 1113 switch (address & 0x07F000) {
philpem@40 1114 default:
philpem@40 1115 break;
philpem@40 1116 }
philpem@40 1117 break;
philpem@40 1118 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@40 1119 break;
philpem@40 1120 }
philpem@40 1121 }
philpem@40 1122 }
philpem@40 1123
philpem@40 1124 LOG_NOT_HANDLED_W(16);
philpem@40 1125 }
philpem@40 1126
philpem@40 1127 /**
philpem@40 1128 * @brief Write M68K memory, 8-bit
philpem@40 1129 */
philpem@40 1130 void m68k_write_memory_8(uint32_t address, uint32_t value)
philpem@40 1131 {
philpem@40 1132 bool handled = false;
philpem@40 1133
philpem@40 1134 // If ROMLMAP is set, force system to access ROM
philpem@40 1135 if (!state.romlmap)
philpem@40 1136 address |= 0x800000;
philpem@40 1137
philpem@40 1138 // Check access permissions
philpem@40 1139 ACCESS_CHECK_WR(address, 8);
philpem@40 1140
philpem@40 1141 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 1142 // ROM access (read only!)
philpem@40 1143 handled = true;
philpem@40 1144 } else if (address <= (state.ram_size - 1)) {
philpem@40 1145 // RAM access
philpem@40 1146 WR8(state.ram, mapAddr(address, false), state.ram_size - 1, value);
philpem@40 1147 handled = true;
philpem@40 1148 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 1149 // I/O register space, zone A
philpem@40 1150 switch (address & 0x0F0000) {
philpem@40 1151 case 0x000000: // Map RAM access
philpem@40 1152 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=%08X, data=%02X\n", address, value);
philpem@40 1153 WR8(state.map, address, 0x7FF, value);
philpem@40 1154 handled = true;
philpem@40 1155 break;
philpem@40 1156 case 0x010000: // General Status Register
philpem@40 1157 handled = true;
philpem@40 1158 break;
philpem@40 1159 case 0x020000: // Video RAM
philpem@46 1160 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=%08X, data=0x%02X\n", address, value);
philpem@40 1161 WR8(state.vram, address, 0x7FFF, value);
philpem@40 1162 handled = true;
philpem@40 1163 break;
philpem@40 1164 case 0x030000: // Bus Status Register 0
philpem@40 1165 handled = true;
philpem@40 1166 break;
philpem@40 1167 case 0x040000: // Bus Status Register 1
philpem@40 1168 handled = true;
philpem@40 1169 break;
philpem@40 1170 case 0x050000: // Phone status
philpem@40 1171 break;
philpem@40 1172 case 0x060000: // DMA Count
philpem@53 1173 // TODO: how to handle this in 8bit mode?
philpem@40 1174 break;
philpem@40 1175 case 0x070000: // Line Printer Status Register
philpem@40 1176 break;
philpem@40 1177 case 0x080000: // Real Time Clock
philpem@40 1178 break;
philpem@40 1179 case 0x090000: // Phone registers
philpem@40 1180 switch (address & 0x0FF000) {
philpem@40 1181 case 0x090000: // Handset relay
philpem@40 1182 case 0x098000:
philpem@40 1183 break;
philpem@40 1184 case 0x091000: // Line select 2
philpem@40 1185 case 0x099000:
philpem@40 1186 break;
philpem@40 1187 case 0x092000: // Hook relay 1
philpem@40 1188 case 0x09A000:
philpem@40 1189 break;
philpem@40 1190 case 0x093000: // Hook relay 2
philpem@40 1191 case 0x09B000:
philpem@40 1192 break;
philpem@40 1193 case 0x094000: // Line 1 hold
philpem@40 1194 case 0x09C000:
philpem@40 1195 break;
philpem@40 1196 case 0x095000: // Line 2 hold
philpem@40 1197 case 0x09D000:
philpem@40 1198 break;
philpem@40 1199 case 0x096000: // Line 1 A-lead
philpem@40 1200 case 0x09E000:
philpem@40 1201 break;
philpem@40 1202 case 0x097000: // Line 2 A-lead
philpem@40 1203 case 0x09F000:
philpem@40 1204 break;
philpem@40 1205 }
philpem@40 1206 break;
philpem@40 1207 case 0x0A0000: // Miscellaneous Control Register
philpem@53 1208 // TODO: how to handle this in 8bit mode?
philpem@53 1209 /*
philpem@46 1210 // TODO: handle the ctrl bits properly
philpem@52 1211 if ((address & 1) == 0) {
philpem@52 1212 // low byte
philpem@52 1213 } else {
philpem@52 1214 // hight byte
philpem@52 1215 // TODO: &0x8000 --> dismiss 60hz intr
philpem@52 1216 state.dma_reading = (value & 0x40);
philpem@46 1217 state.leds = (~value & 0xF);
philpem@52 1218 }
philpem@46 1219 printf("LEDs: %s %s %s %s\n",
philpem@46 1220 (state.leds & 8) ? "R" : "-",
philpem@46 1221 (state.leds & 4) ? "G" : "-",
philpem@46 1222 (state.leds & 2) ? "Y" : "-",
philpem@46 1223 (state.leds & 1) ? "R" : "-");
philpem@46 1224 handled = true;
philpem@53 1225 */
philpem@40 1226 break;
philpem@40 1227 case 0x0B0000: // TM/DIALWR
philpem@40 1228 break;
philpem@43 1229 case 0x0C0000: // Clear Status Register
philpem@43 1230 state.genstat = 0xFFFF;
philpem@43 1231 state.bsr0 = 0xFFFF;
philpem@43 1232 state.bsr1 = 0xFFFF;
philpem@43 1233 handled = true;
philpem@40 1234 break;
philpem@40 1235 case 0x0D0000: // DMA Address Register
philpem@52 1236 if (address & 0x004000) {
philpem@52 1237 // A14 high -- set most significant bits
philpem@52 1238 state.dma_address = (state.dma_address & 0xff) | ((address & 0x3fff) << 7);
philpem@52 1239 } else {
philpem@52 1240 // A14 low -- set least significant bits
philpem@52 1241 state.dma_address = (state.dma_address & 0x3fff00) | (address & 0xff);
philpem@52 1242 }
philpem@53 1243 printf("WR DMA_ADDR, now %08X\n", state.dma_address);
philpem@53 1244 handled = true;
philpem@40 1245 break;
philpem@40 1246 case 0x0E0000: // Disk Control Register
philpem@52 1247 // B7 = FDD controller reset
philpem@52 1248 if ((value & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
philpem@52 1249 // B6 = drive 0 select -- TODO
philpem@52 1250 // B5 = motor enable -- TODO
philpem@52 1251 // B4 = HDD controller reset -- TODO
philpem@52 1252 // B3 = HDD0 select -- TODO
philpem@52 1253 // B2,1,0 = HDD0 head select
philpem@53 1254 handled = true;
philpem@40 1255 break;
philpem@40 1256 case 0x0F0000: // Line Printer Data Register
philpem@40 1257 break;
philpem@40 1258 }
philpem@40 1259 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 1260 // I/O register space, zone B
philpem@40 1261 switch (address & 0xF00000) {
philpem@40 1262 case 0xC00000: // Expansion slots
philpem@40 1263 case 0xD00000:
philpem@40 1264 switch (address & 0xFC0000) {
philpem@40 1265 case 0xC00000: // Expansion slot 0
philpem@40 1266 case 0xC40000: // Expansion slot 1
philpem@40 1267 case 0xC80000: // Expansion slot 2
philpem@40 1268 case 0xCC0000: // Expansion slot 3
philpem@40 1269 case 0xD00000: // Expansion slot 4
philpem@40 1270 case 0xD40000: // Expansion slot 5
philpem@40 1271 case 0xD80000: // Expansion slot 6
philpem@40 1272 case 0xDC0000: // Expansion slot 7
philpem@40 1273 fprintf(stderr, "NOTE: WR8 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
philpem@40 1274 break;
philpem@40 1275 }
philpem@40 1276 break;
philpem@40 1277 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 1278 case 0xF00000:
philpem@40 1279 switch (address & 0x070000) {
philpem@40 1280 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@40 1281 break;
philpem@40 1282 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@53 1283 printf("WD279X: wr8 %02X ==> %02X\n", (address >> 1) & 3, value);
philpem@52 1284 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, value);
philpem@53 1285 handled = true;
philpem@40 1286 break;
philpem@40 1287 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 1288 break;
philpem@40 1289 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 1290 break;
philpem@40 1291 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 1292 switch (address & 0x077000) {
philpem@40 1293 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@40 1294 break;
philpem@44 1295 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@44 1296 if ((address & 1) == 0)
philpem@44 1297 state.pie = ((value & 0x80) == 0x80);
philpem@44 1298 handled = true;
philpem@40 1299 break;
philpem@40 1300 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 1301 break;
philpem@40 1302 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@40 1303 if ((address & 1) == 0)
philpem@40 1304 state.romlmap = ((value & 0x80) == 0x80);
philpem@40 1305 handled = true;
philpem@40 1306 break;
philpem@40 1307 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@40 1308 break;
philpem@40 1309 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@40 1310 break;
philpem@40 1311 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@40 1312 break;
philpem@40 1313 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@40 1314 break;
philpem@40 1315 }
philpem@40 1316 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 1317 break;
philpem@40 1318 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 1319 switch (address & 0x07F000) {
philpem@40 1320 default:
philpem@40 1321 break;
philpem@40 1322 }
philpem@40 1323 break;
philpem@40 1324 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@40 1325 break;
philpem@40 1326 default:
philpem@40 1327 fprintf(stderr, "NOTE: WR8 to undefined E/F-block space, addr=0x%08X, data=0x%08X\n", address, value);
philpem@40 1328 break;
philpem@40 1329 }
philpem@40 1330 }
philpem@40 1331 }
philpem@40 1332
philpem@40 1333 LOG_NOT_HANDLED_W(8);
philpem@40 1334 }
philpem@40 1335
philpem@40 1336
philpem@40 1337 // for the disassembler
philpem@40 1338 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
philpem@40 1339 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
philpem@40 1340 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }
philpem@40 1341
philpem@40 1342