src/memory.c

Fri, 04 Mar 2011 00:44:36 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Fri, 04 Mar 2011 00:44:36 +0000
changeset 103
b749a3356e8d
parent 102
4e1c29899aca
child 104
b12651d8a0ab
permissions
-rw-r--r--

more verbose bus error logging

philpem@40 1 #include <stdio.h>
philpem@40 2 #include <stdlib.h>
philpem@40 3 #include <stdint.h>
philpem@40 4 #include <stdbool.h>
philpem@59 5 #include <assert.h>
philpem@40 6 #include "musashi/m68k.h"
philpem@40 7 #include "state.h"
philpem@100 8 #include "utils.h"
philpem@40 9 #include "memory.h"
philpem@40 10
philpem@40 11 /******************
philpem@40 12 * Memory mapping
philpem@40 13 ******************/
philpem@40 14
philpem@40 15 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
philpem@40 16
philpem@59 17 uint32_t mapAddr(uint32_t addr, bool writing)/*{{{*/
philpem@40 18 {
philpem@40 19 if (addr < 0x400000) {
philpem@40 20 // RAM access. Check against the Map RAM
philpem@40 21 // Start by getting the original page address
philpem@40 22 uint16_t page = (addr >> 12) & 0x3FF;
philpem@40 23
philpem@40 24 // Look it up in the map RAM and get the physical page address
philpem@40 25 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@40 26
philpem@40 27 // Update the Page Status bits
philpem@40 28 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
philpem@100 29 // Pagebits --
philpem@100 30 // 0 = not present
philpem@100 31 // 1 = present but not accessed
philpem@100 32 // 2 = present, accessed (read from)
philpem@100 33 // 3 = present, dirty (written to)
philpem@100 34 switch (pagebits) {
philpem@100 35 case 0:
philpem@100 36 // Page not present
philpem@100 37 // This should cause a page fault
philpem@100 38 LOGS("Whoa! Pagebit update, when the page is not present!");
philpem@100 39 break;
philpem@100 40
philpem@100 41 case 1:
philpem@100 42 // Page present -- first access
philpem@100 43 state.map[page*2] &= 0x1F; // turn off "present" bit
philpem@100 44 if (writing)
philpem@100 45 state.map[page*2] |= 0x60; // Page written to (dirty)
philpem@100 46 else
philpem@100 47 state.map[page*2] |= 0x40; // Page accessed but not written
philpem@100 48 break;
philpem@100 49
philpem@100 50 case 2:
philpem@100 51 case 3:
philpem@100 52 // Page present, 2nd or later access
philpem@100 53 if (writing)
philpem@100 54 state.map[page*2] |= 0x60; // Page written to (dirty)
philpem@100 55 break;
philpem@40 56 }
philpem@40 57
philpem@40 58 // Return the address with the new physical page spliced in
philpem@40 59 return (new_page_addr << 12) + (addr & 0xFFF);
philpem@40 60 } else {
philpem@40 61 // I/O, VRAM or MapRAM space; no mapping is performed or required
philpem@40 62 // TODO: assert here?
philpem@40 63 return addr;
philpem@40 64 }
philpem@59 65 }/*}}}*/
philpem@40 66
philpem@59 67 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)/*{{{*/
philpem@40 68 {
philpem@40 69 // Are we in Supervisor mode?
philpem@40 70 if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
philpem@40 71 // Yes. We can do anything we like.
philpem@40 72 return MEM_ALLOWED;
philpem@40 73
philpem@40 74 // If we're here, then we must be in User mode.
philpem@40 75 // Check that the user didn't access memory outside of the RAM area
philpem@40 76 if (addr >= 0x400000)
philpem@40 77 return MEM_UIE;
philpem@40 78
philpem@40 79 // This leaves us with Page Fault checking. Get the page bits for this page.
philpem@40 80 uint16_t page = (addr >> 12) & 0x3FF;
philpem@40 81 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
philpem@40 82
philpem@40 83 // Check page is present
philpem@40 84 if ((pagebits & 0x03) == 0)
philpem@40 85 return MEM_PAGEFAULT;
philpem@40 86
philpem@40 87 // User attempt to access the kernel
philpem@40 88 // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
philpem@40 89 if (((addr >> 19) & 0x0F) == 0)
philpem@40 90 return MEM_KERNEL;
philpem@40 91
philpem@40 92 // Check page is write enabled
philpem@68 93 if (writing && ((pagebits & 0x04) == 0))
philpem@40 94 return MEM_PAGE_NO_WE;
philpem@40 95
philpem@40 96 // Page access allowed.
philpem@40 97 return MEM_ALLOWED;
philpem@59 98 }/*}}}*/
philpem@40 99
philpem@40 100 #undef MAPRAM
philpem@40 101
philpem@40 102
philpem@40 103 /********************************************************
philpem@40 104 * m68k memory read/write support functions for Musashi
philpem@40 105 ********************************************************/
philpem@40 106
philpem@40 107 /**
philpem@40 108 * @brief Check memory access permissions for a write operation.
philpem@40 109 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
philpem@40 110 * gcc throws warnings when you have a return-with-value in a void
philpem@40 111 * function, even if the return-with-value is completely unreachable.
philpem@40 112 * Similarly it doesn't like it if you have a return without a value
philpem@40 113 * in a non-void function, even if it's impossible to ever reach the
philpem@40 114 * return-with-no-value. UGH!
philpem@40 115 */
philpem@59 116 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
philpem@59 117 #define ACCESS_CHECK_WR(address, bits) \
philpem@59 118 do { \
philpem@40 119 bool fault = false; \
philpem@103 120 MEM_STATUS st; \
philpem@103 121 switch (st = checkMemoryAccess(address, true)) { \
philpem@40 122 case MEM_ALLOWED: \
philpem@40 123 /* Access allowed */ \
philpem@40 124 break; \
philpem@40 125 case MEM_PAGEFAULT: \
philpem@40 126 /* Page fault */ \
philpem@44 127 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0); \
philpem@40 128 fault = true; \
philpem@40 129 break; \
philpem@40 130 case MEM_UIE: \
philpem@40 131 /* User access to memory above 4MB */ \
philpem@44 132 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0); \
philpem@40 133 fault = true; \
philpem@40 134 break; \
philpem@40 135 case MEM_KERNEL: \
philpem@40 136 case MEM_PAGE_NO_WE: \
philpem@40 137 /* kernel access or page not write enabled */ \
philpem@68 138 /* FIXME: which regs need setting? */ \
philpem@40 139 fault = true; \
philpem@40 140 break; \
philpem@40 141 } \
philpem@40 142 \
philpem@40 143 if (fault) { \
philpem@40 144 if (bits >= 16) \
philpem@68 145 state.bsr0 = 0x7C00; \
philpem@40 146 else \
philpem@40 147 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
philpem@40 148 state.bsr0 |= (address >> 16); \
philpem@40 149 state.bsr1 = address & 0xffff; \
philpem@103 150 LOG("Bus Error while writing, addr %08X, statcode %d", address, st); \
philpem@103 151 if (state.ee) m68k_pulse_bus_error(); \
philpem@40 152 return; \
philpem@40 153 } \
philpem@70 154 } while (0)
philpem@59 155 /*}}}*/
philpem@40 156
philpem@40 157 /**
philpem@40 158 * @brief Check memory access permissions for a read operation.
philpem@40 159 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
philpem@40 160 * gcc throws warnings when you have a return-with-value in a void
philpem@40 161 * function, even if the return-with-value is completely unreachable.
philpem@40 162 * Similarly it doesn't like it if you have a return without a value
philpem@40 163 * in a non-void function, even if it's impossible to ever reach the
philpem@40 164 * return-with-no-value. UGH!
philpem@40 165 */
philpem@59 166 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
philpem@59 167 #define ACCESS_CHECK_RD(address, bits) \
philpem@59 168 do { \
philpem@40 169 bool fault = false; \
philpem@103 170 MEM_STATUS st; \
philpem@103 171 switch (st = checkMemoryAccess(address, false)) { \
philpem@40 172 case MEM_ALLOWED: \
philpem@40 173 /* Access allowed */ \
philpem@40 174 break; \
philpem@40 175 case MEM_PAGEFAULT: \
philpem@40 176 /* Page fault */ \
philpem@44 177 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0); \
philpem@40 178 fault = true; \
philpem@40 179 break; \
philpem@40 180 case MEM_UIE: \
philpem@40 181 /* User access to memory above 4MB */ \
philpem@44 182 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0); \
philpem@40 183 fault = true; \
philpem@40 184 break; \
philpem@40 185 case MEM_KERNEL: \
philpem@40 186 case MEM_PAGE_NO_WE: \
philpem@40 187 /* kernel access or page not write enabled */ \
philpem@68 188 /* FIXME: which regs need setting? */ \
philpem@40 189 fault = true; \
philpem@40 190 break; \
philpem@40 191 } \
philpem@40 192 \
philpem@40 193 if (fault) { \
philpem@40 194 if (bits >= 16) \
philpem@68 195 state.bsr0 = 0x7C00; \
philpem@40 196 else \
philpem@40 197 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
philpem@40 198 state.bsr0 |= (address >> 16); \
philpem@40 199 state.bsr1 = address & 0xffff; \
philpem@103 200 LOG("Bus Error while reading, addr %08X, statcode %d", address, st); \
philpem@103 201 if (state.ee) m68k_pulse_bus_error(); \
philpem@40 202 return 0xFFFFFFFF; \
philpem@40 203 } \
philpem@70 204 } while (0)
philpem@59 205 /*}}}*/
philpem@40 206
philpem@40 207 // Logging macros
philpem@59 208 #define LOG_NOT_HANDLED_R(bits) \
philpem@64 209 if (!handled) printf("unhandled read%02d, addr=0x%08X\n", bits, address);
philpem@40 210
philpem@59 211 #define LOG_NOT_HANDLED_W(bits) \
philpem@64 212 if (!handled) printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
philpem@59 213
philpem@59 214 /********************************************************
philpem@59 215 * I/O read/write functions
philpem@59 216 ********************************************************/
philpem@40 217
philpem@40 218 /**
philpem@59 219 * Issue a warning if a read operation is made with an invalid size
philpem@40 220 */
philpem@66 221 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
philpem@40 222 {
philpem@59 223 assert((bits == 8) || (bits == 16) || (bits == 32));
philpem@59 224 if ((bits & allowed) == 0) {
philpem@66 225 printf("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
philpem@59 226 }
philpem@59 227 }
philpem@59 228
philpem@66 229 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
philpem@40 230 {
philpem@66 231 ENFORCE_SIZE(bits, address, true, allowed, regname);
philpem@66 232 }
philpem@66 233
philpem@66 234 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
philpem@66 235 {
philpem@66 236 ENFORCE_SIZE(bits, address, false, allowed, regname);
philpem@66 237 }
philpem@66 238
philpem@59 239 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
philpem@59 240 {
philpem@40 241 bool handled = false;
philpem@40 242
philpem@59 243 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 244 // I/O register space, zone A
philpem@40 245 switch (address & 0x0F0000) {
philpem@40 246 case 0x010000: // General Status Register
philpem@59 247 if (bits == 16)
philpem@59 248 state.genstat = (data & 0xffff);
philpem@59 249 else if (bits == 8) {
philpem@59 250 if (address & 0)
philpem@59 251 state.genstat = data;
philpem@59 252 else
philpem@59 253 state.genstat = data << 8;
philpem@59 254 }
philpem@40 255 handled = true;
philpem@40 256 break;
philpem@40 257 case 0x030000: // Bus Status Register 0
philpem@40 258 break;
philpem@40 259 case 0x040000: // Bus Status Register 1
philpem@40 260 break;
philpem@40 261 case 0x050000: // Phone status
philpem@40 262 break;
philpem@40 263 case 0x060000: // DMA Count
philpem@66 264 ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
philpem@59 265 state.dma_count = (data & 0x3FFF);
philpem@59 266 state.idmarw = ((data & 0x4000) == 0x4000);
philpem@59 267 state.dmaen = ((data & 0x8000) == 0x8000);
philpem@59 268 // This handles the "dummy DMA transfer" mentioned in the docs
philpem@59 269 // TODO: access check, peripheral access
philpem@59 270 if (!state.idmarw)
philpem@60 271 WR32(state.base_ram, mapAddr(address, true), state.base_ram_size - 1, 0xDEAD);
philpem@59 272 state.dma_count++;
philpem@53 273 handled = true;
philpem@40 274 break;
philpem@40 275 case 0x070000: // Line Printer Status Register
philpem@40 276 break;
philpem@40 277 case 0x080000: // Real Time Clock
philpem@40 278 break;
philpem@40 279 case 0x090000: // Phone registers
philpem@40 280 switch (address & 0x0FF000) {
philpem@40 281 case 0x090000: // Handset relay
philpem@40 282 case 0x098000:
philpem@40 283 break;
philpem@40 284 case 0x091000: // Line select 2
philpem@40 285 case 0x099000:
philpem@40 286 break;
philpem@40 287 case 0x092000: // Hook relay 1
philpem@40 288 case 0x09A000:
philpem@40 289 break;
philpem@40 290 case 0x093000: // Hook relay 2
philpem@40 291 case 0x09B000:
philpem@40 292 break;
philpem@40 293 case 0x094000: // Line 1 hold
philpem@40 294 case 0x09C000:
philpem@40 295 break;
philpem@40 296 case 0x095000: // Line 2 hold
philpem@40 297 case 0x09D000:
philpem@40 298 break;
philpem@40 299 case 0x096000: // Line 1 A-lead
philpem@40 300 case 0x09E000:
philpem@40 301 break;
philpem@40 302 case 0x097000: // Line 2 A-lead
philpem@40 303 case 0x09F000:
philpem@40 304 break;
philpem@40 305 }
philpem@40 306 break;
philpem@59 307 case 0x0A0000: // Miscellaneous Control Register
philpem@66 308 ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
philpem@59 309 // TODO: handle the ctrl bits properly
philpem@59 310 // TODO: &0x8000 --> dismiss 60hz intr
philpem@97 311 if (data & 0x8000){
philpem@97 312 state.timer_enabled = 1;
philpem@97 313 }else{
philpem@97 314 state.timer_enabled = 0;
philpem@97 315 state.timer_asserted = 0;
philpem@97 316 }
philpem@59 317 state.dma_reading = (data & 0x4000);
philpem@72 318 if (state.leds != ((~data & 0xF00) >> 8)) {
philpem@72 319 state.leds = (~data & 0xF00) >> 8;
philpem@72 320 printf("LEDs: %s %s %s %s\n",
philpem@72 321 (state.leds & 8) ? "R" : "-",
philpem@72 322 (state.leds & 4) ? "G" : "-",
philpem@72 323 (state.leds & 2) ? "Y" : "-",
philpem@72 324 (state.leds & 1) ? "R" : "-");
philpem@72 325 }
philpem@46 326 handled = true;
philpem@40 327 break;
philpem@40 328 case 0x0B0000: // TM/DIALWR
philpem@40 329 break;
philpem@59 330 case 0x0C0000: // Clear Status Register
philpem@59 331 state.genstat = 0xFFFF;
philpem@59 332 state.bsr0 = 0xFFFF;
philpem@59 333 state.bsr1 = 0xFFFF;
philpem@43 334 handled = true;
philpem@40 335 break;
philpem@40 336 case 0x0D0000: // DMA Address Register
philpem@59 337 if (address & 0x004000) {
philpem@59 338 // A14 high -- set most significant bits
philpem@59 339 state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
philpem@59 340 } else {
philpem@59 341 // A14 low -- set least significant bits
philpem@59 342 state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
philpem@59 343 }
philpem@59 344 handled = true;
philpem@40 345 break;
philpem@40 346 case 0x0E0000: // Disk Control Register
philpem@66 347 ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
philpem@59 348 // B7 = FDD controller reset
philpem@59 349 if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
philpem@59 350 // B6 = drive 0 select -- TODO
philpem@59 351 // B5 = motor enable -- TODO
philpem@59 352 // B4 = HDD controller reset -- TODO
philpem@59 353 // B3 = HDD0 select -- TODO
philpem@59 354 // B2,1,0 = HDD0 head select
philpem@59 355 handled = true;
philpem@40 356 break;
philpem@40 357 case 0x0F0000: // Line Printer Data Register
philpem@40 358 break;
philpem@40 359 }
philpem@40 360 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 361 // I/O register space, zone B
philpem@40 362 switch (address & 0xF00000) {
philpem@40 363 case 0xC00000: // Expansion slots
philpem@40 364 case 0xD00000:
philpem@40 365 switch (address & 0xFC0000) {
philpem@40 366 case 0xC00000: // Expansion slot 0
philpem@40 367 case 0xC40000: // Expansion slot 1
philpem@40 368 case 0xC80000: // Expansion slot 2
philpem@40 369 case 0xCC0000: // Expansion slot 3
philpem@40 370 case 0xD00000: // Expansion slot 4
philpem@40 371 case 0xD40000: // Expansion slot 5
philpem@40 372 case 0xD80000: // Expansion slot 6
philpem@40 373 case 0xDC0000: // Expansion slot 7
philpem@59 374 fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
philpem@59 375 handled = true;
philpem@40 376 break;
philpem@40 377 }
philpem@40 378 break;
philpem@40 379 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 380 case 0xF00000:
philpem@40 381 switch (address & 0x070000) {
philpem@40 382 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@40 383 break;
philpem@40 384 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@66 385 ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");
philpem@59 386 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
philpem@52 387 handled = true;
philpem@40 388 break;
philpem@40 389 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 390 break;
philpem@40 391 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 392 break;
philpem@40 393 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 394 switch (address & 0x077000) {
philpem@40 395 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@102 396 // Error Enable. If =0, Level7 intrs and bus errors are masked.
philpem@102 397 ENFORCE_SIZE_W(bits, address, 16, "EE");
philpem@102 398 state.ee = ((data & 0x8000) == 0x8000);
philpem@102 399 handled = true;
philpem@59 400 break;
philpem@44 401 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@66 402 ENFORCE_SIZE_W(bits, address, 16, "PIE");
philpem@59 403 state.pie = ((data & 0x8000) == 0x8000);
philpem@59 404 handled = true;
philpem@59 405 break;
philpem@40 406 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@59 407 break;
philpem@40 408 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@66 409 ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
philpem@59 410 state.romlmap = ((data & 0x8000) == 0x8000);
philpem@44 411 handled = true;
philpem@40 412 break;
philpem@59 413 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@66 414 ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
philpem@59 415 break;
philpem@59 416 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@66 417 ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
philpem@59 418 break;
philpem@59 419 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@66 420 ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
philpem@59 421 break;
philpem@59 422 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@66 423 ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
philpem@40 424 break;
philpem@40 425 }
philpem@40 426 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 427 break;
philpem@40 428 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 429 switch (address & 0x07F000) {
philpem@40 430 default:
philpem@40 431 break;
philpem@40 432 }
philpem@40 433 break;
philpem@40 434 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@84 435 // TODO: figure out which sizes are valid (probably just 8 and 16)
philpem@84 436 // ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER");
philpem@93 437 if (bits == 8) {
philpem@93 438 printf("KBD WR %02X => %02X\n", (address >> 1) & 3, data);
philpem@93 439 keyboard_write(&state.kbd, (address >> 1) & 3, data);
philpem@93 440 handled = true;
philpem@93 441 } else if (bits == 16) {
philpem@93 442 printf("KBD WR %02X => %04X\n", (address >> 1) & 3, data);
philpem@93 443 keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8);
philpem@93 444 handled = true;
philpem@93 445 }
philpem@40 446 break;
philpem@40 447 }
philpem@40 448 }
philpem@40 449 }
philpem@40 450
philpem@64 451 LOG_NOT_HANDLED_W(bits);
philpem@59 452 }/*}}}*/
philpem@40 453
philpem@59 454 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
philpem@59 455 {
philpem@59 456 bool handled = false;
philpem@59 457 uint32_t data = 0xFFFFFFFF;
philpem@40 458
philpem@59 459 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 460 // I/O register space, zone A
philpem@40 461 switch (address & 0x0F0000) {
philpem@40 462 case 0x010000: // General Status Register
philpem@66 463 ENFORCE_SIZE_R(bits, address, 16, "GENSTAT");
philpem@59 464 return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
philpem@40 465 break;
philpem@40 466 case 0x030000: // Bus Status Register 0
philpem@66 467 ENFORCE_SIZE_R(bits, address, 16, "BSR0");
philpem@59 468 return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
philpem@40 469 break;
philpem@40 470 case 0x040000: // Bus Status Register 1
philpem@66 471 ENFORCE_SIZE_R(bits, address, 16, "BSR1");
philpem@59 472 return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
philpem@40 473 break;
philpem@40 474 case 0x050000: // Phone status
philpem@66 475 ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
philpem@40 476 break;
philpem@40 477 case 0x060000: // DMA Count
philpem@55 478 // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
philpem@55 479 // Bit 14 is always unused, so leave it set
philpem@66 480 ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
philpem@59 481 return (state.dma_count & 0x3fff) | 0xC000;
philpem@40 482 break;
philpem@40 483 case 0x070000: // Line Printer Status Register
philpem@53 484 data = 0x00120012; // no parity error, no line printer error, no irqs from FDD or HDD
philpem@78 485 data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0;
philpem@59 486 return data;
philpem@40 487 break;
philpem@40 488 case 0x080000: // Real Time Clock
philpem@59 489 printf("READ NOTIMP: Realtime Clock\n");
philpem@40 490 break;
philpem@40 491 case 0x090000: // Phone registers
philpem@40 492 switch (address & 0x0FF000) {
philpem@40 493 case 0x090000: // Handset relay
philpem@40 494 case 0x098000:
philpem@40 495 break;
philpem@40 496 case 0x091000: // Line select 2
philpem@40 497 case 0x099000:
philpem@40 498 break;
philpem@40 499 case 0x092000: // Hook relay 1
philpem@40 500 case 0x09A000:
philpem@40 501 break;
philpem@40 502 case 0x093000: // Hook relay 2
philpem@40 503 case 0x09B000:
philpem@40 504 break;
philpem@40 505 case 0x094000: // Line 1 hold
philpem@40 506 case 0x09C000:
philpem@40 507 break;
philpem@40 508 case 0x095000: // Line 2 hold
philpem@40 509 case 0x09D000:
philpem@40 510 break;
philpem@40 511 case 0x096000: // Line 1 A-lead
philpem@40 512 case 0x09E000:
philpem@40 513 break;
philpem@40 514 case 0x097000: // Line 2 A-lead
philpem@40 515 case 0x09F000:
philpem@40 516 break;
philpem@40 517 }
philpem@40 518 break;
philpem@46 519 case 0x0A0000: // Miscellaneous Control Register -- write only!
philpem@46 520 handled = true;
philpem@40 521 break;
philpem@40 522 case 0x0B0000: // TM/DIALWR
philpem@40 523 break;
philpem@46 524 case 0x0C0000: // Clear Status Register -- write only!
philpem@43 525 handled = true;
philpem@40 526 break;
philpem@40 527 case 0x0D0000: // DMA Address Register
philpem@40 528 break;
philpem@40 529 case 0x0E0000: // Disk Control Register
philpem@40 530 break;
philpem@40 531 case 0x0F0000: // Line Printer Data Register
philpem@40 532 break;
philpem@40 533 }
philpem@40 534 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 535 // I/O register space, zone B
philpem@40 536 switch (address & 0xF00000) {
philpem@40 537 case 0xC00000: // Expansion slots
philpem@40 538 case 0xD00000:
philpem@40 539 switch (address & 0xFC0000) {
philpem@40 540 case 0xC00000: // Expansion slot 0
philpem@40 541 case 0xC40000: // Expansion slot 1
philpem@40 542 case 0xC80000: // Expansion slot 2
philpem@40 543 case 0xCC0000: // Expansion slot 3
philpem@40 544 case 0xD00000: // Expansion slot 4
philpem@40 545 case 0xD40000: // Expansion slot 5
philpem@40 546 case 0xD80000: // Expansion slot 6
philpem@40 547 case 0xDC0000: // Expansion slot 7
philpem@65 548 fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
philpem@65 549 handled = true;
philpem@40 550 break;
philpem@40 551 }
philpem@40 552 break;
philpem@40 553 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 554 case 0xF00000:
philpem@40 555 switch (address & 0x070000) {
philpem@40 556 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@40 557 break;
philpem@40 558 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@66 559 ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");
philpem@59 560 return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
philpem@40 561 break;
philpem@40 562 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 563 break;
philpem@40 564 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 565 break;
philpem@40 566 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 567 switch (address & 0x077000) {
philpem@40 568 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@44 569 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@40 570 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 571 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@40 572 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@40 573 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@40 574 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@44 575 // All write-only registers... TODO: bus error?
philpem@44 576 handled = true;
philpem@40 577 break;
philpem@44 578 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
philpem@40 579 break;
philpem@40 580 }
philpem@40 581 break;
philpem@40 582 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 583 break;
philpem@40 584 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 585 switch (address & 0x07F000) {
philpem@40 586 default:
philpem@40 587 break;
philpem@40 588 }
philpem@40 589 break;
philpem@40 590 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@84 591 // TODO: figure out which sizes are valid (probably just 8 and 16)
philpem@84 592 //ENFORCE_SIZE_R(bits, address, 16, "KEYBOARD CONTROLLER");
philpem@84 593 {
philpem@93 594 if (bits == 8) {
philpem@93 595 return keyboard_read(&state.kbd, (address >> 1) & 3);
philpem@93 596 } else {
philpem@93 597 return keyboard_read(&state.kbd, (address >> 1) & 3) << 8;
philpem@93 598 }
philpem@84 599 return data;
philpem@84 600 }
philpem@40 601 break;
philpem@40 602 }
philpem@40 603 }
philpem@40 604 }
philpem@40 605
philpem@64 606 LOG_NOT_HANDLED_R(bits);
philpem@64 607
philpem@59 608 return data;
philpem@59 609 }/*}}}*/
philpem@40 610
philpem@59 611
philpem@59 612 /********************************************************
philpem@59 613 * m68k memory read/write support functions for Musashi
philpem@59 614 ********************************************************/
philpem@59 615
philpem@59 616 /**
philpem@59 617 * @brief Read M68K memory, 32-bit
philpem@59 618 */
philpem@59 619 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
philpem@59 620 {
philpem@59 621 uint32_t data = 0xFFFFFFFF;
philpem@59 622
philpem@59 623 // If ROMLMAP is set, force system to access ROM
philpem@59 624 if (!state.romlmap)
philpem@59 625 address |= 0x800000;
philpem@59 626
philpem@59 627 // Check access permissions
philpem@59 628 ACCESS_CHECK_RD(address, 32);
philpem@59 629
philpem@59 630 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@59 631 // ROM access
philpem@60 632 return RD32(state.rom, address, ROM_SIZE - 1);
philpem@60 633 } else if (address <= 0x3fffff) {
philpem@59 634 // RAM access
philpem@60 635 uint32_t newAddr = mapAddr(address, false);
philpem@63 636 if (newAddr <= 0x1fffff) {
philpem@60 637 return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 638 } else {
philpem@63 639 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
philpem@63 640 return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 641 else
philpem@63 642 return 0xffffffff;
philpem@63 643 }
philpem@59 644 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@59 645 // I/O register space, zone A
philpem@59 646 switch (address & 0x0F0000) {
philpem@59 647 case 0x000000: // Map RAM access
philpem@59 648 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
philpem@60 649 return RD32(state.map, address, 0x7FF);
philpem@59 650 break;
philpem@59 651 case 0x020000: // Video RAM
philpem@59 652 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@60 653 return RD32(state.vram, address, 0x7FFF);
philpem@59 654 break;
philpem@59 655 default:
philpem@60 656 return IoRead(address, 32);
philpem@59 657 }
philpem@59 658 } else {
philpem@60 659 return IoRead(address, 32);
philpem@59 660 }
philpem@59 661
philpem@40 662 return data;
philpem@59 663 }/*}}}*/
philpem@40 664
philpem@40 665 /**
philpem@40 666 * @brief Read M68K memory, 16-bit
philpem@40 667 */
philpem@59 668 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
philpem@40 669 {
philpem@40 670 uint16_t data = 0xFFFF;
philpem@40 671
philpem@40 672 // If ROMLMAP is set, force system to access ROM
philpem@40 673 if (!state.romlmap)
philpem@40 674 address |= 0x800000;
philpem@40 675
philpem@40 676 // Check access permissions
philpem@40 677 ACCESS_CHECK_RD(address, 16);
philpem@40 678
philpem@40 679 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 680 // ROM access
philpem@40 681 data = RD16(state.rom, address, ROM_SIZE - 1);
philpem@60 682 } else if (address <= 0x3fffff) {
philpem@40 683 // RAM access
philpem@60 684 uint32_t newAddr = mapAddr(address, false);
philpem@63 685 if (newAddr <= 0x1fffff) {
philpem@60 686 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 687 } else {
philpem@63 688 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
philpem@63 689 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 690 else
philpem@63 691 return 0xffff;
philpem@63 692 }
philpem@40 693 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 694 // I/O register space, zone A
philpem@40 695 switch (address & 0x0F0000) {
philpem@40 696 case 0x000000: // Map RAM access
philpem@40 697 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 698 data = RD16(state.map, address, 0x7FF);
philpem@40 699 break;
philpem@40 700 case 0x020000: // Video RAM
philpem@40 701 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 702 data = RD16(state.vram, address, 0x7FFF);
philpem@40 703 break;
philpem@59 704 default:
philpem@59 705 data = IoRead(address, 16);
philpem@40 706 }
philpem@59 707 } else {
philpem@59 708 data = IoRead(address, 16);
philpem@40 709 }
philpem@40 710
philpem@40 711 return data;
philpem@59 712 }/*}}}*/
philpem@40 713
philpem@40 714 /**
philpem@40 715 * @brief Read M68K memory, 8-bit
philpem@40 716 */
philpem@59 717 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
philpem@40 718 {
philpem@40 719 uint8_t data = 0xFF;
philpem@40 720
philpem@40 721 // If ROMLMAP is set, force system to access ROM
philpem@40 722 if (!state.romlmap)
philpem@40 723 address |= 0x800000;
philpem@40 724
philpem@40 725 // Check access permissions
philpem@40 726 ACCESS_CHECK_RD(address, 8);
philpem@40 727
philpem@40 728 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 729 // ROM access
philpem@40 730 data = RD8(state.rom, address, ROM_SIZE - 1);
philpem@60 731 } else if (address <= 0x3fffff) {
philpem@40 732 // RAM access
philpem@60 733 uint32_t newAddr = mapAddr(address, false);
philpem@63 734 if (newAddr <= 0x1fffff) {
philpem@60 735 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 736 } else {
philpem@63 737 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
philpem@63 738 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 739 else
philpem@63 740 return 0xff;
philpem@63 741 }
philpem@40 742 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 743 // I/O register space, zone A
philpem@40 744 switch (address & 0x0F0000) {
philpem@40 745 case 0x000000: // Map RAM access
philpem@40 746 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 747 data = RD8(state.map, address, 0x7FF);
philpem@40 748 break;
philpem@40 749 case 0x020000: // Video RAM
philpem@40 750 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 751 data = RD8(state.vram, address, 0x7FFF);
philpem@40 752 break;
philpem@59 753 default:
philpem@59 754 data = IoRead(address, 8);
philpem@40 755 }
philpem@59 756 } else {
philpem@59 757 data = IoRead(address, 8);
philpem@40 758 }
philpem@40 759
philpem@40 760 return data;
philpem@59 761 }/*}}}*/
philpem@40 762
philpem@40 763 /**
philpem@40 764 * @brief Write M68K memory, 32-bit
philpem@40 765 */
philpem@59 766 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
philpem@40 767 {
philpem@40 768 // If ROMLMAP is set, force system to access ROM
philpem@40 769 if (!state.romlmap)
philpem@40 770 address |= 0x800000;
philpem@40 771
philpem@40 772 // Check access permissions
philpem@40 773 ACCESS_CHECK_WR(address, 32);
philpem@40 774
philpem@40 775 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 776 // ROM access
philpem@60 777 } else if (address <= 0x3FFFFF) {
philpem@40 778 // RAM access
philpem@60 779 uint32_t newAddr = mapAddr(address, true);
philpem@70 780 if (newAddr <= 0x1fffff)
philpem@60 781 WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@70 782 else
philpem@65 783 WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@40 784 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 785 // I/O register space, zone A
philpem@40 786 switch (address & 0x0F0000) {
philpem@40 787 case 0x000000: // Map RAM access
philpem@59 788 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 789 WR32(state.map, address, 0x7FF, value);
philpem@40 790 break;
philpem@40 791 case 0x020000: // Video RAM
philpem@59 792 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 793 WR32(state.vram, address, 0x7FFF, value);
philpem@40 794 break;
philpem@59 795 default:
philpem@59 796 IoWrite(address, value, 32);
philpem@40 797 }
philpem@59 798 } else {
philpem@59 799 IoWrite(address, value, 32);
philpem@40 800 }
philpem@59 801 }/*}}}*/
philpem@40 802
philpem@40 803 /**
philpem@40 804 * @brief Write M68K memory, 16-bit
philpem@40 805 */
philpem@59 806 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
philpem@40 807 {
philpem@40 808 // If ROMLMAP is set, force system to access ROM
philpem@40 809 if (!state.romlmap)
philpem@40 810 address |= 0x800000;
philpem@40 811
philpem@40 812 // Check access permissions
philpem@40 813 ACCESS_CHECK_WR(address, 16);
philpem@40 814
philpem@40 815 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 816 // ROM access
philpem@60 817 } else if (address <= 0x3FFFFF) {
philpem@40 818 // RAM access
philpem@60 819 uint32_t newAddr = mapAddr(address, true);
philpem@70 820 if (newAddr <= 0x1fffff)
philpem@60 821 WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@70 822 else
philpem@65 823 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@40 824 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 825 // I/O register space, zone A
philpem@40 826 switch (address & 0x0F0000) {
philpem@40 827 case 0x000000: // Map RAM access
philpem@40 828 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 829 WR16(state.map, address, 0x7FF, value);
philpem@40 830 break;
philpem@40 831 case 0x020000: // Video RAM
philpem@40 832 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 833 WR16(state.vram, address, 0x7FFF, value);
philpem@40 834 break;
philpem@59 835 default:
philpem@59 836 IoWrite(address, value, 16);
philpem@40 837 }
philpem@59 838 } else {
philpem@59 839 IoWrite(address, value, 16);
philpem@40 840 }
philpem@59 841 }/*}}}*/
philpem@40 842
philpem@40 843 /**
philpem@40 844 * @brief Write M68K memory, 8-bit
philpem@40 845 */
philpem@59 846 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
philpem@40 847 {
philpem@40 848 // If ROMLMAP is set, force system to access ROM
philpem@40 849 if (!state.romlmap)
philpem@40 850 address |= 0x800000;
philpem@40 851
philpem@40 852 // Check access permissions
philpem@40 853 ACCESS_CHECK_WR(address, 8);
philpem@40 854
philpem@40 855 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 856 // ROM access (read only!)
philpem@60 857 } else if (address <= 0x3FFFFF) {
philpem@40 858 // RAM access
philpem@60 859 uint32_t newAddr = mapAddr(address, true);
philpem@70 860 if (newAddr <= 0x1fffff)
philpem@60 861 WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@70 862 else
philpem@65 863 WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@40 864 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 865 // I/O register space, zone A
philpem@40 866 switch (address & 0x0F0000) {
philpem@40 867 case 0x000000: // Map RAM access
philpem@59 868 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 869 WR8(state.map, address, 0x7FF, value);
philpem@40 870 break;
philpem@40 871 case 0x020000: // Video RAM
philpem@59 872 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 873 WR8(state.vram, address, 0x7FFF, value);
philpem@40 874 break;
philpem@59 875 default:
philpem@59 876 IoWrite(address, value, 8);
philpem@40 877 }
philpem@59 878 } else {
philpem@59 879 IoWrite(address, value, 8);
philpem@40 880 }
philpem@59 881 }/*}}}*/
philpem@40 882
philpem@40 883
philpem@40 884 // for the disassembler
philpem@40 885 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
philpem@40 886 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
philpem@40 887 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }
philpem@40 888