src/memory.c

Fri, 18 Apr 2014 01:26:01 -0600

author
andrew@localhost
date
Fri, 18 Apr 2014 01:26:01 -0600
changeset 150
c19afa2c81db
parent 139
d91346487fe9
child 151
b63a3999e2e7
permissions
-rw-r--r--

treat all DMA reads/writes as kernel mode (previously it would depend on whether the processor happens to be in user mode or kernel mode when the DMA completes, which is totally incorrect); handle 32-bit accesses that straddle page boundaries properly (all 32-bit accesses are now split into two 16-bit accesses); allow reads to the entire zero page, rather than just address 0

philpem@40 1 #include <stdio.h>
philpem@40 2 #include <stdlib.h>
philpem@40 3 #include <stdint.h>
philpem@40 4 #include <stdbool.h>
philpem@59 5 #include <assert.h>
philpem@40 6 #include "musashi/m68k.h"
philpem@40 7 #include "state.h"
philpem@100 8 #include "utils.h"
philpem@40 9 #include "memory.h"
philpem@40 10
philpem@119 11 // The value which will be returned if the CPU attempts to read from empty memory
philpem@119 12 // TODO (FIXME?) - need to figure out if R/W ops wrap around. This seems to appease the UNIX kernel and P4TEST.
philpem@119 13 #define EMPTY 0xFFFFFFFFUL
philpem@129 14 //#define EMPTY 0x55555555UL
philpem@129 15 //#define EMPTY 0x00000000UL
philpem@119 16
philpem@40 17 /******************
philpem@40 18 * Memory mapping
philpem@40 19 ******************/
philpem@40 20
philpem@40 21 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
philpem@40 22
andrew@150 23 static uint32_t map_address_debug(uint32_t addr)
andrew@150 24 {
andrew@150 25 uint16_t page = (addr >> 12) & 0x3FF;
andrew@150 26
andrew@150 27 // Look it up in the map RAM and get the physical page address
andrew@150 28 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
andrew@150 29 return (new_page_addr << 12) + (addr & 0xFFF);
andrew@150 30 }
andrew@150 31
philpem@59 32 uint32_t mapAddr(uint32_t addr, bool writing)/*{{{*/
philpem@40 33 {
philpem@40 34 if (addr < 0x400000) {
philpem@40 35 // RAM access. Check against the Map RAM
philpem@40 36 // Start by getting the original page address
philpem@40 37 uint16_t page = (addr >> 12) & 0x3FF;
philpem@40 38
philpem@40 39 // Look it up in the map RAM and get the physical page address
philpem@40 40 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@40 41
philpem@40 42 // Update the Page Status bits
philpem@40 43 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
philpem@100 44 // Pagebits --
philpem@100 45 // 0 = not present
philpem@100 46 // 1 = present but not accessed
philpem@100 47 // 2 = present, accessed (read from)
philpem@100 48 // 3 = present, dirty (written to)
philpem@100 49 switch (pagebits) {
philpem@100 50 case 0:
philpem@100 51 // Page not present
philpem@100 52 // This should cause a page fault
philpem@100 53 LOGS("Whoa! Pagebit update, when the page is not present!");
philpem@100 54 break;
philpem@100 55
philpem@100 56 case 1:
philpem@100 57 // Page present -- first access
philpem@104 58 state.map[page*2] &= 0x9F; // turn off "present" bit (but not write enable!)
philpem@100 59 if (writing)
philpem@100 60 state.map[page*2] |= 0x60; // Page written to (dirty)
philpem@100 61 else
philpem@100 62 state.map[page*2] |= 0x40; // Page accessed but not written
philpem@100 63 break;
philpem@100 64
philpem@100 65 case 2:
philpem@100 66 case 3:
philpem@100 67 // Page present, 2nd or later access
philpem@100 68 if (writing)
philpem@100 69 state.map[page*2] |= 0x60; // Page written to (dirty)
philpem@100 70 break;
philpem@40 71 }
philpem@40 72
philpem@40 73 // Return the address with the new physical page spliced in
philpem@40 74 return (new_page_addr << 12) + (addr & 0xFFF);
philpem@40 75 } else {
philpem@40 76 // I/O, VRAM or MapRAM space; no mapping is performed or required
philpem@40 77 // TODO: assert here?
philpem@40 78 return addr;
philpem@40 79 }
philpem@59 80 }/*}}}*/
philpem@40 81
andrew@150 82 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing, bool dma)/*{{{*/
philpem@40 83 {
philpem@104 84 // Get the page bits for this page.
philpem@104 85 uint16_t page = (addr >> 12) & 0x3FF;
philpem@104 86 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
philpem@104 87
philpem@104 88 // Check page is present (but only for RAM zone)
philpem@104 89 if ((addr < 0x400000) && ((pagebits & 0x03) == 0)) {
philpem@104 90 LOG("Page not mapped in: addr %08X, page %04X, mapbits %04X", addr, page, MAPRAM(page));
philpem@104 91 return MEM_PAGEFAULT;
philpem@104 92 }
philpem@104 93
philpem@40 94 // Are we in Supervisor mode?
andrew@150 95 if (dma || (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000))
philpem@40 96 // Yes. We can do anything we like.
philpem@40 97 return MEM_ALLOWED;
philpem@40 98
philpem@40 99 // If we're here, then we must be in User mode.
philpem@40 100 // Check that the user didn't access memory outside of the RAM area
philpem@106 101 if (addr >= 0x400000) {
philpem@106 102 LOGS("User accessed privileged memory");
philpem@40 103 return MEM_UIE;
philpem@106 104 }
philpem@40 105
philpem@40 106 // User attempt to access the kernel
philpem@40 107 // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
andrew@150 108 if (((addr >> 19) & 0x0F) == 0 && !(!writing && addr <= 0x1000)) {
philpem@106 109 LOGS("Attempt by user code to access kernel space");
philpem@40 110 return MEM_KERNEL;
philpem@106 111 }
philpem@40 112
philpem@40 113 // Check page is write enabled
philpem@106 114 if (writing && ((pagebits & 0x04) == 0)) {
philpem@106 115 LOG("Page not write enabled: inaddr %08X, page %04X, mapram %04X [%02X %02X], pagebits %d",
philpem@106 116 addr, page, MAPRAM(page), state.map[page*2], state.map[(page*2)+1], pagebits);
philpem@40 117 return MEM_PAGE_NO_WE;
philpem@106 118 }
philpem@40 119 // Page access allowed.
philpem@40 120 return MEM_ALLOWED;
philpem@59 121 }/*}}}*/
philpem@40 122
andrew@150 123 #define _ACCESS_CHECK_WR_BYTE(address) \
philpem@59 124 do { \
andrew@150 125 switch (st = checkMemoryAccess(address, true, false)) { \
philpem@40 126 case MEM_ALLOWED: \
philpem@40 127 /* Access allowed */ \
philpem@40 128 break; \
philpem@40 129 case MEM_PAGEFAULT: \
philpem@40 130 /* Page fault */ \
philpem@44 131 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0); \
philpem@40 132 fault = true; \
philpem@40 133 break; \
philpem@40 134 case MEM_UIE: \
philpem@40 135 /* User access to memory above 4MB */ \
philpem@44 136 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0); \
philpem@40 137 fault = true; \
philpem@40 138 break; \
philpem@40 139 case MEM_KERNEL: \
philpem@40 140 case MEM_PAGE_NO_WE: \
philpem@40 141 /* kernel access or page not write enabled */ \
philpem@112 142 /* XXX: is this the correct value? */ \
philpem@112 143 state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0); \
philpem@40 144 fault = true; \
philpem@40 145 break; \
philpem@40 146 } \
andrew@150 147 }while (0)
andrew@150 148
andrew@150 149
andrew@150 150
andrew@150 151 /********************************************************
andrew@150 152 * m68k memory read/write support functions for Musashi
andrew@150 153 ********************************************************/
andrew@150 154
andrew@150 155 /**
andrew@150 156 * @brief Check memory access permissions for a write operation.
andrew@150 157 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
andrew@150 158 * gcc throws warnings when you have a return-with-value in a void
andrew@150 159 * function, even if the return-with-value is completely unreachable.
andrew@150 160 * Similarly it doesn't like it if you have a return without a value
andrew@150 161 * in a non-void function, even if it's impossible to ever reach the
andrew@150 162 * return-with-no-value. UGH!
andrew@150 163 */
andrew@150 164 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
andrew@150 165 #define ACCESS_CHECK_WR(address, bits) \
andrew@150 166 do { \
andrew@150 167 bool fault = false; \
andrew@150 168 MEM_STATUS st; \
andrew@150 169 _ACCESS_CHECK_WR_BYTE(address); \
andrew@150 170 if (!fault && bits == 32 \
andrew@150 171 && ((address + 3) & ~0xfff) != ((address & ~0xfff))){ \
andrew@150 172 _ACCESS_CHECK_WR_BYTE(address + 3); \
andrew@150 173 } \
philpem@40 174 if (fault) { \
philpem@40 175 if (bits >= 16) \
philpem@68 176 state.bsr0 = 0x7C00; \
philpem@40 177 else \
philpem@108 178 state.bsr0 = (address & 1) ? 0x7E00 : 0x7D00; \
philpem@40 179 state.bsr0 |= (address >> 16); \
philpem@40 180 state.bsr1 = address & 0xffff; \
philpem@103 181 LOG("Bus Error while writing, addr %08X, statcode %d", address, st); \
philpem@103 182 if (state.ee) m68k_pulse_bus_error(); \
philpem@40 183 return; \
philpem@40 184 } \
philpem@70 185 } while (0)
philpem@59 186 /*}}}*/
philpem@40 187
andrew@150 188 #define _ACCESS_CHECK_RD_BYTE(address) \
philpem@59 189 do { \
andrew@150 190 switch (st = checkMemoryAccess(address, false, false)) { \
philpem@40 191 case MEM_ALLOWED: \
philpem@40 192 /* Access allowed */ \
philpem@40 193 break; \
philpem@40 194 case MEM_PAGEFAULT: \
philpem@40 195 /* Page fault */ \
philpem@44 196 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0); \
philpem@40 197 fault = true; \
philpem@40 198 break; \
philpem@40 199 case MEM_UIE: \
philpem@40 200 /* User access to memory above 4MB */ \
philpem@44 201 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0); \
philpem@40 202 fault = true; \
philpem@40 203 break; \
philpem@40 204 case MEM_KERNEL: \
philpem@40 205 case MEM_PAGE_NO_WE: \
philpem@40 206 /* kernel access or page not write enabled */ \
philpem@112 207 /* XXX: is this the correct value? */ \
philpem@112 208 state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0); \
philpem@40 209 fault = true; \
philpem@40 210 break; \
philpem@40 211 } \
andrew@150 212 } while (0)
andrew@150 213
andrew@150 214 /**
andrew@150 215 * @brief Check memory access permissions for a read operation.
andrew@150 216 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
andrew@150 217 * gcc throws warnings when you have a return-with-value in a void
andrew@150 218 * function, even if the return-with-value is completely unreachable.
andrew@150 219 * Similarly it doesn't like it if you have a return without a value
andrew@150 220 * in a non-void function, even if it's impossible to ever reach the
andrew@150 221 * return-with-no-value. UGH!
andrew@150 222 */
andrew@150 223 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
andrew@150 224 #define ACCESS_CHECK_RD(address, bits) \
andrew@150 225 do { \
andrew@150 226 bool fault = false; \
andrew@150 227 uint32_t faultAddr = address; \
andrew@150 228 MEM_STATUS st; \
andrew@150 229 _ACCESS_CHECK_RD_BYTE(address); \
andrew@150 230 if (!fault && bits == 32 \
andrew@150 231 && ((address + 2) & ~0xfff) != (address & ~0xfff)){ \
andrew@150 232 _ACCESS_CHECK_RD_BYTE(address + 2); \
andrew@150 233 if (fault) faultAddr = address + 2; \
andrew@150 234 } \
philpem@40 235 \
philpem@40 236 if (fault) { \
philpem@40 237 if (bits >= 16) \
philpem@68 238 state.bsr0 = 0x7C00; \
philpem@40 239 else \
andrew@150 240 state.bsr0 = (faultAddr & 1) ? 0x7E00 : 0x7D00; \
andrew@150 241 state.bsr0 |= (faultAddr >> 16); \
andrew@150 242 state.bsr1 = faultAddr & 0xffff; \
andrew@150 243 LOG("Bus Error while reading, addr %08X, statcode %d", faultAddr, st); \
philpem@103 244 if (state.ee) m68k_pulse_bus_error(); \
philpem@136 245 if (bits >= 32) \
philpem@119 246 return EMPTY & 0xFFFFFFFF; \
philpem@113 247 else \
philpem@136 248 return EMPTY & ((1ULL << bits)-1); \
philpem@40 249 } \
philpem@70 250 } while (0)
philpem@59 251 /*}}}*/
philpem@40 252
philpem@112 253 bool access_check_dma(int reading)
philpem@112 254 {
philpem@112 255 // Check memory access permissions
philpem@139 256 bool access_ok = false;
andrew@150 257 switch (checkMemoryAccess(state.dma_address, !reading, true)) {
philpem@112 258 case MEM_PAGEFAULT:
philpem@112 259 // Page fault
philpem@112 260 state.genstat = 0xABFF
philpem@112 261 | (reading ? 0x4000 : 0)
philpem@112 262 | (state.pie ? 0x0400 : 0);
philpem@112 263 access_ok = false;
philpem@112 264 break;
philpem@112 265
philpem@112 266 case MEM_UIE:
philpem@112 267 // User access to memory above 4MB
philpem@112 268 // FIXME? Shouldn't be possible with DMA... assert this?
philpem@112 269 state.genstat = 0xBAFF
philpem@112 270 | (reading ? 0x4000 : 0)
philpem@112 271 | (state.pie ? 0x0400 : 0);
philpem@112 272 access_ok = false;
philpem@112 273 break;
philpem@112 274
philpem@112 275 case MEM_KERNEL:
philpem@112 276 case MEM_PAGE_NO_WE:
philpem@112 277 // Kernel access or page not write enabled
philpem@112 278 /* XXX: is this correct? */
philpem@112 279 state.genstat = 0xBBFF
philpem@112 280 | (reading ? 0x4000 : 0)
philpem@112 281 | (state.pie ? 0x0400 : 0);
philpem@112 282 access_ok = false;
philpem@112 283 break;
philpem@112 284
philpem@112 285 case MEM_ALLOWED:
philpem@112 286 access_ok = true;
philpem@112 287 break;
philpem@112 288 }
philpem@112 289 if (!access_ok) {
philpem@112 290 state.bsr0 = 0x3C00;
philpem@112 291 state.bsr0 |= (state.dma_address >> 16);
philpem@112 292 state.bsr1 = state.dma_address & 0xffff;
philpem@112 293 if (state.ee) m68k_set_irq(7);
philpem@112 294 printf("BUS ERROR FROM DMA: genstat=%04X, bsr0=%04X, bsr1=%04X\n", state.genstat, state.bsr0, state.bsr1);
philpem@112 295 }
philpem@112 296 return (access_ok);
philpem@112 297 }
philpem@112 298
philpem@40 299 // Logging macros
philpem@59 300 #define LOG_NOT_HANDLED_R(bits) \
philpem@64 301 if (!handled) printf("unhandled read%02d, addr=0x%08X\n", bits, address);
philpem@40 302
philpem@59 303 #define LOG_NOT_HANDLED_W(bits) \
philpem@64 304 if (!handled) printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
philpem@59 305
philpem@59 306 /********************************************************
philpem@59 307 * I/O read/write functions
philpem@59 308 ********************************************************/
philpem@40 309
philpem@40 310 /**
philpem@59 311 * Issue a warning if a read operation is made with an invalid size
philpem@40 312 */
philpem@66 313 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
philpem@40 314 {
philpem@59 315 assert((bits == 8) || (bits == 16) || (bits == 32));
philpem@59 316 if ((bits & allowed) == 0) {
philpem@66 317 printf("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
philpem@59 318 }
philpem@59 319 }
philpem@59 320
philpem@66 321 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
philpem@40 322 {
philpem@66 323 ENFORCE_SIZE(bits, address, true, allowed, regname);
philpem@66 324 }
philpem@66 325
philpem@66 326 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
philpem@66 327 {
philpem@66 328 ENFORCE_SIZE(bits, address, false, allowed, regname);
philpem@66 329 }
philpem@66 330
philpem@59 331 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
philpem@59 332 {
philpem@40 333 bool handled = false;
philpem@40 334
philpem@59 335 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 336 // I/O register space, zone A
philpem@40 337 switch (address & 0x0F0000) {
philpem@40 338 case 0x010000: // General Status Register
philpem@59 339 if (bits == 16)
philpem@59 340 state.genstat = (data & 0xffff);
philpem@59 341 else if (bits == 8) {
philpem@59 342 if (address & 0)
philpem@59 343 state.genstat = data;
philpem@59 344 else
philpem@59 345 state.genstat = data << 8;
philpem@59 346 }
philpem@40 347 handled = true;
philpem@40 348 break;
philpem@40 349 case 0x030000: // Bus Status Register 0
philpem@40 350 break;
philpem@40 351 case 0x040000: // Bus Status Register 1
philpem@40 352 break;
philpem@40 353 case 0x050000: // Phone status
philpem@40 354 break;
philpem@40 355 case 0x060000: // DMA Count
philpem@66 356 ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
philpem@59 357 state.dma_count = (data & 0x3FFF);
philpem@59 358 state.idmarw = ((data & 0x4000) == 0x4000);
philpem@59 359 state.dmaen = ((data & 0x8000) == 0x8000);
philpem@59 360 // This handles the "dummy DMA transfer" mentioned in the docs
philpem@112 361 // disabled because it causes the floppy test to fail
philpem@112 362 #if 0
philpem@112 363 if (!state.idmarw){
philpem@112 364 if (access_check_dma(true)){
philpem@112 365 uint32_t newAddr = mapAddr(state.dma_address, true);
philpem@112 366 // RAM access
philpem@112 367 if (newAddr <= 0x1fffff)
philpem@112 368 WR16(state.base_ram, newAddr, state.base_ram_size - 1, 0xFF);
philpem@112 369 else if (address <= 0x3FFFFF)
philpem@112 370 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, 0xFF);
philpem@112 371 }
philpem@112 372 }
philpem@112 373 #endif
philpem@59 374 state.dma_count++;
philpem@53 375 handled = true;
philpem@40 376 break;
philpem@40 377 case 0x070000: // Line Printer Status Register
philpem@40 378 break;
philpem@40 379 case 0x080000: // Real Time Clock
philpem@40 380 break;
philpem@40 381 case 0x090000: // Phone registers
philpem@40 382 switch (address & 0x0FF000) {
philpem@40 383 case 0x090000: // Handset relay
philpem@40 384 case 0x098000:
philpem@40 385 break;
philpem@40 386 case 0x091000: // Line select 2
philpem@40 387 case 0x099000:
philpem@40 388 break;
philpem@40 389 case 0x092000: // Hook relay 1
philpem@40 390 case 0x09A000:
philpem@40 391 break;
philpem@40 392 case 0x093000: // Hook relay 2
philpem@40 393 case 0x09B000:
philpem@40 394 break;
philpem@40 395 case 0x094000: // Line 1 hold
philpem@40 396 case 0x09C000:
philpem@40 397 break;
philpem@40 398 case 0x095000: // Line 2 hold
philpem@40 399 case 0x09D000:
philpem@40 400 break;
philpem@40 401 case 0x096000: // Line 1 A-lead
philpem@40 402 case 0x09E000:
philpem@40 403 break;
philpem@40 404 case 0x097000: // Line 2 A-lead
philpem@40 405 case 0x09F000:
philpem@40 406 break;
philpem@40 407 }
philpem@40 408 break;
philpem@59 409 case 0x0A0000: // Miscellaneous Control Register
philpem@66 410 ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
philpem@59 411 // TODO: handle the ctrl bits properly
philpem@97 412 if (data & 0x8000){
philpem@97 413 state.timer_enabled = 1;
philpem@97 414 }else{
philpem@97 415 state.timer_enabled = 0;
philpem@97 416 state.timer_asserted = 0;
philpem@97 417 }
philpem@59 418 state.dma_reading = (data & 0x4000);
philpem@72 419 if (state.leds != ((~data & 0xF00) >> 8)) {
philpem@72 420 state.leds = (~data & 0xF00) >> 8;
philpem@117 421 #ifdef SHOW_LEDS
philpem@72 422 printf("LEDs: %s %s %s %s\n",
philpem@72 423 (state.leds & 8) ? "R" : "-",
philpem@72 424 (state.leds & 4) ? "G" : "-",
philpem@72 425 (state.leds & 2) ? "Y" : "-",
philpem@72 426 (state.leds & 1) ? "R" : "-");
philpem@117 427 #endif
philpem@72 428 }
philpem@46 429 handled = true;
philpem@40 430 break;
philpem@40 431 case 0x0B0000: // TM/DIALWR
philpem@40 432 break;
philpem@59 433 case 0x0C0000: // Clear Status Register
philpem@59 434 state.genstat = 0xFFFF;
philpem@59 435 state.bsr0 = 0xFFFF;
philpem@59 436 state.bsr1 = 0xFFFF;
philpem@43 437 handled = true;
philpem@40 438 break;
philpem@40 439 case 0x0D0000: // DMA Address Register
philpem@59 440 if (address & 0x004000) {
philpem@59 441 // A14 high -- set most significant bits
philpem@59 442 state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
philpem@59 443 } else {
philpem@59 444 // A14 low -- set least significant bits
philpem@59 445 state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
philpem@59 446 }
philpem@59 447 handled = true;
philpem@40 448 break;
philpem@40 449 case 0x0E0000: // Disk Control Register
philpem@112 450 {
philpem@112 451 bool fd_selected;
philpem@112 452 bool hd_selected;
philpem@112 453 ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
philpem@112 454 // B7 = FDD controller reset
philpem@112 455 if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
philpem@112 456 // B6 = drive 0 select
philpem@112 457 fd_selected = (data & 0x40) != 0;
philpem@112 458 // B5 = motor enable -- TODO
philpem@112 459 // B4 = HDD controller reset
philpem@112 460 if ((data & 0x10) == 0) wd2010_reset(&state.hdc_ctx);
philpem@112 461 // B3 = HDD0 select
philpem@112 462 hd_selected = (data & 0x08) != 0;
philpem@112 463 // B2,1,0 = HDD0 head select -- TODO?
philpem@112 464 if (hd_selected && !state.hd_selected){
philpem@112 465 state.fd_selected = false;
philpem@112 466 state.hd_selected = true;
philpem@112 467 }else if (fd_selected && !state.fd_selected){
philpem@112 468 state.hd_selected = false;
philpem@112 469 state.fd_selected = true;
philpem@112 470 }
philpem@112 471 handled = true;
philpem@112 472 break;
philpem@112 473 }
philpem@40 474 case 0x0F0000: // Line Printer Data Register
philpem@40 475 break;
philpem@40 476 }
philpem@40 477 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 478 // I/O register space, zone B
philpem@40 479 switch (address & 0xF00000) {
philpem@40 480 case 0xC00000: // Expansion slots
philpem@40 481 case 0xD00000:
philpem@40 482 switch (address & 0xFC0000) {
philpem@40 483 case 0xC00000: // Expansion slot 0
philpem@40 484 case 0xC40000: // Expansion slot 1
philpem@40 485 case 0xC80000: // Expansion slot 2
philpem@40 486 case 0xCC0000: // Expansion slot 3
philpem@40 487 case 0xD00000: // Expansion slot 4
philpem@40 488 case 0xD40000: // Expansion slot 5
philpem@40 489 case 0xD80000: // Expansion slot 6
philpem@40 490 case 0xDC0000: // Expansion slot 7
philpem@59 491 fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
philpem@59 492 handled = true;
philpem@40 493 break;
philpem@40 494 }
philpem@40 495 break;
philpem@40 496 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 497 case 0xF00000:
philpem@40 498 switch (address & 0x070000) {
philpem@112 499 case 0x000000: // [ef][08]xxxx ==> WD2010 hard disc controller
philpem@112 500 wd2010_write_reg(&state.hdc_ctx, (address >> 1) & 7, data);
philpem@112 501 handled = true;
philpem@40 502 break;
philpem@40 503 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@112 504 /*ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");*/
philpem@59 505 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
philpem@52 506 handled = true;
philpem@40 507 break;
philpem@40 508 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@116 509 // MCR2 - UNIX PC Rev. P5.1 HDD head select b3 and potential HDD#2 select
philpem@116 510 wd2010_write_reg(&state.hdc_ctx, UNIXPC_REG_MCR2, data);
philpem@116 511 handled = true;
philpem@40 512 break;
philpem@40 513 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 514 break;
philpem@40 515 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 516 switch (address & 0x077000) {
philpem@40 517 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@102 518 // Error Enable. If =0, Level7 intrs and bus errors are masked.
philpem@102 519 ENFORCE_SIZE_W(bits, address, 16, "EE");
philpem@102 520 state.ee = ((data & 0x8000) == 0x8000);
philpem@102 521 handled = true;
philpem@59 522 break;
philpem@44 523 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@66 524 ENFORCE_SIZE_W(bits, address, 16, "PIE");
philpem@59 525 state.pie = ((data & 0x8000) == 0x8000);
philpem@59 526 handled = true;
philpem@59 527 break;
philpem@40 528 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@59 529 break;
philpem@40 530 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@66 531 ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
philpem@59 532 state.romlmap = ((data & 0x8000) == 0x8000);
philpem@44 533 handled = true;
philpem@40 534 break;
philpem@59 535 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@66 536 ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
philpem@59 537 break;
philpem@59 538 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@66 539 ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
philpem@59 540 break;
philpem@59 541 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@66 542 ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
philpem@59 543 break;
philpem@59 544 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@66 545 ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
philpem@40 546 break;
philpem@40 547 }
philpem@40 548 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 549 break;
philpem@40 550 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 551 switch (address & 0x07F000) {
philpem@40 552 default:
philpem@40 553 break;
philpem@40 554 }
philpem@40 555 break;
philpem@40 556 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@84 557 // TODO: figure out which sizes are valid (probably just 8 and 16)
philpem@84 558 // ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER");
philpem@93 559 if (bits == 8) {
philpem@93 560 printf("KBD WR %02X => %02X\n", (address >> 1) & 3, data);
philpem@93 561 keyboard_write(&state.kbd, (address >> 1) & 3, data);
philpem@93 562 handled = true;
philpem@93 563 } else if (bits == 16) {
philpem@93 564 printf("KBD WR %02X => %04X\n", (address >> 1) & 3, data);
philpem@93 565 keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8);
philpem@93 566 handled = true;
philpem@93 567 }
philpem@40 568 break;
philpem@40 569 }
philpem@40 570 }
philpem@40 571 }
philpem@40 572
philpem@64 573 LOG_NOT_HANDLED_W(bits);
philpem@59 574 }/*}}}*/
philpem@40 575
philpem@59 576 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
philpem@59 577 {
philpem@59 578 bool handled = false;
philpem@119 579 uint32_t data = EMPTY & 0xFFFFFFFF;
philpem@40 580
philpem@59 581 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 582 // I/O register space, zone A
philpem@40 583 switch (address & 0x0F0000) {
philpem@40 584 case 0x010000: // General Status Register
philpem@116 585 /* ENFORCE_SIZE_R(bits, address, 16, "GENSTAT"); */
philpem@116 586 if (bits == 32) {
philpem@116 587 return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
philpem@116 588 } else if (bits == 16) {
philpem@116 589 return (uint16_t)state.genstat;
philpem@116 590 } else {
philpem@116 591 return (uint8_t)(state.genstat & 0xff);
philpem@116 592 }
philpem@40 593 break;
philpem@40 594 case 0x030000: // Bus Status Register 0
philpem@66 595 ENFORCE_SIZE_R(bits, address, 16, "BSR0");
philpem@59 596 return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
philpem@40 597 break;
philpem@40 598 case 0x040000: // Bus Status Register 1
philpem@66 599 ENFORCE_SIZE_R(bits, address, 16, "BSR1");
philpem@59 600 return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
philpem@40 601 break;
philpem@40 602 case 0x050000: // Phone status
philpem@66 603 ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
philpem@40 604 break;
philpem@40 605 case 0x060000: // DMA Count
philpem@55 606 // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
philpem@55 607 // Bit 14 is always unused, so leave it set
philpem@66 608 ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
philpem@59 609 return (state.dma_count & 0x3fff) | 0xC000;
philpem@40 610 break;
philpem@40 611 case 0x070000: // Line Printer Status Register
philpem@53 612 data = 0x00120012; // no parity error, no line printer error, no irqs from FDD or HDD
philpem@78 613 data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0;
philpem@112 614 data |= wd2010_get_irq(&state.hdc_ctx) ? 0x00040004 : 0;
philpem@59 615 return data;
philpem@40 616 break;
philpem@40 617 case 0x080000: // Real Time Clock
philpem@59 618 printf("READ NOTIMP: Realtime Clock\n");
philpem@40 619 break;
philpem@40 620 case 0x090000: // Phone registers
philpem@40 621 switch (address & 0x0FF000) {
philpem@40 622 case 0x090000: // Handset relay
philpem@40 623 case 0x098000:
philpem@40 624 break;
philpem@40 625 case 0x091000: // Line select 2
philpem@40 626 case 0x099000:
philpem@40 627 break;
philpem@40 628 case 0x092000: // Hook relay 1
philpem@40 629 case 0x09A000:
philpem@40 630 break;
philpem@40 631 case 0x093000: // Hook relay 2
philpem@40 632 case 0x09B000:
philpem@40 633 break;
philpem@40 634 case 0x094000: // Line 1 hold
philpem@40 635 case 0x09C000:
philpem@40 636 break;
philpem@40 637 case 0x095000: // Line 2 hold
philpem@40 638 case 0x09D000:
philpem@40 639 break;
philpem@40 640 case 0x096000: // Line 1 A-lead
philpem@40 641 case 0x09E000:
philpem@40 642 break;
philpem@40 643 case 0x097000: // Line 2 A-lead
philpem@40 644 case 0x09F000:
philpem@40 645 break;
philpem@40 646 }
philpem@40 647 break;
philpem@46 648 case 0x0A0000: // Miscellaneous Control Register -- write only!
philpem@46 649 handled = true;
philpem@40 650 break;
philpem@40 651 case 0x0B0000: // TM/DIALWR
philpem@40 652 break;
philpem@46 653 case 0x0C0000: // Clear Status Register -- write only!
philpem@43 654 handled = true;
philpem@40 655 break;
philpem@40 656 case 0x0D0000: // DMA Address Register
philpem@40 657 break;
philpem@40 658 case 0x0E0000: // Disk Control Register
philpem@40 659 break;
philpem@40 660 case 0x0F0000: // Line Printer Data Register
philpem@40 661 break;
philpem@40 662 }
philpem@40 663 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 664 // I/O register space, zone B
philpem@40 665 switch (address & 0xF00000) {
philpem@40 666 case 0xC00000: // Expansion slots
philpem@40 667 case 0xD00000:
philpem@40 668 switch (address & 0xFC0000) {
philpem@40 669 case 0xC00000: // Expansion slot 0
philpem@40 670 case 0xC40000: // Expansion slot 1
philpem@40 671 case 0xC80000: // Expansion slot 2
philpem@40 672 case 0xCC0000: // Expansion slot 3
philpem@40 673 case 0xD00000: // Expansion slot 4
philpem@40 674 case 0xD40000: // Expansion slot 5
philpem@40 675 case 0xD80000: // Expansion slot 6
philpem@40 676 case 0xDC0000: // Expansion slot 7
philpem@65 677 fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
philpem@65 678 handled = true;
philpem@40 679 break;
philpem@40 680 }
philpem@40 681 break;
philpem@40 682 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 683 case 0xF00000:
philpem@40 684 switch (address & 0x070000) {
philpem@40 685 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@112 686 return (wd2010_read_reg(&state.hdc_ctx, (address >> 1) & 7));
philpem@112 687
philpem@40 688 break;
philpem@40 689 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@112 690 /*ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");*/
philpem@59 691 return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
philpem@40 692 break;
philpem@40 693 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 694 break;
philpem@40 695 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 696 break;
philpem@40 697 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 698 switch (address & 0x077000) {
philpem@40 699 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@44 700 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@40 701 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 702 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@40 703 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@40 704 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@40 705 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@44 706 // All write-only registers... TODO: bus error?
philpem@44 707 handled = true;
philpem@40 708 break;
philpem@44 709 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
philpem@40 710 break;
philpem@40 711 }
philpem@40 712 break;
philpem@40 713 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 714 break;
philpem@40 715 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 716 switch (address & 0x07F000) {
philpem@40 717 default:
philpem@40 718 break;
philpem@40 719 }
philpem@40 720 break;
philpem@40 721 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@84 722 // TODO: figure out which sizes are valid (probably just 8 and 16)
philpem@84 723 //ENFORCE_SIZE_R(bits, address, 16, "KEYBOARD CONTROLLER");
philpem@84 724 {
philpem@93 725 if (bits == 8) {
philpem@93 726 return keyboard_read(&state.kbd, (address >> 1) & 3);
philpem@93 727 } else {
philpem@93 728 return keyboard_read(&state.kbd, (address >> 1) & 3) << 8;
philpem@93 729 }
philpem@84 730 return data;
philpem@84 731 }
philpem@40 732 break;
philpem@40 733 }
philpem@40 734 }
philpem@40 735 }
philpem@40 736
philpem@64 737 LOG_NOT_HANDLED_R(bits);
philpem@64 738
philpem@59 739 return data;
philpem@59 740 }/*}}}*/
philpem@40 741
philpem@59 742
philpem@59 743 /********************************************************
philpem@59 744 * m68k memory read/write support functions for Musashi
philpem@59 745 ********************************************************/
philpem@59 746
andrew@150 747
andrew@150 748 static uint16_t ram_read_16(uint32_t address)
andrew@150 749 {
andrew@150 750 if (address <= 0x1fffff) {
andrew@150 751 // Base memory wraps around
andrew@150 752 return RD16(state.base_ram, address, state.base_ram_size - 1);
andrew@150 753 } else {
andrew@150 754 if ((address <= (state.exp_ram_size + 0x200000 - 1)) && (address >= 0x200000)){
andrew@150 755 return RD16(state.exp_ram, address - 0x200000, state.exp_ram_size - 1);
andrew@150 756 }else
andrew@150 757 return EMPTY & 0xffff;
andrew@150 758 }
andrew@150 759 }
andrew@150 760
philpem@59 761 /**
philpem@59 762 * @brief Read M68K memory, 32-bit
philpem@59 763 */
philpem@59 764 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
philpem@59 765 {
philpem@119 766 uint32_t data = EMPTY & 0xFFFFFFFF;
philpem@59 767
philpem@59 768 // If ROMLMAP is set, force system to access ROM
philpem@59 769 if (!state.romlmap)
philpem@59 770 address |= 0x800000;
philpem@59 771
philpem@59 772 // Check access permissions
philpem@59 773 ACCESS_CHECK_RD(address, 32);
philpem@59 774
philpem@59 775 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@59 776 // ROM access
philpem@60 777 return RD32(state.rom, address, ROM_SIZE - 1);
philpem@60 778 } else if (address <= 0x3fffff) {
philpem@59 779 // RAM access
philpem@60 780 uint32_t newAddr = mapAddr(address, false);
andrew@150 781 // Base memory wraps around
andrew@150 782 data = ((ram_read_16(newAddr) << 16) |
andrew@150 783 ram_read_16(mapAddr(address + 2, false)));
andrew@150 784
andrew@150 785 return (data);
philpem@59 786 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@59 787 // I/O register space, zone A
philpem@59 788 switch (address & 0x0F0000) {
philpem@59 789 case 0x000000: // Map RAM access
philpem@59 790 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
philpem@60 791 return RD32(state.map, address, 0x7FF);
philpem@59 792 break;
philpem@59 793 case 0x020000: // Video RAM
philpem@59 794 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@60 795 return RD32(state.vram, address, 0x7FFF);
philpem@59 796 break;
philpem@59 797 default:
philpem@60 798 return IoRead(address, 32);
philpem@59 799 }
philpem@59 800 } else {
philpem@60 801 return IoRead(address, 32);
philpem@59 802 }
philpem@59 803
philpem@40 804 return data;
philpem@59 805 }/*}}}*/
philpem@40 806
philpem@40 807 /**
philpem@40 808 * @brief Read M68K memory, 16-bit
philpem@40 809 */
philpem@59 810 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
philpem@40 811 {
philpem@119 812 uint16_t data = EMPTY & 0xFFFF;
philpem@40 813
philpem@40 814 // If ROMLMAP is set, force system to access ROM
philpem@40 815 if (!state.romlmap)
philpem@40 816 address |= 0x800000;
philpem@40 817
philpem@40 818 // Check access permissions
philpem@40 819 ACCESS_CHECK_RD(address, 16);
philpem@40 820
philpem@40 821 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 822 // ROM access
philpem@40 823 data = RD16(state.rom, address, ROM_SIZE - 1);
philpem@60 824 } else if (address <= 0x3fffff) {
philpem@40 825 // RAM access
philpem@60 826 uint32_t newAddr = mapAddr(address, false);
philpem@63 827 if (newAddr <= 0x1fffff) {
philpem@129 828 // Base memory wraps around
philpem@129 829 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 830 } else {
philpem@119 831 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@63 832 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 833 else
philpem@119 834 return EMPTY & 0xffff;
philpem@63 835 }
philpem@40 836 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 837 // I/O register space, zone A
philpem@40 838 switch (address & 0x0F0000) {
philpem@40 839 case 0x000000: // Map RAM access
philpem@40 840 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 841 data = RD16(state.map, address, 0x7FF);
philpem@40 842 break;
philpem@40 843 case 0x020000: // Video RAM
philpem@40 844 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 845 data = RD16(state.vram, address, 0x7FFF);
philpem@40 846 break;
philpem@59 847 default:
philpem@59 848 data = IoRead(address, 16);
philpem@40 849 }
philpem@59 850 } else {
philpem@59 851 data = IoRead(address, 16);
philpem@40 852 }
philpem@40 853
philpem@40 854 return data;
philpem@59 855 }/*}}}*/
philpem@40 856
philpem@40 857 /**
philpem@40 858 * @brief Read M68K memory, 8-bit
philpem@40 859 */
philpem@59 860 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
philpem@40 861 {
philpem@119 862 uint8_t data = EMPTY & 0xFF;
philpem@40 863
philpem@40 864 // If ROMLMAP is set, force system to access ROM
philpem@40 865 if (!state.romlmap)
philpem@40 866 address |= 0x800000;
philpem@40 867
philpem@40 868 // Check access permissions
philpem@40 869 ACCESS_CHECK_RD(address, 8);
philpem@40 870
philpem@40 871 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 872 // ROM access
philpem@40 873 data = RD8(state.rom, address, ROM_SIZE - 1);
philpem@60 874 } else if (address <= 0x3fffff) {
philpem@40 875 // RAM access
philpem@60 876 uint32_t newAddr = mapAddr(address, false);
philpem@63 877 if (newAddr <= 0x1fffff) {
philpem@129 878 // Base memory wraps around
philpem@129 879 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@63 880 } else {
philpem@119 881 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@63 882 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@63 883 else
philpem@119 884 return EMPTY & 0xff;
philpem@63 885 }
philpem@40 886 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 887 // I/O register space, zone A
philpem@40 888 switch (address & 0x0F0000) {
philpem@40 889 case 0x000000: // Map RAM access
philpem@40 890 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 891 data = RD8(state.map, address, 0x7FF);
philpem@40 892 break;
philpem@40 893 case 0x020000: // Video RAM
philpem@40 894 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 895 data = RD8(state.vram, address, 0x7FFF);
philpem@40 896 break;
philpem@59 897 default:
philpem@59 898 data = IoRead(address, 8);
philpem@40 899 }
philpem@59 900 } else {
philpem@59 901 data = IoRead(address, 8);
philpem@40 902 }
philpem@40 903
philpem@40 904 return data;
philpem@59 905 }/*}}}*/
philpem@40 906
andrew@150 907
andrew@150 908 static void ram_write_16(uint32_t address, uint32_t value)/*{{{*/
andrew@150 909 {
andrew@150 910 if (address <= 0x1fffff) {
andrew@150 911 if (address < state.base_ram_size) {
andrew@150 912 WR16(state.base_ram, address, state.base_ram_size - 1, value);
andrew@150 913 }
andrew@150 914 } else {
andrew@150 915 if ((address - 0x200000) < state.exp_ram_size) {
andrew@150 916 WR16(state.exp_ram, address - 0x200000, state.exp_ram_size - 1, value);
andrew@150 917 }
andrew@150 918 }
andrew@150 919 }
andrew@150 920
philpem@40 921 /**
philpem@40 922 * @brief Write M68K memory, 32-bit
philpem@40 923 */
philpem@59 924 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
philpem@40 925 {
philpem@40 926 // If ROMLMAP is set, force system to access ROM
philpem@40 927 if (!state.romlmap)
philpem@40 928 address |= 0x800000;
philpem@40 929
philpem@40 930 // Check access permissions
philpem@40 931 ACCESS_CHECK_WR(address, 32);
philpem@40 932 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 933 // ROM access
philpem@60 934 } else if (address <= 0x3FFFFF) {
philpem@40 935 // RAM access
philpem@60 936 uint32_t newAddr = mapAddr(address, true);
andrew@150 937 ram_write_16(newAddr, (value & 0xffff0000) >> 16);
andrew@150 938 ram_write_16(mapAddr(address + 2, true), (value & 0xffff));
philpem@40 939 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 940 // I/O register space, zone A
philpem@40 941 switch (address & 0x0F0000) {
philpem@40 942 case 0x000000: // Map RAM access
philpem@105 943 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X\n", address);
philpem@40 944 WR32(state.map, address, 0x7FF, value);
philpem@40 945 break;
philpem@40 946 case 0x020000: // Video RAM
philpem@105 947 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 948 WR32(state.vram, address, 0x7FFF, value);
philpem@40 949 break;
philpem@59 950 default:
philpem@59 951 IoWrite(address, value, 32);
philpem@40 952 }
philpem@59 953 } else {
philpem@59 954 IoWrite(address, value, 32);
philpem@40 955 }
philpem@59 956 }/*}}}*/
philpem@40 957
philpem@40 958 /**
philpem@40 959 * @brief Write M68K memory, 16-bit
philpem@40 960 */
philpem@59 961 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
philpem@40 962 {
philpem@40 963 // If ROMLMAP is set, force system to access ROM
philpem@40 964 if (!state.romlmap)
philpem@40 965 address |= 0x800000;
philpem@40 966
philpem@40 967 // Check access permissions
philpem@40 968 ACCESS_CHECK_WR(address, 16);
philpem@40 969
philpem@40 970 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 971 // ROM access
philpem@60 972 } else if (address <= 0x3FFFFF) {
philpem@40 973 // RAM access
philpem@60 974 uint32_t newAddr = mapAddr(address, true);
philpem@112 975
philpem@119 976 if (newAddr <= 0x1fffff) {
philpem@119 977 if (newAddr < state.base_ram_size) {
philpem@119 978 WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@119 979 }
philpem@119 980 } else {
philpem@119 981 if ((newAddr - 0x200000) < state.exp_ram_size) {
philpem@119 982 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@119 983 }
philpem@119 984 }
philpem@40 985 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 986 // I/O register space, zone A
philpem@40 987 switch (address & 0x0F0000) {
philpem@40 988 case 0x000000: // Map RAM access
philpem@40 989 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 990 WR16(state.map, address, 0x7FF, value);
philpem@40 991 break;
philpem@40 992 case 0x020000: // Video RAM
philpem@40 993 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 994 WR16(state.vram, address, 0x7FFF, value);
philpem@40 995 break;
philpem@59 996 default:
philpem@59 997 IoWrite(address, value, 16);
philpem@40 998 }
philpem@59 999 } else {
philpem@59 1000 IoWrite(address, value, 16);
philpem@40 1001 }
philpem@59 1002 }/*}}}*/
philpem@40 1003
philpem@40 1004 /**
philpem@40 1005 * @brief Write M68K memory, 8-bit
philpem@40 1006 */
philpem@59 1007 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
philpem@40 1008 {
philpem@40 1009 // If ROMLMAP is set, force system to access ROM
philpem@40 1010 if (!state.romlmap)
philpem@40 1011 address |= 0x800000;
philpem@40 1012
philpem@40 1013 // Check access permissions
philpem@40 1014 ACCESS_CHECK_WR(address, 8);
philpem@40 1015
philpem@40 1016 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 1017 // ROM access (read only!)
philpem@60 1018 } else if (address <= 0x3FFFFF) {
philpem@40 1019 // RAM access
philpem@60 1020 uint32_t newAddr = mapAddr(address, true);
philpem@119 1021 if (newAddr <= 0x1fffff) {
philpem@119 1022 if (newAddr < state.base_ram_size) {
philpem@119 1023 WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
philpem@119 1024 }
philpem@119 1025 } else {
philpem@119 1026 if ((newAddr - 0x200000) < state.exp_ram_size) {
philpem@119 1027 WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
philpem@119 1028 }
philpem@119 1029 }
philpem@40 1030 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 1031 // I/O register space, zone A
philpem@40 1032 switch (address & 0x0F0000) {
philpem@40 1033 case 0x000000: // Map RAM access
philpem@59 1034 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 1035 WR8(state.map, address, 0x7FF, value);
philpem@40 1036 break;
philpem@40 1037 case 0x020000: // Video RAM
philpem@59 1038 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 1039 WR8(state.vram, address, 0x7FFF, value);
philpem@40 1040 break;
philpem@59 1041 default:
philpem@59 1042 IoWrite(address, value, 8);
philpem@40 1043 }
philpem@59 1044 } else {
philpem@59 1045 IoWrite(address, value, 8);
philpem@40 1046 }
philpem@59 1047 }/*}}}*/
philpem@40 1048
philpem@40 1049
philpem@40 1050 // for the disassembler
philpem@121 1051 uint32_t m68k_read_disassembler_32(uint32_t addr)
philpem@121 1052 {
philpem@121 1053 if (addr < 0x400000) {
andrew@150 1054 uint32_t newAddrHigh, newAddrLow;
andrew@150 1055 newAddrHigh = map_address_debug(addr);
andrew@150 1056 newAddrLow = map_address_debug(addr + 2);
andrew@150 1057 return ((ram_read_16(newAddrHigh) << 16) |
andrew@150 1058 ram_read_16(newAddrLow));
andrew@150 1059
philpem@121 1060 } else {
philpem@121 1061 printf(">>> WARNING Disassembler RD32 out of range 0x%08X\n", addr);
philpem@121 1062 return EMPTY;
philpem@121 1063 }
philpem@121 1064 }
philpem@40 1065
philpem@121 1066 uint32_t m68k_read_disassembler_16(uint32_t addr)
philpem@121 1067 {
philpem@121 1068 if (addr < 0x400000) {
philpem@121 1069 uint16_t page = (addr >> 12) & 0x3FF;
philpem@121 1070 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@121 1071 uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
philpem@121 1072 if (newAddr <= 0x1fffff) {
philpem@121 1073 if (newAddr >= state.base_ram_size)
philpem@121 1074 return EMPTY & 0xffff;
philpem@121 1075 else
philpem@121 1076 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@121 1077 } else {
philpem@121 1078 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@121 1079 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@121 1080 else
philpem@121 1081 return EMPTY & 0xffff;
philpem@121 1082 }
philpem@121 1083 } else {
philpem@121 1084 printf(">>> WARNING Disassembler RD16 out of range 0x%08X\n", addr);
philpem@121 1085 return EMPTY & 0xffff;
philpem@121 1086 }
philpem@121 1087 }
philpem@121 1088
philpem@121 1089 uint32_t m68k_read_disassembler_8 (uint32_t addr)
philpem@121 1090 {
philpem@121 1091 if (addr < 0x400000) {
philpem@121 1092 uint16_t page = (addr >> 12) & 0x3FF;
philpem@121 1093 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@121 1094 uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
philpem@121 1095 if (newAddr <= 0x1fffff) {
philpem@121 1096 if (newAddr >= state.base_ram_size)
philpem@121 1097 return EMPTY & 0xff;
philpem@121 1098 else
philpem@121 1099 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
philpem@121 1100 } else {
philpem@121 1101 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
philpem@121 1102 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
philpem@121 1103 else
philpem@121 1104 return EMPTY & 0xff;
philpem@121 1105 }
philpem@121 1106 } else {
philpem@121 1107 printf(">>> WARNING Disassembler RD8 out of range 0x%08X\n", addr);
philpem@121 1108 return EMPTY & 0xff;
philpem@121 1109 }
philpem@121 1110 }
philpem@121 1111