src/main.c

Thu, 02 Dec 2010 22:40:13 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Thu, 02 Dec 2010 22:40:13 +0000
changeset 39
cab49f90c3b9
parent 38
b948045ca964
child 40
239bc48590ba
permissions
-rw-r--r--

remove redundant debug printf

philpem@0 1 #include <stdio.h>
philpem@7 2 #include <stdlib.h>
philpem@4 3 #include <stdint.h>
philpem@7 4 #include <stdbool.h>
philpem@7 5 #include <malloc.h>
philpem@7 6 #include <string.h>
philpem@18 7
philpem@20 8 #include "SDL.h"
philpem@20 9
philpem@4 10 #include "musashi/m68k.h"
philpem@7 11 #include "version.h"
philpem@18 12 #include "state.h"
philpem@7 13
philpem@7 14 void FAIL(char *err)
philpem@7 15 {
philpem@7 16 state_done();
philpem@7 17 fprintf(stderr, "ERROR: %s\nExiting...\n", err);
philpem@7 18 exit(EXIT_FAILURE);
philpem@7 19 }
philpem@7 20
philpem@26 21 /***********************************
philpem@26 22 * Array read/write utility macros
philpem@26 23 * "Don't Repeat Yourself" :)
philpem@26 24 ***********************************/
philpem@26 25
philpem@26 26 /// Array read, 32-bit
philpem@26 27 #define RD32(array, address, andmask) \
philpem@26 28 (((uint32_t)array[(address + 0) & (andmask)] << 24) | \
philpem@26 29 ((uint32_t)array[(address + 1) & (andmask)] << 16) | \
philpem@26 30 ((uint32_t)array[(address + 2) & (andmask)] << 8) | \
philpem@26 31 ((uint32_t)array[(address + 3) & (andmask)]))
philpem@26 32
philpem@26 33 /// Array read, 16-bit
philpem@26 34 #define RD16(array, address, andmask) \
philpem@26 35 (((uint32_t)array[(address + 0) & (andmask)] << 8) | \
philpem@26 36 ((uint32_t)array[(address + 1) & (andmask)]))
philpem@26 37
philpem@26 38 /// Array read, 8-bit
philpem@26 39 #define RD8(array, address, andmask) \
philpem@26 40 ((uint32_t)array[(address + 0) & (andmask)])
philpem@26 41
philpem@26 42 /// Array write, 32-bit
philpem@26 43 #define WR32(array, address, andmask, value) { \
philpem@26 44 array[(address + 0) & (andmask)] = (value >> 24) & 0xff; \
philpem@26 45 array[(address + 1) & (andmask)] = (value >> 16) & 0xff; \
philpem@26 46 array[(address + 2) & (andmask)] = (value >> 8) & 0xff; \
philpem@26 47 array[(address + 3) & (andmask)] = value & 0xff; \
philpem@26 48 }
philpem@26 49
philpem@26 50 /// Array write, 16-bit
philpem@26 51 #define WR16(array, address, andmask, value) { \
philpem@26 52 array[(address + 0) & (andmask)] = (value >> 8) & 0xff; \
philpem@26 53 array[(address + 1) & (andmask)] = value & 0xff; \
philpem@26 54 }
philpem@26 55
philpem@26 56 /// Array write, 8-bit
philpem@26 57 #define WR8(array, address, andmask, value) \
philpem@26 58 array[(address + 0) & (andmask)] = value & 0xff;
philpem@26 59
philpem@30 60 /******************
philpem@30 61 * Memory mapping
philpem@30 62 ******************/
philpem@30 63
philpem@30 64 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
philpem@30 65
philpem@30 66 uint32_t mapAddr(uint32_t addr, bool writing)
philpem@30 67 {
philpem@30 68 if (addr < 0x400000) {
philpem@30 69 // RAM access. Check against the Map RAM
philpem@30 70 // Start by getting the original page address
philpem@30 71 uint16_t page = (addr >> 12) & 0x3FF;
philpem@30 72
philpem@30 73 // Look it up in the map RAM and get the physical page address
philpem@30 74 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@30 75
philpem@30 76 // Update the Page Status bits
philpem@30 77 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
philpem@30 78 if (pagebits != 0) {
philpem@30 79 if (writing)
philpem@32 80 state.map[page*2] |= 0x60; // Page written to (dirty)
philpem@30 81 else
philpem@32 82 state.map[page*2] |= 0x40; // Page accessed but not written
philpem@30 83 }
philpem@30 84
philpem@30 85 // Return the address with the new physical page spliced in
philpem@30 86 return (new_page_addr << 12) + (addr & 0xFFF);
philpem@30 87 } else {
philpem@30 88 // I/O, VRAM or MapRAM space; no mapping is performed or required
philpem@30 89 // TODO: assert here?
philpem@30 90 return addr;
philpem@30 91 }
philpem@30 92 }
philpem@30 93
philpem@30 94 typedef enum {
philpem@30 95 MEM_ALLOWED = 0,
philpem@30 96 MEM_PAGEFAULT, // Page fault -- page not present
philpem@30 97 MEM_PAGE_NO_WE, // Page not write enabled
philpem@30 98 MEM_KERNEL, // User attempted to access kernel memory
philpem@30 99 MEM_UIE // User Nonmemory Location Access
philpem@30 100 } MEM_STATUS;
philpem@30 101
philpem@30 102 // check memory access permissions
philpem@30 103 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)
philpem@30 104 {
philpem@30 105 // Are we in Supervisor mode?
philpem@30 106 if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
philpem@30 107 // Yes. We can do anything we like.
philpem@30 108 return MEM_ALLOWED;
philpem@30 109
philpem@30 110 // If we're here, then we must be in User mode.
philpem@30 111 // Check that the user didn't access memory outside of the RAM area
philpem@30 112 if (addr >= 0x400000)
philpem@30 113 return MEM_UIE;
philpem@30 114
philpem@30 115 // This leaves us with Page Fault checking. Get the page bits for this page.
philpem@30 116 uint16_t page = (addr >> 12) & 0x3FF;
philpem@30 117 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
philpem@30 118
philpem@30 119 // Check page is present
philpem@30 120 if ((pagebits & 0x03) == 0)
philpem@30 121 return MEM_PAGEFAULT;
philpem@30 122
philpem@30 123 // User attempt to access the kernel
philpem@30 124 // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
philpem@30 125 if (((addr >> 19) & 0x0F) == 0)
philpem@30 126 return MEM_KERNEL;
philpem@30 127
philpem@30 128 // Check page is write enabled
philpem@30 129 if ((pagebits & 0x04) == 0)
philpem@30 130 return MEM_PAGE_NO_WE;
philpem@30 131
philpem@30 132 // Page access allowed.
philpem@30 133 return MEM_ALLOWED;
philpem@30 134 }
philpem@30 135
philpem@30 136 #undef MAPRAM
philpem@26 137
philpem@26 138 /********************************************************
philpem@26 139 * m68k memory read/write support functions for Musashi
philpem@26 140 ********************************************************/
philpem@26 141
philpem@32 142 /**
philpem@32 143 * @brief Check memory access permissions for a write operation.
philpem@32 144 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
philpem@32 145 * gcc throws warnings when you have a return-with-value in a void
philpem@32 146 * function, even if the return-with-value is completely unreachable.
philpem@32 147 * Similarly it doesn't like it if you have a return without a value
philpem@32 148 * in a non-void function, even if it's impossible to ever reach the
philpem@32 149 * return-with-no-value. UGH!
philpem@32 150 */
philpem@37 151 #define ACCESS_CHECK_WR(address, bits) do { \
philpem@37 152 bool fault = false; \
philpem@37 153 /* MEM_STATUS st; */ \
philpem@37 154 switch (checkMemoryAccess(address, true)) { \
philpem@37 155 case MEM_ALLOWED: \
philpem@37 156 /* Access allowed */ \
philpem@37 157 break; \
philpem@37 158 case MEM_PAGEFAULT: \
philpem@37 159 /* Page fault */ \
philpem@37 160 state.genstat = 0x8FFF; \
philpem@37 161 fault = true; \
philpem@37 162 break; \
philpem@37 163 case MEM_UIE: \
philpem@37 164 /* User access to memory above 4MB */ \
philpem@37 165 state.genstat = 0x9EFF; \
philpem@37 166 fault = true; \
philpem@37 167 break; \
philpem@37 168 case MEM_KERNEL: \
philpem@37 169 case MEM_PAGE_NO_WE: \
philpem@37 170 /* kernel access or page not write enabled */ \
philpem@37 171 /* TODO: which regs need setting? */ \
philpem@37 172 fault = true; \
philpem@37 173 break; \
philpem@37 174 } \
philpem@37 175 \
philpem@37 176 if (fault) { \
philpem@37 177 if (bits >= 16) \
philpem@37 178 state.bsr0 = 0x7F00; \
philpem@37 179 else \
philpem@37 180 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
philpem@37 181 state.bsr0 |= (address >> 16); \
philpem@37 182 state.bsr1 = address & 0xffff; \
philpem@37 183 printf("ERR: BusError WR\n"); \
philpem@37 184 m68k_pulse_bus_error(); \
philpem@37 185 return; \
philpem@37 186 } \
philpem@32 187 } while (false)
philpem@32 188
philpem@32 189 /**
philpem@32 190 * @brief Check memory access permissions for a read operation.
philpem@32 191 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
philpem@32 192 * gcc throws warnings when you have a return-with-value in a void
philpem@32 193 * function, even if the return-with-value is completely unreachable.
philpem@32 194 * Similarly it doesn't like it if you have a return without a value
philpem@32 195 * in a non-void function, even if it's impossible to ever reach the
philpem@32 196 * return-with-no-value. UGH!
philpem@32 197 */
philpem@37 198 #define ACCESS_CHECK_RD(address, bits) do { \
philpem@37 199 bool fault = false; \
philpem@37 200 /* MEM_STATUS st; */ \
philpem@37 201 switch (checkMemoryAccess(address, false)) { \
philpem@37 202 case MEM_ALLOWED: \
philpem@37 203 /* Access allowed */ \
philpem@37 204 break; \
philpem@37 205 case MEM_PAGEFAULT: \
philpem@37 206 /* Page fault */ \
philpem@37 207 state.genstat = 0x8FFF; \
philpem@37 208 fault = true; \
philpem@37 209 break; \
philpem@37 210 case MEM_UIE: \
philpem@37 211 /* User access to memory above 4MB */ \
philpem@37 212 state.genstat = 0x9EFF; \
philpem@37 213 fault = true; \
philpem@37 214 break; \
philpem@37 215 case MEM_KERNEL: \
philpem@37 216 case MEM_PAGE_NO_WE: \
philpem@37 217 /* kernel access or page not write enabled */ \
philpem@37 218 /* TODO: which regs need setting? */ \
philpem@37 219 fault = true; \
philpem@37 220 break; \
philpem@37 221 } \
philpem@37 222 \
philpem@37 223 if (fault) { \
philpem@37 224 if (bits >= 16) \
philpem@37 225 state.bsr0 = 0x7F00; \
philpem@37 226 else \
philpem@37 227 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
philpem@37 228 state.bsr0 |= (address >> 16); \
philpem@37 229 state.bsr1 = address & 0xffff; \
philpem@37 230 printf("ERR: BusError RD\n"); \
philpem@37 231 m68k_pulse_bus_error(); \
philpem@37 232 return 0xFFFFFFFF; \
philpem@37 233 } \
philpem@32 234 } while (false)
philpem@32 235
philpem@38 236 // Logging macros
philpem@38 237 #define LOG_NOT_HANDLED_R(bits) \
philpem@38 238 do { \
philpem@38 239 if (!handled) \
philpem@38 240 printf("unhandled read%02d, addr=0x%08X\n", bits, address); \
philpem@38 241 } while (0);
philpem@38 242
philpem@38 243 #define LOG_NOT_HANDLED_W(bits) \
philpem@38 244 do { \
philpem@38 245 if (!handled) \
philpem@38 246 printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, value); \
philpem@38 247 } while (0);
philpem@37 248
philpem@32 249 /**
philpem@32 250 * @brief Read M68K memory, 32-bit
philpem@32 251 */
philpem@4 252 uint32_t m68k_read_memory_32(uint32_t address)
philpem@4 253 {
philpem@9 254 uint32_t data = 0xFFFFFFFF;
philpem@38 255 bool handled = false;
philpem@9 256
philpem@7 257 // If ROMLMAP is set, force system to access ROM
philpem@7 258 if (!state.romlmap)
philpem@7 259 address |= 0x800000;
philpem@7 260
philpem@32 261 // Check access permissions
philpem@37 262 ACCESS_CHECK_RD(address, 32);
philpem@32 263
philpem@9 264 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@7 265 // ROM access
philpem@26 266 data = RD32(state.rom, address, ROM_SIZE - 1);
philpem@38 267 handled = true;
philpem@26 268 } else if (address <= (state.ram_size - 1)) {
philpem@32 269 // RAM access
philpem@32 270 data = RD32(state.ram, mapAddr(address, false), state.ram_size - 1);
philpem@38 271 handled = true;
philpem@34 272 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@34 273 // I/O register space, zone A
philpem@34 274 switch (address & 0x0F0000) {
philpem@34 275 case 0x000000: // Map RAM access
philpem@34 276 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
philpem@34 277 data = RD32(state.map, address, 0x7FF);
philpem@38 278 handled = true;
philpem@34 279 break;
philpem@34 280 case 0x010000: // General Status Register
philpem@34 281 data = ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
philpem@38 282 handled = true;
philpem@34 283 break;
philpem@34 284 case 0x020000: // Video RAM
philpem@34 285 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@34 286 data = RD32(state.vram, address, 0x7FFF);
philpem@38 287 handled = true;
philpem@34 288 break;
philpem@34 289 case 0x030000: // Bus Status Register 0
philpem@38 290 data = ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
philpem@38 291 handled = true;
philpem@35 292 break;
philpem@34 293 case 0x040000: // Bus Status Register 1
philpem@38 294 data = ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
philpem@38 295 handled = true;
philpem@35 296 break;
philpem@34 297 case 0x050000: // Phone status
philpem@35 298 break;
philpem@34 299 case 0x060000: // DMA Count
philpem@35 300 break;
philpem@34 301 case 0x070000: // Line Printer Status Register
philpem@35 302 break;
philpem@34 303 case 0x080000: // Real Time Clock
philpem@35 304 break;
philpem@34 305 case 0x090000: // Phone registers
philpem@34 306 switch (address & 0x0FF000) {
philpem@34 307 case 0x090000: // Handset relay
philpem@34 308 case 0x098000:
philpem@35 309 break;
philpem@34 310 case 0x091000: // Line select 2
philpem@34 311 case 0x099000:
philpem@35 312 break;
philpem@34 313 case 0x092000: // Hook relay 1
philpem@34 314 case 0x09A000:
philpem@35 315 break;
philpem@34 316 case 0x093000: // Hook relay 2
philpem@34 317 case 0x09B000:
philpem@35 318 break;
philpem@34 319 case 0x094000: // Line 1 hold
philpem@34 320 case 0x09C000:
philpem@35 321 break;
philpem@34 322 case 0x095000: // Line 2 hold
philpem@34 323 case 0x09D000:
philpem@35 324 break;
philpem@34 325 case 0x096000: // Line 1 A-lead
philpem@34 326 case 0x09E000:
philpem@35 327 break;
philpem@34 328 case 0x097000: // Line 2 A-lead
philpem@34 329 case 0x09F000:
philpem@34 330 break;
philpem@34 331 }
philpem@34 332 break;
philpem@34 333 case 0x0A0000: // Miscellaneous Control Register
philpem@35 334 break;
philpem@34 335 case 0x0B0000: // TM/DIALWR
philpem@35 336 break;
philpem@34 337 case 0x0C0000: // CSR
philpem@35 338 break;
philpem@34 339 case 0x0D0000: // DMA Address Register
philpem@35 340 break;
philpem@34 341 case 0x0E0000: // Disk Control Register
philpem@35 342 break;
philpem@34 343 case 0x0F0000: // Line Printer Data Register
philpem@34 344 break;
philpem@34 345 }
philpem@34 346 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@34 347 // I/O register space, zone B
philpem@34 348 switch (address & 0xF00000) {
philpem@34 349 case 0xC00000: // Expansion slots
philpem@34 350 case 0xD00000:
philpem@34 351 switch (address & 0xFC0000) {
philpem@34 352 case 0xC00000: // Expansion slot 0
philpem@34 353 case 0xC40000: // Expansion slot 1
philpem@34 354 case 0xC80000: // Expansion slot 2
philpem@34 355 case 0xCC0000: // Expansion slot 3
philpem@34 356 case 0xD00000: // Expansion slot 4
philpem@34 357 case 0xD40000: // Expansion slot 5
philpem@34 358 case 0xD80000: // Expansion slot 6
philpem@34 359 case 0xDC0000: // Expansion slot 7
philpem@34 360 fprintf(stderr, "NOTE: RD32 from expansion card space, addr=0x%08X\n", address);
philpem@34 361 break;
philpem@34 362 }
philpem@34 363 break;
philpem@34 364 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@34 365 case 0xF00000:
philpem@34 366 switch (address & 0x070000) {
philpem@34 367 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@34 368 break;
philpem@34 369 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@34 370 break;
philpem@34 371 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@34 372 break;
philpem@34 373 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@34 374 break;
philpem@35 375 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@35 376 switch (address & 0x077000) {
philpem@35 377 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@35 378 break;
philpem@35 379 case 0x041000: // [ef][4c][19]xxx ==> P1E
philpem@35 380 break;
philpem@35 381 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@35 382 break;
philpem@35 383 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@35 384 break;
philpem@35 385 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@35 386 break;
philpem@35 387 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@35 388 break;
philpem@35 389 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@35 390 break;
philpem@35 391 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@35 392 break;
philpem@35 393 }
philpem@38 394 break;
philpem@35 395 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@38 396 break;
philpem@35 397 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@35 398 switch (address & 0x07F000) {
philpem@35 399 default:
philpem@35 400 break;
philpem@35 401 }
philpem@35 402 break;
philpem@35 403 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@38 404 break;
philpem@34 405 }
philpem@34 406 }
philpem@7 407 }
philpem@38 408
philpem@38 409 LOG_NOT_HANDLED_R(32);
philpem@9 410 return data;
philpem@4 411 }
philpem@4 412
philpem@32 413 /**
philpem@32 414 * @brief Read M68K memory, 16-bit
philpem@32 415 */
philpem@4 416 uint32_t m68k_read_memory_16(uint32_t address)
philpem@4 417 {
philpem@9 418 uint16_t data = 0xFFFF;
philpem@38 419 bool handled = false;
philpem@9 420
philpem@9 421 // If ROMLMAP is set, force system to access ROM
philpem@9 422 if (!state.romlmap)
philpem@9 423 address |= 0x800000;
philpem@9 424
philpem@32 425 // Check access permissions
philpem@37 426 ACCESS_CHECK_RD(address, 16);
philpem@32 427
philpem@10 428 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@10 429 // ROM access
philpem@26 430 data = RD16(state.rom, address, ROM_SIZE - 1);
philpem@38 431 handled = true;
philpem@26 432 } else if (address <= (state.ram_size - 1)) {
philpem@32 433 // RAM access
philpem@32 434 data = RD16(state.ram, mapAddr(address, false), state.ram_size - 1);
philpem@38 435 handled = true;
philpem@34 436 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@34 437 // I/O register space, zone A
philpem@34 438 switch (address & 0x0F0000) {
philpem@34 439 case 0x000000: // Map RAM access
philpem@34 440 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
philpem@34 441 data = RD16(state.map, address, 0x7FF);
philpem@38 442 handled = true;
philpem@34 443 break;
philpem@34 444 case 0x010000: // General Status Register
philpem@34 445 data = state.genstat;
philpem@38 446 handled = true;
philpem@34 447 break;
philpem@34 448 case 0x020000: // Video RAM
philpem@34 449 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@34 450 data = RD16(state.vram, address, 0x7FFF);
philpem@38 451 handled = true;
philpem@34 452 break;
philpem@34 453 case 0x030000: // Bus Status Register 0
philpem@38 454 data = state.bsr0;
philpem@38 455 handled = true;
philpem@35 456 break;
philpem@34 457 case 0x040000: // Bus Status Register 1
philpem@38 458 data = state.bsr1;
philpem@38 459 handled = true;
philpem@35 460 break;
philpem@34 461 case 0x050000: // Phone status
philpem@35 462 break;
philpem@34 463 case 0x060000: // DMA Count
philpem@35 464 break;
philpem@34 465 case 0x070000: // Line Printer Status Register
philpem@35 466 break;
philpem@34 467 case 0x080000: // Real Time Clock
philpem@35 468 break;
philpem@34 469 case 0x090000: // Phone registers
philpem@34 470 switch (address & 0x0FF000) {
philpem@34 471 case 0x090000: // Handset relay
philpem@34 472 case 0x098000:
philpem@35 473 break;
philpem@34 474 case 0x091000: // Line select 2
philpem@34 475 case 0x099000:
philpem@35 476 break;
philpem@34 477 case 0x092000: // Hook relay 1
philpem@34 478 case 0x09A000:
philpem@35 479 break;
philpem@34 480 case 0x093000: // Hook relay 2
philpem@34 481 case 0x09B000:
philpem@35 482 break;
philpem@34 483 case 0x094000: // Line 1 hold
philpem@34 484 case 0x09C000:
philpem@35 485 break;
philpem@34 486 case 0x095000: // Line 2 hold
philpem@34 487 case 0x09D000:
philpem@35 488 break;
philpem@34 489 case 0x096000: // Line 1 A-lead
philpem@34 490 case 0x09E000:
philpem@35 491 break;
philpem@34 492 case 0x097000: // Line 2 A-lead
philpem@34 493 case 0x09F000:
philpem@34 494 break;
philpem@34 495 }
philpem@34 496 break;
philpem@34 497 case 0x0A0000: // Miscellaneous Control Register
philpem@35 498 break;
philpem@34 499 case 0x0B0000: // TM/DIALWR
philpem@35 500 break;
philpem@34 501 case 0x0C0000: // CSR
philpem@35 502 break;
philpem@34 503 case 0x0D0000: // DMA Address Register
philpem@35 504 break;
philpem@34 505 case 0x0E0000: // Disk Control Register
philpem@35 506 break;
philpem@34 507 case 0x0F0000: // Line Printer Data Register
philpem@34 508 break;
philpem@34 509 }
philpem@34 510 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@34 511 // I/O register space, zone B
philpem@34 512 switch (address & 0xF00000) {
philpem@34 513 case 0xC00000: // Expansion slots
philpem@34 514 case 0xD00000:
philpem@34 515 switch (address & 0xFC0000) {
philpem@34 516 case 0xC00000: // Expansion slot 0
philpem@34 517 case 0xC40000: // Expansion slot 1
philpem@34 518 case 0xC80000: // Expansion slot 2
philpem@34 519 case 0xCC0000: // Expansion slot 3
philpem@34 520 case 0xD00000: // Expansion slot 4
philpem@34 521 case 0xD40000: // Expansion slot 5
philpem@34 522 case 0xD80000: // Expansion slot 6
philpem@34 523 case 0xDC0000: // Expansion slot 7
philpem@34 524 fprintf(stderr, "NOTE: RD16 from expansion card space, addr=0x%08X\n", address);
philpem@34 525 break;
philpem@34 526 }
philpem@34 527 break;
philpem@34 528 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@34 529 case 0xF00000:
philpem@34 530 switch (address & 0x070000) {
philpem@34 531 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@34 532 break;
philpem@34 533 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@34 534 break;
philpem@34 535 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@34 536 break;
philpem@34 537 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@34 538 break;
philpem@35 539 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@35 540 switch (address & 0x077000) {
philpem@35 541 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@35 542 break;
philpem@35 543 case 0x041000: // [ef][4c][19]xxx ==> P1E
philpem@35 544 break;
philpem@35 545 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@35 546 break;
philpem@35 547 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@35 548 break;
philpem@35 549 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@35 550 break;
philpem@35 551 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@35 552 break;
philpem@35 553 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@35 554 break;
philpem@35 555 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@35 556 break;
philpem@35 557 }
philpem@38 558 break;
philpem@35 559 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@38 560 break;
philpem@35 561 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@35 562 switch (address & 0x07F000) {
philpem@35 563 default:
philpem@35 564 break;
philpem@35 565 }
philpem@35 566 break;
philpem@35 567 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@38 568 break;
philpem@34 569 }
philpem@34 570 }
philpem@10 571 }
philpem@38 572
philpem@38 573 LOG_NOT_HANDLED_R(32);
philpem@9 574 return data;
philpem@4 575 }
philpem@4 576
philpem@32 577 /**
philpem@32 578 * @brief Read M68K memory, 8-bit
philpem@32 579 */
philpem@4 580 uint32_t m68k_read_memory_8(uint32_t address)
philpem@4 581 {
philpem@9 582 uint8_t data = 0xFF;
philpem@38 583 bool handled = false;
philpem@9 584
philpem@7 585 // If ROMLMAP is set, force system to access ROM
philpem@7 586 if (!state.romlmap)
philpem@7 587 address |= 0x800000;
philpem@7 588
philpem@32 589 // Check access permissions
philpem@37 590 ACCESS_CHECK_RD(address, 8);
philpem@32 591
philpem@10 592 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@10 593 // ROM access
philpem@26 594 data = RD8(state.rom, address, ROM_SIZE - 1);
philpem@38 595 handled = true;
philpem@26 596 } else if (address <= (state.ram_size - 1)) {
philpem@32 597 // RAM access
philpem@32 598 data = RD8(state.ram, mapAddr(address, false), state.ram_size - 1);
philpem@38 599 handled = true;
philpem@34 600 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@34 601 // I/O register space, zone A
philpem@34 602 switch (address & 0x0F0000) {
philpem@34 603 case 0x000000: // Map RAM access
philpem@34 604 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
philpem@34 605 data = RD8(state.map, address, 0x7FF);
philpem@38 606 handled = true;
philpem@34 607 break;
philpem@34 608 case 0x010000: // General Status Register
philpem@34 609 if ((address & 1) == 0)
philpem@34 610 data = (state.genstat >> 8) & 0xff;
philpem@34 611 else
philpem@34 612 data = (state.genstat) & 0xff;
philpem@38 613 handled = true;
philpem@34 614 break;
philpem@34 615 case 0x020000: // Video RAM
philpem@34 616 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@34 617 data = RD8(state.vram, address, 0x7FFF);
philpem@38 618 handled = true;
philpem@38 619 break;
philpem@38 620 case 0x030000: // Bus Status Register 0
philpem@38 621 if ((address & 1) == 0)
philpem@38 622 data = (state.bsr0 >> 8) & 0xff;
philpem@38 623 else
philpem@38 624 data = (state.bsr0) & 0xff;
philpem@38 625 handled = true;
philpem@38 626 break;
philpem@38 627 case 0x040000: // Bus Status Register 1
philpem@38 628 if ((address & 1) == 0)
philpem@38 629 data = (state.bsr1 >> 8) & 0xff;
philpem@38 630 else
philpem@38 631 data = (state.bsr1) & 0xff;
philpem@38 632 handled = true;
philpem@38 633 break;
philpem@38 634 case 0x050000: // Phone status
philpem@38 635 break;
philpem@38 636 case 0x060000: // DMA Count
philpem@38 637 break;
philpem@38 638 case 0x070000: // Line Printer Status Register
philpem@38 639 break;
philpem@38 640 case 0x080000: // Real Time Clock
philpem@38 641 break;
philpem@38 642 case 0x090000: // Phone registers
philpem@38 643 switch (address & 0x0FF000) {
philpem@38 644 case 0x090000: // Handset relay
philpem@38 645 case 0x098000:
philpem@38 646 break;
philpem@38 647 case 0x091000: // Line select 2
philpem@38 648 case 0x099000:
philpem@38 649 break;
philpem@38 650 case 0x092000: // Hook relay 1
philpem@38 651 case 0x09A000:
philpem@38 652 break;
philpem@38 653 case 0x093000: // Hook relay 2
philpem@38 654 case 0x09B000:
philpem@38 655 break;
philpem@38 656 case 0x094000: // Line 1 hold
philpem@38 657 case 0x09C000:
philpem@38 658 break;
philpem@38 659 case 0x095000: // Line 2 hold
philpem@38 660 case 0x09D000:
philpem@38 661 break;
philpem@38 662 case 0x096000: // Line 1 A-lead
philpem@38 663 case 0x09E000:
philpem@38 664 break;
philpem@38 665 case 0x097000: // Line 2 A-lead
philpem@38 666 case 0x09F000:
philpem@38 667 break;
philpem@38 668 }
philpem@38 669 break;
philpem@38 670 case 0x0A0000: // Miscellaneous Control Register
philpem@38 671 break;
philpem@38 672 case 0x0B0000: // TM/DIALWR
philpem@38 673 break;
philpem@38 674 case 0x0C0000: // CSR
philpem@38 675 break;
philpem@38 676 case 0x0D0000: // DMA Address Register
philpem@38 677 break;
philpem@38 678 case 0x0E0000: // Disk Control Register
philpem@38 679 break;
philpem@38 680 case 0x0F0000: // Line Printer Data Register
philpem@38 681 break;
philpem@38 682 }
philpem@38 683 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@38 684 // I/O register space, zone B
philpem@38 685 switch (address & 0xF00000) {
philpem@38 686 case 0xC00000: // Expansion slots
philpem@38 687 case 0xD00000:
philpem@38 688 switch (address & 0xFC0000) {
philpem@38 689 case 0xC00000: // Expansion slot 0
philpem@38 690 case 0xC40000: // Expansion slot 1
philpem@38 691 case 0xC80000: // Expansion slot 2
philpem@38 692 case 0xCC0000: // Expansion slot 3
philpem@38 693 case 0xD00000: // Expansion slot 4
philpem@38 694 case 0xD40000: // Expansion slot 5
philpem@38 695 case 0xD80000: // Expansion slot 6
philpem@38 696 case 0xDC0000: // Expansion slot 7
philpem@38 697 fprintf(stderr, "NOTE: RD8 from expansion card space, addr=0x%08X\n", address);
philpem@38 698 break;
philpem@38 699 }
philpem@38 700 break;
philpem@38 701 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@38 702 case 0xF00000:
philpem@38 703 switch (address & 0x070000) {
philpem@38 704 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@38 705 break;
philpem@38 706 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@38 707 break;
philpem@38 708 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@38 709 break;
philpem@38 710 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@38 711 break;
philpem@38 712 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@38 713 switch (address & 0x077000) {
philpem@38 714 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@38 715 break;
philpem@38 716 case 0x041000: // [ef][4c][19]xxx ==> P1E
philpem@38 717 break;
philpem@38 718 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@38 719 break;
philpem@38 720 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@38 721 break;
philpem@38 722 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@38 723 break;
philpem@38 724 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@38 725 break;
philpem@38 726 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@38 727 break;
philpem@38 728 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@38 729 break;
philpem@38 730 }
philpem@38 731 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@38 732 break;
philpem@38 733 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@38 734 switch (address & 0x07F000) {
philpem@38 735 default:
philpem@38 736 break;
philpem@38 737 }
philpem@38 738 break;
philpem@38 739 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@38 740 break;
philpem@38 741 }
philpem@38 742 }
philpem@38 743 }
philpem@38 744
philpem@38 745 LOG_NOT_HANDLED_R(8);
philpem@38 746
philpem@38 747 return data;
philpem@38 748 }
philpem@38 749
philpem@38 750 /**
philpem@38 751 * @brief Write M68K memory, 32-bit
philpem@38 752 */
philpem@38 753 void m68k_write_memory_32(uint32_t address, uint32_t value)
philpem@38 754 {
philpem@38 755 bool handled = false;
philpem@38 756
philpem@38 757 // If ROMLMAP is set, force system to access ROM
philpem@38 758 if (!state.romlmap)
philpem@38 759 address |= 0x800000;
philpem@38 760
philpem@38 761 // Check access permissions
philpem@38 762 ACCESS_CHECK_WR(address, 32);
philpem@38 763
philpem@38 764 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@38 765 // ROM access
philpem@38 766 handled = true;
philpem@38 767 } else if (address <= (state.ram_size - 1)) {
philpem@38 768 // RAM access
philpem@38 769 WR32(state.ram, mapAddr(address, false), state.ram_size - 1, value);
philpem@38 770 handled = true;
philpem@38 771 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@38 772 // I/O register space, zone A
philpem@38 773 switch (address & 0x0F0000) {
philpem@38 774 case 0x000000: // Map RAM access
philpem@38 775 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
philpem@38 776 WR32(state.map, address, 0x7FF, value);
philpem@38 777 handled = true;
philpem@38 778 break;
philpem@38 779 case 0x010000: // General Status Register
philpem@38 780 state.genstat = (value & 0xffff);
philpem@38 781 handled = true;
philpem@38 782 break;
philpem@38 783 case 0x020000: // Video RAM
philpem@38 784 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
philpem@38 785 WR32(state.vram, address, 0x7FFF, value);
philpem@38 786 handled = true;
philpem@34 787 break;
philpem@34 788 case 0x030000: // Bus Status Register 0
philpem@35 789 break;
philpem@34 790 case 0x040000: // Bus Status Register 1
philpem@35 791 break;
philpem@34 792 case 0x050000: // Phone status
philpem@35 793 break;
philpem@34 794 case 0x060000: // DMA Count
philpem@35 795 break;
philpem@34 796 case 0x070000: // Line Printer Status Register
philpem@35 797 break;
philpem@34 798 case 0x080000: // Real Time Clock
philpem@35 799 break;
philpem@34 800 case 0x090000: // Phone registers
philpem@34 801 switch (address & 0x0FF000) {
philpem@34 802 case 0x090000: // Handset relay
philpem@34 803 case 0x098000:
philpem@35 804 break;
philpem@34 805 case 0x091000: // Line select 2
philpem@34 806 case 0x099000:
philpem@35 807 break;
philpem@34 808 case 0x092000: // Hook relay 1
philpem@34 809 case 0x09A000:
philpem@35 810 break;
philpem@34 811 case 0x093000: // Hook relay 2
philpem@34 812 case 0x09B000:
philpem@35 813 break;
philpem@34 814 case 0x094000: // Line 1 hold
philpem@34 815 case 0x09C000:
philpem@35 816 break;
philpem@34 817 case 0x095000: // Line 2 hold
philpem@34 818 case 0x09D000:
philpem@35 819 break;
philpem@34 820 case 0x096000: // Line 1 A-lead
philpem@34 821 case 0x09E000:
philpem@35 822 break;
philpem@34 823 case 0x097000: // Line 2 A-lead
philpem@34 824 case 0x09F000:
philpem@34 825 break;
philpem@34 826 }
philpem@34 827 break;
philpem@34 828 case 0x0A0000: // Miscellaneous Control Register
philpem@35 829 break;
philpem@34 830 case 0x0B0000: // TM/DIALWR
philpem@35 831 break;
philpem@34 832 case 0x0C0000: // CSR
philpem@35 833 break;
philpem@34 834 case 0x0D0000: // DMA Address Register
philpem@35 835 break;
philpem@34 836 case 0x0E0000: // Disk Control Register
philpem@35 837 break;
philpem@34 838 case 0x0F0000: // Line Printer Data Register
philpem@34 839 break;
philpem@34 840 }
philpem@34 841 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@34 842 // I/O register space, zone B
philpem@34 843 switch (address & 0xF00000) {
philpem@34 844 case 0xC00000: // Expansion slots
philpem@34 845 case 0xD00000:
philpem@34 846 switch (address & 0xFC0000) {
philpem@34 847 case 0xC00000: // Expansion slot 0
philpem@34 848 case 0xC40000: // Expansion slot 1
philpem@34 849 case 0xC80000: // Expansion slot 2
philpem@34 850 case 0xCC0000: // Expansion slot 3
philpem@34 851 case 0xD00000: // Expansion slot 4
philpem@34 852 case 0xD40000: // Expansion slot 5
philpem@34 853 case 0xD80000: // Expansion slot 6
philpem@34 854 case 0xDC0000: // Expansion slot 7
philpem@38 855 fprintf(stderr, "NOTE: WR32 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
philpem@38 856 handled = true;
philpem@34 857 break;
philpem@34 858 }
philpem@34 859 break;
philpem@34 860 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@34 861 case 0xF00000:
philpem@34 862 switch (address & 0x070000) {
philpem@34 863 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@34 864 break;
philpem@34 865 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@34 866 break;
philpem@34 867 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@34 868 break;
philpem@34 869 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@34 870 break;
philpem@35 871 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@35 872 switch (address & 0x077000) {
philpem@35 873 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@35 874 break;
philpem@35 875 case 0x041000: // [ef][4c][19]xxx ==> P1E
philpem@35 876 break;
philpem@35 877 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@35 878 break;
philpem@35 879 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@38 880 state.romlmap = ((value & 0x8000) == 0x8000);
philpem@35 881 break;
philpem@35 882 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@35 883 break;
philpem@35 884 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@35 885 break;
philpem@35 886 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@35 887 break;
philpem@35 888 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@35 889 break;
philpem@35 890 }
philpem@35 891 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@38 892 break;
philpem@35 893 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@35 894 switch (address & 0x07F000) {
philpem@35 895 default:
philpem@35 896 break;
philpem@35 897 }
philpem@35 898 break;
philpem@35 899 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@38 900 break;
philpem@34 901 }
philpem@34 902 }
philpem@10 903 }
philpem@38 904
philpem@38 905 LOG_NOT_HANDLED_W(32);
philpem@4 906 }
philpem@4 907
philpem@32 908 /**
philpem@38 909 * @brief Write M68K memory, 16-bit
philpem@32 910 */
philpem@38 911 void m68k_write_memory_16(uint32_t address, uint32_t value)
philpem@4 912 {
philpem@38 913 bool handled = false;
philpem@38 914
philpem@7 915 // If ROMLMAP is set, force system to access ROM
philpem@7 916 if (!state.romlmap)
philpem@7 917 address |= 0x800000;
philpem@7 918
philpem@32 919 // Check access permissions
philpem@38 920 ACCESS_CHECK_WR(address, 16);
philpem@32 921
philpem@9 922 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@7 923 // ROM access
philpem@38 924 handled = true;
philpem@26 925 } else if (address <= (state.ram_size - 1)) {
philpem@32 926 // RAM access
philpem@38 927 WR16(state.ram, mapAddr(address, false), state.ram_size - 1, value);
philpem@38 928 handled = true;
philpem@34 929 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@34 930 // I/O register space, zone A
philpem@34 931 switch (address & 0x0F0000) {
philpem@34 932 case 0x000000: // Map RAM access
philpem@38 933 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@38 934 WR16(state.map, address, 0x7FF, value);
philpem@38 935 handled = true;
philpem@34 936 break;
philpem@38 937 case 0x010000: // General Status Register (read only)
philpem@38 938 handled = true;
philpem@34 939 break;
philpem@34 940 case 0x020000: // Video RAM
philpem@38 941 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@38 942 WR16(state.vram, address, 0x7FFF, value);
philpem@38 943 handled = true;
philpem@34 944 break;
philpem@38 945 case 0x030000: // Bus Status Register 0 (read only)
philpem@38 946 handled = true;
philpem@35 947 break;
philpem@38 948 case 0x040000: // Bus Status Register 1 (read only)
philpem@38 949 handled = true;
philpem@35 950 break;
philpem@34 951 case 0x050000: // Phone status
philpem@35 952 break;
philpem@34 953 case 0x060000: // DMA Count
philpem@35 954 break;
philpem@34 955 case 0x070000: // Line Printer Status Register
philpem@35 956 break;
philpem@34 957 case 0x080000: // Real Time Clock
philpem@35 958 break;
philpem@34 959 case 0x090000: // Phone registers
philpem@34 960 switch (address & 0x0FF000) {
philpem@34 961 case 0x090000: // Handset relay
philpem@34 962 case 0x098000:
philpem@35 963 break;
philpem@34 964 case 0x091000: // Line select 2
philpem@34 965 case 0x099000:
philpem@35 966 break;
philpem@34 967 case 0x092000: // Hook relay 1
philpem@34 968 case 0x09A000:
philpem@35 969 break;
philpem@34 970 case 0x093000: // Hook relay 2
philpem@34 971 case 0x09B000:
philpem@35 972 break;
philpem@34 973 case 0x094000: // Line 1 hold
philpem@34 974 case 0x09C000:
philpem@35 975 break;
philpem@34 976 case 0x095000: // Line 2 hold
philpem@34 977 case 0x09D000:
philpem@35 978 break;
philpem@34 979 case 0x096000: // Line 1 A-lead
philpem@34 980 case 0x09E000:
philpem@35 981 break;
philpem@34 982 case 0x097000: // Line 2 A-lead
philpem@34 983 case 0x09F000:
philpem@34 984 break;
philpem@34 985 }
philpem@34 986 break;
philpem@34 987 case 0x0A0000: // Miscellaneous Control Register
philpem@35 988 break;
philpem@34 989 case 0x0B0000: // TM/DIALWR
philpem@35 990 break;
philpem@34 991 case 0x0C0000: // CSR
philpem@35 992 break;
philpem@34 993 case 0x0D0000: // DMA Address Register
philpem@35 994 break;
philpem@34 995 case 0x0E0000: // Disk Control Register
philpem@35 996 break;
philpem@34 997 case 0x0F0000: // Line Printer Data Register
philpem@34 998 break;
philpem@34 999 }
philpem@34 1000 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@34 1001 // I/O register space, zone B
philpem@34 1002 switch (address & 0xF00000) {
philpem@34 1003 case 0xC00000: // Expansion slots
philpem@34 1004 case 0xD00000:
philpem@34 1005 switch (address & 0xFC0000) {
philpem@34 1006 case 0xC00000: // Expansion slot 0
philpem@34 1007 case 0xC40000: // Expansion slot 1
philpem@34 1008 case 0xC80000: // Expansion slot 2
philpem@34 1009 case 0xCC0000: // Expansion slot 3
philpem@34 1010 case 0xD00000: // Expansion slot 4
philpem@34 1011 case 0xD40000: // Expansion slot 5
philpem@34 1012 case 0xD80000: // Expansion slot 6
philpem@34 1013 case 0xDC0000: // Expansion slot 7
philpem@38 1014 fprintf(stderr, "NOTE: WR16 to expansion card space, addr=0x%08X, data=0x%04X\n", address, value);
philpem@34 1015 break;
philpem@34 1016 }
philpem@34 1017 break;
philpem@34 1018 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@34 1019 case 0xF00000:
philpem@34 1020 switch (address & 0x070000) {
philpem@34 1021 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@34 1022 break;
philpem@34 1023 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@34 1024 break;
philpem@34 1025 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@34 1026 break;
philpem@34 1027 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@34 1028 break;
philpem@35 1029 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@35 1030 switch (address & 0x077000) {
philpem@35 1031 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@35 1032 break;
philpem@35 1033 case 0x041000: // [ef][4c][19]xxx ==> P1E
philpem@35 1034 break;
philpem@35 1035 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@35 1036 break;
philpem@35 1037 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@35 1038 state.romlmap = ((value & 0x8000) == 0x8000);
philpem@38 1039 handled = true;
philpem@35 1040 break;
philpem@35 1041 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@35 1042 break;
philpem@35 1043 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@35 1044 break;
philpem@35 1045 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@35 1046 break;
philpem@35 1047 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@35 1048 break;
philpem@35 1049 }
philpem@35 1050 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@35 1051 break;
philpem@35 1052 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@35 1053 switch (address & 0x07F000) {
philpem@35 1054 default:
philpem@35 1055 break;
philpem@35 1056 }
philpem@35 1057 break;
philpem@35 1058 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@35 1059 break;
philpem@34 1060 }
philpem@9 1061 }
philpem@7 1062 }
philpem@38 1063
philpem@38 1064 LOG_NOT_HANDLED_W(16);
philpem@4 1065 }
philpem@4 1066
philpem@32 1067 /**
philpem@38 1068 * @brief Write M68K memory, 8-bit
philpem@32 1069 */
philpem@38 1070 void m68k_write_memory_8(uint32_t address, uint32_t value)
philpem@4 1071 {
philpem@38 1072 bool handled = false;
philpem@38 1073
philpem@7 1074 // If ROMLMAP is set, force system to access ROM
philpem@7 1075 if (!state.romlmap)
philpem@7 1076 address |= 0x800000;
philpem@7 1077
philpem@32 1078 // Check access permissions
philpem@38 1079 ACCESS_CHECK_WR(address, 8);
philpem@32 1080
philpem@9 1081 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@38 1082 // ROM access (read only!)
philpem@38 1083 handled = true;
philpem@26 1084 } else if (address <= (state.ram_size - 1)) {
philpem@32 1085 // RAM access
philpem@38 1086 WR8(state.ram, mapAddr(address, false), state.ram_size - 1, value);
philpem@38 1087 handled = true;
philpem@34 1088 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@34 1089 // I/O register space, zone A
philpem@34 1090 switch (address & 0x0F0000) {
philpem@34 1091 case 0x000000: // Map RAM access
philpem@38 1092 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=%08X, data=%02X\n", address, value);
philpem@38 1093 WR8(state.map, address, 0x7FF, value);
philpem@38 1094 handled = true;
philpem@34 1095 break;
philpem@34 1096 case 0x010000: // General Status Register
philpem@38 1097 handled = true;
philpem@34 1098 break;
philpem@34 1099 case 0x020000: // Video RAM
philpem@38 1100 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=%08X\n, data=0x%02X", address, value);
philpem@38 1101 WR8(state.vram, address, 0x7FFF, value);
philpem@38 1102 handled = true;
philpem@34 1103 break;
philpem@34 1104 case 0x030000: // Bus Status Register 0
philpem@38 1105 handled = true;
philpem@35 1106 break;
philpem@34 1107 case 0x040000: // Bus Status Register 1
philpem@38 1108 handled = true;
philpem@35 1109 break;
philpem@34 1110 case 0x050000: // Phone status
philpem@35 1111 break;
philpem@34 1112 case 0x060000: // DMA Count
philpem@35 1113 break;
philpem@34 1114 case 0x070000: // Line Printer Status Register
philpem@35 1115 break;
philpem@34 1116 case 0x080000: // Real Time Clock
philpem@35 1117 break;
philpem@34 1118 case 0x090000: // Phone registers
philpem@34 1119 switch (address & 0x0FF000) {
philpem@34 1120 case 0x090000: // Handset relay
philpem@34 1121 case 0x098000:
philpem@35 1122 break;
philpem@34 1123 case 0x091000: // Line select 2
philpem@34 1124 case 0x099000:
philpem@35 1125 break;
philpem@34 1126 case 0x092000: // Hook relay 1
philpem@34 1127 case 0x09A000:
philpem@35 1128 break;
philpem@34 1129 case 0x093000: // Hook relay 2
philpem@34 1130 case 0x09B000:
philpem@35 1131 break;
philpem@34 1132 case 0x094000: // Line 1 hold
philpem@34 1133 case 0x09C000:
philpem@35 1134 break;
philpem@34 1135 case 0x095000: // Line 2 hold
philpem@34 1136 case 0x09D000:
philpem@35 1137 break;
philpem@34 1138 case 0x096000: // Line 1 A-lead
philpem@34 1139 case 0x09E000:
philpem@35 1140 break;
philpem@34 1141 case 0x097000: // Line 2 A-lead
philpem@34 1142 case 0x09F000:
philpem@34 1143 break;
philpem@34 1144 }
philpem@34 1145 break;
philpem@34 1146 case 0x0A0000: // Miscellaneous Control Register
philpem@35 1147 break;
philpem@34 1148 case 0x0B0000: // TM/DIALWR
philpem@35 1149 break;
philpem@34 1150 case 0x0C0000: // CSR
philpem@35 1151 break;
philpem@34 1152 case 0x0D0000: // DMA Address Register
philpem@35 1153 break;
philpem@34 1154 case 0x0E0000: // Disk Control Register
philpem@35 1155 break;
philpem@34 1156 case 0x0F0000: // Line Printer Data Register
philpem@34 1157 break;
philpem@9 1158 }
philpem@34 1159 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@34 1160 // I/O register space, zone B
philpem@34 1161 switch (address & 0xF00000) {
philpem@34 1162 case 0xC00000: // Expansion slots
philpem@34 1163 case 0xD00000:
philpem@34 1164 switch (address & 0xFC0000) {
philpem@34 1165 case 0xC00000: // Expansion slot 0
philpem@34 1166 case 0xC40000: // Expansion slot 1
philpem@34 1167 case 0xC80000: // Expansion slot 2
philpem@34 1168 case 0xCC0000: // Expansion slot 3
philpem@34 1169 case 0xD00000: // Expansion slot 4
philpem@34 1170 case 0xD40000: // Expansion slot 5
philpem@34 1171 case 0xD80000: // Expansion slot 6
philpem@34 1172 case 0xDC0000: // Expansion slot 7
philpem@34 1173 fprintf(stderr, "NOTE: WR8 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
philpem@34 1174 break;
philpem@34 1175 }
philpem@34 1176 break;
philpem@34 1177 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@34 1178 case 0xF00000:
philpem@34 1179 switch (address & 0x070000) {
philpem@34 1180 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@34 1181 break;
philpem@34 1182 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@34 1183 break;
philpem@34 1184 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@34 1185 break;
philpem@34 1186 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@34 1187 break;
philpem@35 1188 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@35 1189 switch (address & 0x077000) {
philpem@35 1190 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@35 1191 break;
philpem@35 1192 case 0x041000: // [ef][4c][19]xxx ==> P1E
philpem@35 1193 break;
philpem@35 1194 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@35 1195 break;
philpem@35 1196 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@35 1197 if ((address & 1) == 0)
philpem@38 1198 state.romlmap = ((value & 0x80) == 0x80);
philpem@38 1199 handled = true;
philpem@35 1200 break;
philpem@35 1201 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@35 1202 break;
philpem@35 1203 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@35 1204 break;
philpem@35 1205 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@35 1206 break;
philpem@35 1207 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@35 1208 break;
philpem@35 1209 }
philpem@35 1210 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@35 1211 break;
philpem@35 1212 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@35 1213 switch (address & 0x07F000) {
philpem@35 1214 default:
philpem@35 1215 break;
philpem@35 1216 }
philpem@35 1217 break;
philpem@35 1218 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@35 1219 break;
philpem@34 1220 default:
philpem@34 1221 fprintf(stderr, "NOTE: WR8 to undefined E/F-block space, addr=0x%08X, data=0x%08X\n", address, value);
philpem@35 1222 break;
philpem@34 1223 }
philpem@9 1224 }
philpem@7 1225 }
philpem@38 1226
philpem@38 1227 LOG_NOT_HANDLED_W(8);
philpem@4 1228 }
philpem@4 1229
philpem@34 1230
philpem@10 1231 // for the disassembler
philpem@9 1232 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
philpem@9 1233 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
philpem@9 1234 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }
philpem@9 1235
philpem@27 1236
philpem@27 1237 /****************************
philpem@27 1238 * blessed be thy main()...
philpem@27 1239 ****************************/
philpem@27 1240
philpem@0 1241 int main(void)
philpem@0 1242 {
philpem@7 1243 // copyright banner
philpem@16 1244 printf("FreeBee: A Quick-and-Dirty AT&T 3B1 Emulator. Version %s, %s mode.\n", VER_FULLSTR, VER_BUILD_TYPE);
philpem@17 1245 printf("Copyright (C) 2010 P. A. Pemberton. All rights reserved.\nLicensed under the Apache License Version 2.0.\n");
philpem@17 1246 printf("Musashi M680x0 emulator engine developed by Karl Stenerud <kstenerud@gmail.com>\n");
philpem@16 1247 printf("Built %s by %s@%s.\n", VER_COMPILE_DATETIME, VER_COMPILE_BY, VER_COMPILE_HOST);
philpem@16 1248 printf("Compiler: %s\n", VER_COMPILER);
philpem@16 1249 printf("CFLAGS: %s\n", VER_CFLAGS);
philpem@17 1250 printf("\n");
philpem@7 1251
philpem@7 1252 // set up system state
philpem@7 1253 // 512K of RAM
philpem@18 1254 state_init(512*1024);
philpem@7 1255
philpem@20 1256 // set up musashi and reset the CPU
philpem@7 1257 m68k_set_cpu_type(M68K_CPU_TYPE_68010);
philpem@7 1258 m68k_pulse_reset();
philpem@9 1259
philpem@28 1260 // Set up SDL
philpem@20 1261 if (SDL_Init(SDL_INIT_VIDEO | SDL_INIT_TIMER) == -1) {
philpem@20 1262 printf("Could not initialise SDL: %s.\n", SDL_GetError());
philpem@28 1263 exit(EXIT_FAILURE);
philpem@20 1264 }
philpem@7 1265
philpem@28 1266 // Make sure SDL cleans up after itself
philpem@28 1267 atexit(SDL_Quit);
philpem@28 1268
philpem@28 1269 // Set up the video display
philpem@28 1270 SDL_Surface *screen = NULL;
philpem@28 1271 if ((screen = SDL_SetVideoMode(720, 384, 8, SDL_SWSURFACE | SDL_ANYFORMAT)) == NULL) {
philpem@28 1272 printf("Could not find a suitable video mode: %s.\n", SDL_GetError());
philpem@28 1273 exit(EXIT_FAILURE);
philpem@28 1274 }
philpem@32 1275 printf("Set %dx%d at %d bits-per-pixel mode\n\n", screen->w, screen->h, screen->format->BitsPerPixel);
philpem@28 1276 SDL_WM_SetCaption("FreeBee 3B1 emulator", "FreeBee");
philpem@28 1277
philpem@20 1278 /***
philpem@20 1279 * The 3B1 CPU runs at 10MHz, with DMA running at 1MHz and video refreshing at
philpem@20 1280 * around 60Hz (???), with a 60Hz periodic interrupt.
philpem@20 1281 */
philpem@20 1282 const uint32_t TIMESLOT_FREQUENCY = 240; // Hz
philpem@20 1283 const uint32_t MILLISECS_PER_TIMESLOT = 1e3 / TIMESLOT_FREQUENCY;
philpem@20 1284 const uint32_t CLOCKS_PER_60HZ = (10e6 / 60);
philpem@20 1285 uint32_t next_timeslot = SDL_GetTicks() + MILLISECS_PER_TIMESLOT;
philpem@20 1286 uint32_t clock_cycles = 0;
philpem@16 1287 bool exitEmu = false;
philpem@16 1288 for (;;) {
philpem@20 1289 // Run the CPU for however many cycles we need to. CPU core clock is
philpem@20 1290 // 10MHz, and we're running at 240Hz/timeslot. Thus: 10e6/240 or
philpem@20 1291 // 41667 cycles per timeslot.
philpem@20 1292 clock_cycles += m68k_execute(10e6/TIMESLOT_FREQUENCY);
philpem@20 1293
philpem@20 1294 // TODO: run DMA here
philpem@16 1295
philpem@20 1296 // Is it time to run the 60Hz periodic interrupt yet?
philpem@20 1297 if (clock_cycles > CLOCKS_PER_60HZ) {
philpem@20 1298 // TODO: refresh screen
philpem@20 1299 // TODO: trigger periodic interrupt (if enabled)
philpem@20 1300 // decrement clock cycle counter, we've handled the intr.
philpem@20 1301 clock_cycles -= CLOCKS_PER_60HZ;
philpem@16 1302 }
philpem@16 1303
philpem@20 1304 // make sure frame rate is equal to real time
philpem@20 1305 uint32_t now = SDL_GetTicks();
philpem@20 1306 if (now < next_timeslot) {
philpem@20 1307 // timeslot finished early -- eat up some time
philpem@20 1308 SDL_Delay(next_timeslot - now);
philpem@20 1309 } else {
philpem@20 1310 // timeslot finished late -- skip ahead to gain time
philpem@20 1311 // TODO: if this happens a lot, we should let the user know
philpem@20 1312 // that their PC might not be fast enough...
philpem@20 1313 next_timeslot = now;
philpem@20 1314 }
philpem@20 1315 // advance to the next timeslot
philpem@20 1316 next_timeslot += MILLISECS_PER_TIMESLOT;
philpem@20 1317
philpem@20 1318 // if we've been asked to exit the emulator, then do so.
philpem@16 1319 if (exitEmu) break;
philpem@16 1320 }
philpem@7 1321
philpem@7 1322 // shut down and exit
philpem@20 1323 SDL_Quit();
philpem@7 1324
philpem@0 1325 return 0;
philpem@0 1326 }