src/wd279x.h

Sun, 05 Dec 2010 03:55:46 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 05 Dec 2010 03:55:46 +0000
changeset 48
d52688dad7fd
child 49
545798274dad
permissions
-rw-r--r--

add preliminary WD2797 FDC emulator

philpem@48 1 #ifndef _WD279X_H
philpem@48 2 #define _WD279X_H
philpem@48 3
philpem@48 4 #include <stdbool.h>
philpem@48 5 #include <stddef.h>
philpem@48 6 #include <stdint.h>
philpem@48 7 #include <stdio.h>
philpem@48 8
philpem@48 9 enum {
philpem@48 10 WD279X_REG_STATUS = 0,
philpem@48 11 WD279X_REG_COMMAND = 0,
philpem@48 12 WD279X_REG_TRACK = 1,
philpem@48 13 WD279X_REG_SECTOR = 2,
philpem@48 14 WD279X_REG_DATA = 3
philpem@48 15 } WD279X_REG;
philpem@48 16
philpem@48 17 typedef struct {
philpem@48 18 // Current track, head and sector
philpem@48 19 int track, head, sector;
philpem@48 20 // Geometry of current disc
philpem@48 21 int geom_secsz, geom_spt, geom_heads, geom_tracks;
philpem@48 22 // IRQ status, level and edge sensitive.
philpem@48 23 // Edge sensitive is cleared when host polls the IRQ status.
philpem@48 24 // Level sensitive is cleared when emulated CPU polls the status reg or writes a new cmnd.
philpem@48 25 // No EDGE sensitive interrupts will be issued unless the LEVEL SENSITIVE IRQ is clear.
philpem@48 26 bool irql, irqe;
philpem@48 27 // Status of last command
philpem@48 28 uint8_t status;
philpem@48 29 // Last command uses DRQ bit?
philpem@48 30 bool cmd_has_drq;
philpem@48 31 // The last value written to the data register
philpem@48 32 uint8_t data_reg;
philpem@48 33 // Last step direction. -1 for "towards zero", 1 for "away from zero"
philpem@48 34 int last_step_dir;
philpem@48 35 // Data buffer, current DRQ pointer and length
philpem@48 36 uint8_t data[1024];
philpem@48 37 size_t data_pos, data_len;
philpem@48 38 // Current disc image file
philpem@48 39 FILE *disc_image;
philpem@48 40 } WD279X_CTX;
philpem@48 41
philpem@48 42 #endif