src/musashi/m68k_in.c

Thu, 11 Apr 2013 09:37:11 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Thu, 11 Apr 2013 09:37:11 +0100
changeset 138
d744db15cdf7
parent 110
acea4b2f396f
permissions
-rw-r--r--

Check return value of fread()

philpem@0 1 /* ======================================================================== */
philpem@0 2 /* ========================= LICENSING & COPYRIGHT ======================== */
philpem@0 3 /* ======================================================================== */
philpem@0 4 /*
philpem@0 5 * MUSASHI
philpem@0 6 * Version 3.3
philpem@0 7 *
philpem@0 8 * A portable Motorola M680x0 processor emulation engine.
philpem@0 9 * Copyright 1998-2001 Karl Stenerud. All rights reserved.
philpem@0 10 *
philpem@0 11 * This code may be freely used for non-commercial purposes as long as this
philpem@0 12 * copyright notice remains unaltered in the source code and any binary files
philpem@0 13 * containing this code in compiled form.
philpem@0 14 *
philpem@0 15 * All other lisencing terms must be negotiated with the author
philpem@0 16 * (Karl Stenerud).
philpem@0 17 *
philpem@0 18 * The latest version of this code can be obtained at:
philpem@0 19 * http://kstenerud.cjb.net
philpem@0 20 */
philpem@0 21
philpem@0 22
philpem@0 23
philpem@0 24 /* Input file for m68kmake
philpem@0 25 * -----------------------
philpem@0 26 *
philpem@0 27 * All sections begin with 80 X's in a row followed by an end-of-line
philpem@0 28 * sequence.
philpem@0 29 * After this, m68kmake will expect to find one of the following section
philpem@0 30 * identifiers:
philpem@0 31 * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes
philpem@0 32 * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes
philpem@0 33 * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable
philpem@0 34 * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable
philpem@0 35 * M68KMAKE_TABLE_BODY - the table itself
philpem@0 36 * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation
philpem@0 37 * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation
philpem@0 38 * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation
philpem@0 39 *
philpem@0 40 * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and
philpem@0 41 * M68KMAKE_TABLE_BODY must be second last in the file.
philpem@0 42 *
philpem@0 43 * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler
philpem@0 44 * primitives themselves. Each opcode handler begins with:
philpem@0 45 * M68KMAKE_OP(A, B, C, D)
philpem@0 46 *
philpem@0 47 * where A is the opcode handler name, B is the size of the operation,
philpem@0 48 * C denotes any special processing mode, and D denotes a specific
philpem@0 49 * addressing mode.
philpem@0 50 * For C and D where nothing is specified, use "."
philpem@0 51 *
philpem@0 52 * Example:
philpem@0 53 * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA
philpem@0 54 * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7
philpem@0 55 * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing
philpem@0 56 *
philpem@0 57 * All opcode handler primitives end with a closing curly brace "}" at column 1
philpem@0 58 *
philpem@0 59 * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,
philpem@0 60 * and do not put a closing curly brace at column 1 unless it is
philpem@0 61 * marking the end of the handler!
philpem@0 62 *
philpem@0 63 * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,
philpem@0 64 * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple
philpem@0 65 * opcode handlers to handle variations in the opcode handler.
philpem@0 66 * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.
philpem@0 67 * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only
philpem@0 68 * be interpreted on instructions where the corresponding table entry
philpem@0 69 * specifies multiple effective addressing modes.
philpem@0 70 * Example:
philpem@0 71 * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
philpem@0 72 *
philpem@0 73 * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).
philpem@0 74 * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for
philpem@0 75 * 68000, 6 cycles for 68010, and 4 cycles for 68020.
philpem@0 76 */
philpem@0 77
philpem@0 78 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
philpem@0 79 M68KMAKE_PROTOTYPE_HEADER
philpem@0 80
philpem@0 81 #ifndef M68KOPS__HEADER
philpem@0 82 #define M68KOPS__HEADER
philpem@0 83
philpem@0 84 /* ======================================================================== */
philpem@0 85 /* ============================ OPCODE HANDLERS =========================== */
philpem@0 86 /* ======================================================================== */
philpem@0 87
philpem@0 88
philpem@0 89
philpem@0 90 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
philpem@0 91 M68KMAKE_PROTOTYPE_FOOTER
philpem@0 92
philpem@0 93
philpem@0 94 /* Build the opcode handler table */
philpem@0 95 void m68ki_build_opcode_table(void);
philpem@0 96
philpem@0 97 extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
philpem@0 98 extern unsigned char m68ki_cycles[][0x10000];
philpem@0 99
philpem@0 100
philpem@0 101 /* ======================================================================== */
philpem@0 102 /* ============================== END OF FILE ============================= */
philpem@0 103 /* ======================================================================== */
philpem@0 104
philpem@0 105 #endif /* M68KOPS__HEADER */
philpem@0 106
philpem@0 107
philpem@0 108
philpem@0 109 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
philpem@0 110 M68KMAKE_TABLE_HEADER
philpem@0 111
philpem@0 112 /* ======================================================================== */
philpem@0 113 /* ========================= OPCODE TABLE BUILDER ========================= */
philpem@0 114 /* ======================================================================== */
philpem@0 115
philpem@0 116 #include "m68kops.h"
philpem@0 117
philpem@0 118 #define NUM_CPU_TYPES 3
philpem@0 119
philpem@0 120 void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
philpem@0 121 unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
philpem@0 122
philpem@0 123 /* This is used to generate the opcode handler jump table */
philpem@0 124 typedef struct
philpem@0 125 {
philpem@0 126 void (*opcode_handler)(void); /* handler function */
philpem@0 127 unsigned int mask; /* mask on opcode */
philpem@0 128 unsigned int match; /* what to match after masking */
philpem@0 129 unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
philpem@0 130 } opcode_handler_struct;
philpem@0 131
philpem@0 132
philpem@0 133 /* Opcode handler table */
philpem@0 134 static opcode_handler_struct m68k_opcode_handler_table[] =
philpem@0 135 {
philpem@0 136 /* function mask match 000 010 020 */
philpem@0 137
philpem@0 138
philpem@0 139
philpem@0 140 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
philpem@0 141 M68KMAKE_TABLE_FOOTER
philpem@0 142
philpem@0 143 {0, 0, 0, {0, 0, 0}}
philpem@0 144 };
philpem@0 145
philpem@0 146
philpem@0 147 /* Build the opcode handler jump table */
philpem@0 148 void m68ki_build_opcode_table(void)
philpem@0 149 {
philpem@0 150 opcode_handler_struct *ostruct;
philpem@0 151 int instr;
philpem@0 152 int i;
philpem@0 153 int j;
philpem@0 154 int k;
philpem@0 155
philpem@0 156 for(i = 0; i < 0x10000; i++)
philpem@0 157 {
philpem@0 158 /* default to illegal */
philpem@0 159 m68ki_instruction_jump_table[i] = m68k_op_illegal;
philpem@0 160 for(k=0;k<NUM_CPU_TYPES;k++)
philpem@0 161 m68ki_cycles[k][i] = 0;
philpem@0 162 }
philpem@0 163
philpem@0 164 ostruct = m68k_opcode_handler_table;
philpem@0 165 while(ostruct->mask != 0xff00)
philpem@0 166 {
philpem@0 167 for(i = 0;i < 0x10000;i++)
philpem@0 168 {
philpem@0 169 if((i & ostruct->mask) == ostruct->match)
philpem@0 170 {
philpem@0 171 m68ki_instruction_jump_table[i] = ostruct->opcode_handler;
philpem@0 172 for(k=0;k<NUM_CPU_TYPES;k++)
philpem@0 173 m68ki_cycles[k][i] = ostruct->cycles[k];
philpem@0 174 }
philpem@0 175 }
philpem@0 176 ostruct++;
philpem@0 177 }
philpem@0 178 while(ostruct->mask == 0xff00)
philpem@0 179 {
philpem@0 180 for(i = 0;i <= 0xff;i++)
philpem@0 181 {
philpem@0 182 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
philpem@0 183 for(k=0;k<NUM_CPU_TYPES;k++)
philpem@0 184 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
philpem@0 185 }
philpem@0 186 ostruct++;
philpem@0 187 }
philpem@0 188 while(ostruct->mask == 0xf1f8)
philpem@0 189 {
philpem@0 190 for(i = 0;i < 8;i++)
philpem@0 191 {
philpem@0 192 for(j = 0;j < 8;j++)
philpem@0 193 {
philpem@0 194 instr = ostruct->match | (i << 9) | j;
philpem@0 195 m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;
philpem@0 196 for(k=0;k<NUM_CPU_TYPES;k++)
philpem@0 197 m68ki_cycles[k][instr] = ostruct->cycles[k];
philpem@0 198 if((instr & 0xf000) == 0xe000 && (!(instr & 0x20)))
philpem@0 199 m68ki_cycles[0][instr] = m68ki_cycles[1][instr] = ostruct->cycles[k] + ((((j-1)&7)+1)<<1);
philpem@0 200 }
philpem@0 201 }
philpem@0 202 ostruct++;
philpem@0 203 }
philpem@0 204 while(ostruct->mask == 0xfff0)
philpem@0 205 {
philpem@0 206 for(i = 0;i <= 0x0f;i++)
philpem@0 207 {
philpem@0 208 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
philpem@0 209 for(k=0;k<NUM_CPU_TYPES;k++)
philpem@0 210 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
philpem@0 211 }
philpem@0 212 ostruct++;
philpem@0 213 }
philpem@0 214 while(ostruct->mask == 0xf1ff)
philpem@0 215 {
philpem@0 216 for(i = 0;i <= 0x07;i++)
philpem@0 217 {
philpem@0 218 m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;
philpem@0 219 for(k=0;k<NUM_CPU_TYPES;k++)
philpem@0 220 m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];
philpem@0 221 }
philpem@0 222 ostruct++;
philpem@0 223 }
philpem@0 224 while(ostruct->mask == 0xfff8)
philpem@0 225 {
philpem@0 226 for(i = 0;i <= 0x07;i++)
philpem@0 227 {
philpem@0 228 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
philpem@0 229 for(k=0;k<NUM_CPU_TYPES;k++)
philpem@0 230 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
philpem@0 231 }
philpem@0 232 ostruct++;
philpem@0 233 }
philpem@0 234 while(ostruct->mask == 0xffff)
philpem@0 235 {
philpem@0 236 m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;
philpem@0 237 for(k=0;k<NUM_CPU_TYPES;k++)
philpem@0 238 m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];
philpem@0 239 ostruct++;
philpem@0 240 }
philpem@0 241 }
philpem@0 242
philpem@0 243
philpem@0 244 /* ======================================================================== */
philpem@0 245 /* ============================== END OF FILE ============================= */
philpem@0 246 /* ======================================================================== */
philpem@0 247
philpem@0 248
philpem@0 249
philpem@0 250 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
philpem@0 251 M68KMAKE_OPCODE_HANDLER_HEADER
philpem@0 252
philpem@0 253 #include "m68kcpu.h"
philpem@0 254
philpem@0 255 /* ======================================================================== */
philpem@0 256 /* ========================= INSTRUCTION HANDLERS ========================= */
philpem@0 257 /* ======================================================================== */
philpem@0 258
philpem@0 259
philpem@0 260
philpem@0 261 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
philpem@0 262 M68KMAKE_OPCODE_HANDLER_FOOTER
philpem@0 263
philpem@0 264 /* ======================================================================== */
philpem@0 265 /* ============================== END OF FILE ============================= */
philpem@0 266 /* ======================================================================== */
philpem@0 267
philpem@0 268
philpem@0 269
philpem@0 270 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
philpem@0 271 M68KMAKE_TABLE_BODY
philpem@0 272
philpem@0 273 The following table is arranged as follows:
philpem@0 274
philpem@0 275 name: Opcode mnemonic
philpem@0 276
philpem@0 277 size: Operation size
philpem@0 278
philpem@0 279 spec proc: Special processing mode:
philpem@0 280 .: normal
philpem@0 281 s: static operand
philpem@0 282 r: register operand
philpem@0 283 rr: register to register
philpem@0 284 mm: memory to memory
philpem@0 285 er: effective address to register
philpem@0 286 re: register to effective address
philpem@0 287 dd: data register to data register
philpem@0 288 da: data register to address register
philpem@0 289 aa: address register to address register
philpem@0 290 cr: control register to register
philpem@0 291 rc: register to control register
philpem@0 292 toc: to condition code register
philpem@0 293 tos: to status register
philpem@0 294 tou: to user stack pointer
philpem@0 295 frc: from condition code register
philpem@0 296 frs: from status register
philpem@0 297 fru: from user stack pointer
philpem@0 298 * for move.x, the special processing mode is a specific
philpem@0 299 destination effective addressing mode.
philpem@0 300
philpem@0 301 spec ea: Specific effective addressing mode:
philpem@0 302 .: normal
philpem@0 303 i: immediate
philpem@0 304 d: data register
philpem@0 305 a: address register
philpem@0 306 ai: address register indirect
philpem@0 307 pi: address register indirect with postincrement
philpem@0 308 pd: address register indirect with predecrement
philpem@0 309 di: address register indirect with displacement
philpem@0 310 ix: address register indirect with index
philpem@0 311 aw: absolute word address
philpem@0 312 al: absolute long address
philpem@0 313 pcdi: program counter relative with displacement
philpem@0 314 pcix: program counter relative with index
philpem@0 315 a7: register specified in instruction is A7
philpem@0 316 ax7: register field X of instruction is A7
philpem@0 317 ay7: register field Y of instruction is A7
philpem@0 318 axy7: register fields X and Y of instruction are A7
philpem@0 319
philpem@0 320 bit pattern: Pattern to recognize this opcode. "." means don't care.
philpem@0 321
philpem@0 322 allowed ea: List of allowed addressing modes:
philpem@0 323 .: not present
philpem@0 324 A: address register indirect
philpem@0 325 +: ARI (address register indirect) with postincrement
philpem@0 326 -: ARI with predecrement
philpem@0 327 D: ARI with displacement
philpem@0 328 X: ARI with index
philpem@0 329 W: absolute word address
philpem@0 330 L: absolute long address
philpem@0 331 d: program counter indirect with displacement
philpem@0 332 x: program counter indirect with index
philpem@0 333 I: immediate
philpem@0 334 mode: CPU operating mode for each cpu type. U = user or supervisor,
philpem@0 335 S = supervisor only, "." = opcode not present.
philpem@0 336
philpem@0 337 cpu cycles: Base number of cycles required to execute this opcode on the
philpem@0 338 specified CPU type.
philpem@0 339 Use "." if CPU does not have this opcode.
philpem@0 340
philpem@0 341
philpem@0 342
philpem@0 343 spec spec allowed ea mode cpu cycles
philpem@0 344 name size proc ea bit pattern A+-DXWLdxI 0 1 2 000 010 020 comments
philpem@0 345 ====== ==== ==== ==== ================ ========== = = = === === === =============
philpem@0 346 M68KMAKE_TABLE_START
philpem@0 347 1010 0 . . 1010............ .......... U U U 4 4 4
philpem@0 348 1111 0 . . 1111............ .......... U U U 4 4 4
philpem@0 349 abcd 8 rr . 1100...100000... .......... U U U 6 6 4
philpem@0 350 abcd 8 mm ax7 1100111100001... .......... U U U 18 18 16
philpem@0 351 abcd 8 mm ay7 1100...100001111 .......... U U U 18 18 16
philpem@0 352 abcd 8 mm axy7 1100111100001111 .......... U U U 18 18 16
philpem@0 353 abcd 8 mm . 1100...100001... .......... U U U 18 18 16
philpem@0 354 add 8 er d 1101...000000... .......... U U U 4 4 2
philpem@0 355 add 8 er . 1101...000...... A+-DXWLdxI U U U 4 4 2
philpem@0 356 add 16 er d 1101...001000... .......... U U U 4 4 2
philpem@0 357 add 16 er a 1101...001001... .......... U U U 4 4 2
philpem@0 358 add 16 er . 1101...001...... A+-DXWLdxI U U U 4 4 2
philpem@0 359 add 32 er d 1101...010000... .......... U U U 6 6 2
philpem@0 360 add 32 er a 1101...010001... .......... U U U 6 6 2
philpem@0 361 add 32 er . 1101...010...... A+-DXWLdxI U U U 6 6 2
philpem@0 362 add 8 re . 1101...100...... A+-DXWL... U U U 8 8 4
philpem@0 363 add 16 re . 1101...101...... A+-DXWL... U U U 8 8 4
philpem@0 364 add 32 re . 1101...110...... A+-DXWL... U U U 12 12 4
philpem@0 365 adda 16 . d 1101...011000... .......... U U U 8 8 2
philpem@0 366 adda 16 . a 1101...011001... .......... U U U 8 8 2
philpem@0 367 adda 16 . . 1101...011...... A+-DXWLdxI U U U 8 8 2
philpem@0 368 adda 32 . d 1101...111000... .......... U U U 6 6 2
philpem@0 369 adda 32 . a 1101...111001... .......... U U U 6 6 2
philpem@0 370 adda 32 . . 1101...111...... A+-DXWLdxI U U U 6 6 2
philpem@0 371 addi 8 . d 0000011000000... .......... U U U 8 8 2
philpem@0 372 addi 8 . . 0000011000...... A+-DXWL... U U U 12 12 4
philpem@0 373 addi 16 . d 0000011001000... .......... U U U 8 8 2
philpem@0 374 addi 16 . . 0000011001...... A+-DXWL... U U U 12 12 4
philpem@0 375 addi 32 . d 0000011010000... .......... U U U 16 14 2
philpem@0 376 addi 32 . . 0000011010...... A+-DXWL... U U U 20 20 4
philpem@0 377 addq 8 . d 0101...000000... .......... U U U 4 4 2
philpem@0 378 addq 8 . . 0101...000...... A+-DXWL... U U U 8 8 4
philpem@0 379 addq 16 . d 0101...001000... .......... U U U 4 4 2
philpem@0 380 addq 16 . a 0101...001001... .......... U U U 4 4 2
philpem@0 381 addq 16 . . 0101...001...... A+-DXWL... U U U 8 8 4
philpem@0 382 addq 32 . d 0101...010000... .......... U U U 8 8 2
philpem@0 383 addq 32 . a 0101...010001... .......... U U U 8 8 2
philpem@0 384 addq 32 . . 0101...010...... A+-DXWL... U U U 12 12 4
philpem@0 385 addx 8 rr . 1101...100000... .......... U U U 4 4 2
philpem@0 386 addx 16 rr . 1101...101000... .......... U U U 4 4 2
philpem@0 387 addx 32 rr . 1101...110000... .......... U U U 8 6 2
philpem@0 388 addx 8 mm ax7 1101111100001... .......... U U U 18 18 12
philpem@0 389 addx 8 mm ay7 1101...100001111 .......... U U U 18 18 12
philpem@0 390 addx 8 mm axy7 1101111100001111 .......... U U U 18 18 12
philpem@0 391 addx 8 mm . 1101...100001... .......... U U U 18 18 12
philpem@0 392 addx 16 mm . 1101...101001... .......... U U U 18 18 12
philpem@0 393 addx 32 mm . 1101...110001... .......... U U U 30 30 12
philpem@0 394 and 8 er d 1100...000000... .......... U U U 4 4 2
philpem@0 395 and 8 er . 1100...000...... A+-DXWLdxI U U U 4 4 2
philpem@0 396 and 16 er d 1100...001000... .......... U U U 4 4 2
philpem@0 397 and 16 er . 1100...001...... A+-DXWLdxI U U U 4 4 2
philpem@0 398 and 32 er d 1100...010000... .......... U U U 6 6 2
philpem@0 399 and 32 er . 1100...010...... A+-DXWLdxI U U U 6 6 2
philpem@0 400 and 8 re . 1100...100...... A+-DXWL... U U U 8 8 4
philpem@0 401 and 16 re . 1100...101...... A+-DXWL... U U U 8 8 4
philpem@0 402 and 32 re . 1100...110...... A+-DXWL... U U U 12 12 4
philpem@0 403 andi 16 toc . 0000001000111100 .......... U U U 20 16 12
philpem@0 404 andi 16 tos . 0000001001111100 .......... S S S 20 16 12
philpem@0 405 andi 8 . d 0000001000000... .......... U U U 8 8 2
philpem@0 406 andi 8 . . 0000001000...... A+-DXWL... U U U 12 12 4
philpem@0 407 andi 16 . d 0000001001000... .......... U U U 8 8 2
philpem@0 408 andi 16 . . 0000001001...... A+-DXWL... U U U 12 12 4
philpem@0 409 andi 32 . d 0000001010000... .......... U U U 14 14 2
philpem@0 410 andi 32 . . 0000001010...... A+-DXWL... U U U 20 20 4
philpem@0 411 asr 8 s . 1110...000000... .......... U U U 6 6 6
philpem@0 412 asr 16 s . 1110...001000... .......... U U U 6 6 6
philpem@0 413 asr 32 s . 1110...010000... .......... U U U 8 8 6
philpem@0 414 asr 8 r . 1110...000100... .......... U U U 6 6 6
philpem@0 415 asr 16 r . 1110...001100... .......... U U U 6 6 6
philpem@0 416 asr 32 r . 1110...010100... .......... U U U 8 8 6
philpem@0 417 asr 16 . . 1110000011...... A+-DXWL... U U U 8 8 5
philpem@0 418 asl 8 s . 1110...100000... .......... U U U 6 6 8
philpem@0 419 asl 16 s . 1110...101000... .......... U U U 6 6 8
philpem@0 420 asl 32 s . 1110...110000... .......... U U U 8 8 8
philpem@0 421 asl 8 r . 1110...100100... .......... U U U 6 6 8
philpem@0 422 asl 16 r . 1110...101100... .......... U U U 6 6 8
philpem@0 423 asl 32 r . 1110...110100... .......... U U U 8 8 8
philpem@0 424 asl 16 . . 1110000111...... A+-DXWL... U U U 8 8 6
philpem@0 425 bcc 8 . . 0110............ .......... U U U 8 8 6
philpem@0 426 bcc 16 . . 0110....00000000 .......... U U U 10 10 6
philpem@0 427 bcc 32 . . 0110....11111111 .......... . . U . . 6
philpem@0 428 bchg 8 r . 0000...101...... A+-DXWL... U U U 8 8 4
philpem@0 429 bchg 32 r d 0000...101000... .......... U U U 8 8 4
philpem@0 430 bchg 8 s . 0000100001...... A+-DXWL... U U U 12 12 4
philpem@0 431 bchg 32 s d 0000100001000... .......... U U U 12 12 4
philpem@0 432 bclr 8 r . 0000...110...... A+-DXWL... U U U 8 10 4
philpem@0 433 bclr 32 r d 0000...110000... .......... U U U 10 10 4
philpem@0 434 bclr 8 s . 0000100010...... A+-DXWL... U U U 12 12 4
philpem@0 435 bclr 32 s d 0000100010000... .......... U U U 14 14 4
philpem@0 436 bfchg 32 . d 1110101011000... .......... . . U . . 12 timing not quite correct
philpem@0 437 bfchg 32 . . 1110101011...... A..DXWL... . . U . . 20
philpem@0 438 bfclr 32 . d 1110110011000... .......... . . U . . 12
philpem@0 439 bfclr 32 . . 1110110011...... A..DXWL... . . U . . 20
philpem@0 440 bfexts 32 . d 1110101111000... .......... . . U . . 8
philpem@0 441 bfexts 32 . . 1110101111...... A..DXWLdx. . . U . . 15
philpem@0 442 bfextu 32 . d 1110100111000... .......... . . U . . 8
philpem@0 443 bfextu 32 . . 1110100111...... A..DXWLdx. . . U . . 15
philpem@0 444 bfffo 32 . d 1110110111000... .......... . . U . . 18
philpem@0 445 bfffo 32 . . 1110110111...... A..DXWLdx. . . U . . 28
philpem@0 446 bfins 32 . d 1110111111000... .......... . . U . . 10
philpem@0 447 bfins 32 . . 1110111111...... A..DXWL... . . U . . 17
philpem@0 448 bfset 32 . d 1110111011000... .......... . . U . . 12
philpem@0 449 bfset 32 . . 1110111011...... A..DXWL... . . U . . 20
philpem@0 450 bftst 32 . d 1110100011000... .......... . . U . . 6
philpem@0 451 bftst 32 . . 1110100011...... A..DXWLdx. . . U . . 13
philpem@0 452 bkpt 0 . . 0100100001001... .......... . U U . 10 10
philpem@0 453 bra 8 . . 01100000........ .......... U U U 10 10 10
philpem@0 454 bra 16 . . 0110000000000000 .......... U U U 10 10 10
philpem@0 455 bra 32 . . 0110000011111111 .......... U U U . . 10
philpem@0 456 bset 32 r d 0000...111000... .......... U U U 8 8 4
philpem@0 457 bset 8 r . 0000...111...... A+-DXWL... U U U 8 8 4
philpem@0 458 bset 8 s . 0000100011...... A+-DXWL... U U U 12 12 4
philpem@0 459 bset 32 s d 0000100011000... .......... U U U 12 12 4
philpem@0 460 bsr 8 . . 01100001........ .......... U U U 18 18 7
philpem@0 461 bsr 16 . . 0110000100000000 .......... U U U 18 18 7
philpem@0 462 bsr 32 . . 0110000111111111 .......... . . U . . 7
philpem@0 463 btst 8 r . 0000...100...... A+-DXWLdxI U U U 4 4 4
philpem@0 464 btst 32 r d 0000...100000... .......... U U U 6 6 4
philpem@0 465 btst 8 s . 0000100000...... A+-DXWLdx. U U U 8 8 4
philpem@0 466 btst 32 s d 0000100000000... .......... U U U 10 10 4
philpem@0 467 callm 32 . . 0000011011...... A..DXWLdx. . . U . . 60 not properly emulated
philpem@0 468 cas 8 . . 0000101011...... A+-DXWL... . . U . . 12
philpem@0 469 cas 16 . . 0000110011...... A+-DXWL... . . U . . 12
philpem@0 470 cas 32 . . 0000111011...... A+-DXWL... . . U . . 12
philpem@0 471 cas2 16 . . 0000110011111100 .......... . . U . . 12
philpem@0 472 cas2 32 . . 0000111011111100 .......... . . U . . 12
philpem@0 473 chk 16 . d 0100...110000... .......... U U U 10 8 8
philpem@0 474 chk 16 . . 0100...110...... A+-DXWLdxI U U U 10 8 8
philpem@0 475 chk 32 . d 0100...100000... .......... . . U . . 8
philpem@0 476 chk 32 . . 0100...100...... A+-DXWLdxI . . U . . 8
philpem@0 477 chk2cmp2 8 . . 0000000011...... A..DXWLdx. . . U . . 18
philpem@0 478 chk2cmp2 16 . . 0000001011...... A..DXWLdx. . . U . . 18
philpem@0 479 chk2cmp2 32 . . 0000010011...... A..DXWLdx. . . U . . 18
philpem@0 480 clr 8 . d 0100001000000... .......... U U U 4 4 2
philpem@0 481 clr 8 . . 0100001000...... A+-DXWL... U U U 8 4 4
philpem@0 482 clr 16 . d 0100001001000... .......... U U U 4 4 2
philpem@0 483 clr 16 . . 0100001001...... A+-DXWL... U U U 8 4 4
philpem@0 484 clr 32 . d 0100001010000... .......... U U U 6 6 2
philpem@0 485 clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
philpem@0 486 cmp 8 . d 1011...000000... .......... U U U 4 4 2
philpem@0 487 cmp 8 . . 1011...000...... A+-DXWLdxI U U U 4 4 2
philpem@0 488 cmp 16 . d 1011...001000... .......... U U U 4 4 2
philpem@0 489 cmp 16 . a 1011...001001... .......... U U U 4 4 2
philpem@0 490 cmp 16 . . 1011...001...... A+-DXWLdxI U U U 4 4 2
philpem@0 491 cmp 32 . d 1011...010000... .......... U U U 6 6 2
philpem@0 492 cmp 32 . a 1011...010001... .......... U U U 6 6 2
philpem@0 493 cmp 32 . . 1011...010...... A+-DXWLdxI U U U 6 6 2
philpem@0 494 cmpa 16 . d 1011...011000... .......... U U U 6 6 4
philpem@0 495 cmpa 16 . a 1011...011001... .......... U U U 6 6 4
philpem@0 496 cmpa 16 . . 1011...011...... A+-DXWLdxI U U U 6 6 4
philpem@0 497 cmpa 32 . d 1011...111000... .......... U U U 6 6 4
philpem@0 498 cmpa 32 . a 1011...111001... .......... U U U 6 6 4
philpem@0 499 cmpa 32 . . 1011...111...... A+-DXWLdxI U U U 6 6 4
philpem@0 500 cmpi 8 . d 0000110000000... .......... U U U 8 8 2
philpem@0 501 cmpi 8 . . 0000110000...... A+-DXWL... U U U 8 8 2
philpem@0 502 cmpi 8 . pcdi 0000110000111010 .......... . . U . . 7
philpem@0 503 cmpi 8 . pcix 0000110000111011 .......... . . U . . 9
philpem@0 504 cmpi 16 . d 0000110001000... .......... U U U 8 8 2
philpem@0 505 cmpi 16 . . 0000110001...... A+-DXWL... U U U 8 8 2
philpem@0 506 cmpi 16 . pcdi 0000110001111010 .......... . . U . . 7
philpem@0 507 cmpi 16 . pcix 0000110001111011 .......... . . U . . 9
philpem@0 508 cmpi 32 . d 0000110010000... .......... U U U 14 12 2
philpem@0 509 cmpi 32 . . 0000110010...... A+-DXWL... U U U 12 12 2
philpem@0 510 cmpi 32 . pcdi 0000110010111010 .......... . . U . . 7
philpem@0 511 cmpi 32 . pcix 0000110010111011 .......... . . U . . 9
philpem@0 512 cmpm 8 . ax7 1011111100001... .......... U U U 12 12 9
philpem@0 513 cmpm 8 . ay7 1011...100001111 .......... U U U 12 12 9
philpem@0 514 cmpm 8 . axy7 1011111100001111 .......... U U U 12 12 9
philpem@0 515 cmpm 8 . . 1011...100001... .......... U U U 12 12 9
philpem@0 516 cmpm 16 . . 1011...101001... .......... U U U 12 12 9
philpem@0 517 cmpm 32 . . 1011...110001... .......... U U U 20 20 9
philpem@0 518 cpbcc 32 . . 1111...01....... .......... . . U . . 4 unemulated
philpem@0 519 cpdbcc 32 . . 1111...001001... .......... . . U . . 4 unemulated
philpem@0 520 cpgen 32 . . 1111...000...... .......... . . U . . 4 unemulated
philpem@0 521 cpscc 32 . . 1111...001...... .......... . . U . . 4 unemulated
philpem@0 522 cptrapcc 32 . . 1111...001111... .......... . . U . . 4 unemulated
philpem@0 523 dbt 16 . . 0101000011001... .......... U U U 12 12 6
philpem@0 524 dbf 16 . . 0101000111001... .......... U U U 14 14 6
philpem@0 525 dbcc 16 . . 0101....11001... .......... U U U 12 12 6
philpem@0 526 divs 16 . d 1000...111000... .......... U U U 158 122 56
philpem@0 527 divs 16 . . 1000...111...... A+-DXWLdxI U U U 158 122 56
philpem@0 528 divu 16 . d 1000...011000... .......... U U U 140 108 44
philpem@0 529 divu 16 . . 1000...011...... A+-DXWLdxI U U U 140 108 44
philpem@0 530 divl 32 . d 0100110001000... .......... . . U . . 84
philpem@0 531 divl 32 . . 0100110001...... A+-DXWLdxI . . U . . 84
philpem@0 532 eor 8 . d 1011...100000... .......... U U U 4 4 2
philpem@0 533 eor 8 . . 1011...100...... A+-DXWL... U U U 8 8 4
philpem@0 534 eor 16 . d 1011...101000... .......... U U U 4 4 2
philpem@0 535 eor 16 . . 1011...101...... A+-DXWL... U U U 8 8 4
philpem@0 536 eor 32 . d 1011...110000... .......... U U U 8 6 2
philpem@0 537 eor 32 . . 1011...110...... A+-DXWL... U U U 12 12 4
philpem@0 538 eori 16 toc . 0000101000111100 .......... U U U 20 16 12
philpem@0 539 eori 16 tos . 0000101001111100 .......... S S S 20 16 12
philpem@0 540 eori 8 . d 0000101000000... .......... U U U 8 8 2
philpem@0 541 eori 8 . . 0000101000...... A+-DXWL... U U U 12 12 4
philpem@0 542 eori 16 . d 0000101001000... .......... U U U 8 8 2
philpem@0 543 eori 16 . . 0000101001...... A+-DXWL... U U U 12 12 4
philpem@0 544 eori 32 . d 0000101010000... .......... U U U 16 14 2
philpem@0 545 eori 32 . . 0000101010...... A+-DXWL... U U U 20 20 4
philpem@0 546 exg 32 dd . 1100...101000... .......... U U U 6 6 2
philpem@0 547 exg 32 aa . 1100...101001... .......... U U U 6 6 2
philpem@0 548 exg 32 da . 1100...110001... .......... U U U 6 6 2
philpem@0 549 ext 16 . . 0100100010000... .......... U U U 4 4 4
philpem@0 550 ext 32 . . 0100100011000... .......... U U U 4 4 4
philpem@0 551 extb 32 . . 0100100111000... .......... . . U . . 4
philpem@0 552 illegal 0 . . 0100101011111100 .......... U U U 4 4 4
philpem@0 553 jmp 32 . . 0100111011...... A..DXWLdx. U U U 4 4 0
philpem@0 554 jsr 32 . . 0100111010...... A..DXWLdx. U U U 12 12 0
philpem@0 555 lea 32 . . 0100...111...... A..DXWLdx. U U U 0 0 2
philpem@0 556 link 16 . a7 0100111001010111 .......... U U U 16 16 5
philpem@0 557 link 16 . . 0100111001010... .......... U U U 16 16 5
philpem@0 558 link 32 . a7 0100100000001111 .......... . . U . . 6
philpem@0 559 link 32 . . 0100100000001... .......... . . U . . 6
philpem@0 560 lsr 8 s . 1110...000001... .......... U U U 6 6 4
philpem@0 561 lsr 16 s . 1110...001001... .......... U U U 6 6 4
philpem@0 562 lsr 32 s . 1110...010001... .......... U U U 8 8 4
philpem@0 563 lsr 8 r . 1110...000101... .......... U U U 6 6 6
philpem@0 564 lsr 16 r . 1110...001101... .......... U U U 6 6 6
philpem@0 565 lsr 32 r . 1110...010101... .......... U U U 8 8 6
philpem@0 566 lsr 16 . . 1110001011...... A+-DXWL... U U U 8 8 5
philpem@0 567 lsl 8 s . 1110...100001... .......... U U U 6 6 4
philpem@0 568 lsl 16 s . 1110...101001... .......... U U U 6 6 4
philpem@0 569 lsl 32 s . 1110...110001... .......... U U U 8 8 4
philpem@0 570 lsl 8 r . 1110...100101... .......... U U U 6 6 6
philpem@0 571 lsl 16 r . 1110...101101... .......... U U U 6 6 6
philpem@0 572 lsl 32 r . 1110...110101... .......... U U U 8 8 6
philpem@0 573 lsl 16 . . 1110001111...... A+-DXWL... U U U 8 8 5
philpem@0 574 move 8 d d 0001...000000... .......... U U U 4 4 2
philpem@0 575 move 8 d . 0001...000...... A+-DXWLdxI U U U 4 4 2
philpem@0 576 move 8 ai d 0001...010000... .......... U U U 8 8 4
philpem@0 577 move 8 ai . 0001...010...... A+-DXWLdxI U U U 8 8 4
philpem@0 578 move 8 pi d 0001...011000... .......... U U U 8 8 4
philpem@0 579 move 8 pi . 0001...011...... A+-DXWLdxI U U U 8 8 4
philpem@0 580 move 8 pi7 d 0001111011000... .......... U U U 8 8 4
philpem@0 581 move 8 pi7 . 0001111011...... A+-DXWLdxI U U U 8 8 4
philpem@0 582 move 8 pd d 0001...100000... .......... U U U 8 8 5
philpem@0 583 move 8 pd . 0001...100...... A+-DXWLdxI U U U 8 8 5
philpem@0 584 move 8 pd7 d 0001111100000... .......... U U U 8 8 5
philpem@0 585 move 8 pd7 . 0001111100...... A+-DXWLdxI U U U 8 8 5
philpem@0 586 move 8 di d 0001...101000... .......... U U U 12 12 5
philpem@0 587 move 8 di . 0001...101...... A+-DXWLdxI U U U 12 12 5
philpem@0 588 move 8 ix d 0001...110000... .......... U U U 14 14 7
philpem@0 589 move 8 ix . 0001...110...... A+-DXWLdxI U U U 14 14 7
philpem@0 590 move 8 aw d 0001000111000... .......... U U U 12 12 4
philpem@0 591 move 8 aw . 0001000111...... A+-DXWLdxI U U U 12 12 4
philpem@0 592 move 8 al d 0001001111000... .......... U U U 16 16 6
philpem@0 593 move 8 al . 0001001111...... A+-DXWLdxI U U U 16 16 6
philpem@0 594 move 16 d d 0011...000000... .......... U U U 4 4 2
philpem@0 595 move 16 d a 0011...000001... .......... U U U 4 4 2
philpem@0 596 move 16 d . 0011...000...... A+-DXWLdxI U U U 4 4 2
philpem@0 597 move 16 ai d 0011...010000... .......... U U U 8 8 4
philpem@0 598 move 16 ai a 0011...010001... .......... U U U 8 8 4
philpem@0 599 move 16 ai . 0011...010...... A+-DXWLdxI U U U 8 8 4
philpem@0 600 move 16 pi d 0011...011000... .......... U U U 8 8 4
philpem@0 601 move 16 pi a 0011...011001... .......... U U U 8 8 4
philpem@0 602 move 16 pi . 0011...011...... A+-DXWLdxI U U U 8 8 4
philpem@0 603 move 16 pd d 0011...100000... .......... U U U 8 8 5
philpem@0 604 move 16 pd a 0011...100001... .......... U U U 8 8 5
philpem@0 605 move 16 pd . 0011...100...... A+-DXWLdxI U U U 8 8 5
philpem@0 606 move 16 di d 0011...101000... .......... U U U 12 12 5
philpem@0 607 move 16 di a 0011...101001... .......... U U U 12 12 5
philpem@0 608 move 16 di . 0011...101...... A+-DXWLdxI U U U 12 12 5
philpem@0 609 move 16 ix d 0011...110000... .......... U U U 14 14 7
philpem@0 610 move 16 ix a 0011...110001... .......... U U U 14 14 7
philpem@0 611 move 16 ix . 0011...110...... A+-DXWLdxI U U U 14 14 7
philpem@0 612 move 16 aw d 0011000111000... .......... U U U 12 12 4
philpem@0 613 move 16 aw a 0011000111001... .......... U U U 12 12 4
philpem@0 614 move 16 aw . 0011000111...... A+-DXWLdxI U U U 12 12 4
philpem@0 615 move 16 al d 0011001111000... .......... U U U 16 16 6
philpem@0 616 move 16 al a 0011001111001... .......... U U U 16 16 6
philpem@0 617 move 16 al . 0011001111...... A+-DXWLdxI U U U 16 16 6
philpem@0 618 move 32 d d 0010...000000... .......... U U U 4 4 2
philpem@0 619 move 32 d a 0010...000001... .......... U U U 4 4 2
philpem@0 620 move 32 d . 0010...000...... A+-DXWLdxI U U U 4 4 2
philpem@0 621 move 32 ai d 0010...010000... .......... U U U 12 12 4
philpem@0 622 move 32 ai a 0010...010001... .......... U U U 12 12 4
philpem@0 623 move 32 ai . 0010...010...... A+-DXWLdxI U U U 12 12 4
philpem@0 624 move 32 pi d 0010...011000... .......... U U U 12 12 4
philpem@0 625 move 32 pi a 0010...011001... .......... U U U 12 12 4
philpem@0 626 move 32 pi . 0010...011...... A+-DXWLdxI U U U 12 12 4
philpem@0 627 move 32 pd d 0010...100000... .......... U U U 12 14 5
philpem@0 628 move 32 pd a 0010...100001... .......... U U U 12 14 5
philpem@0 629 move 32 pd . 0010...100...... A+-DXWLdxI U U U 12 14 5
philpem@0 630 move 32 di d 0010...101000... .......... U U U 16 16 5
philpem@0 631 move 32 di a 0010...101001... .......... U U U 16 16 5
philpem@0 632 move 32 di . 0010...101...... A+-DXWLdxI U U U 16 16 5
philpem@0 633 move 32 ix d 0010...110000... .......... U U U 18 18 7
philpem@0 634 move 32 ix a 0010...110001... .......... U U U 18 18 7
philpem@0 635 move 32 ix . 0010...110...... A+-DXWLdxI U U U 18 18 7
philpem@0 636 move 32 aw d 0010000111000... .......... U U U 16 16 4
philpem@0 637 move 32 aw a 0010000111001... .......... U U U 16 16 4
philpem@0 638 move 32 aw . 0010000111...... A+-DXWLdxI U U U 16 16 4
philpem@0 639 move 32 al d 0010001111000... .......... U U U 20 20 6
philpem@0 640 move 32 al a 0010001111001... .......... U U U 20 20 6
philpem@0 641 move 32 al . 0010001111...... A+-DXWLdxI U U U 20 20 6
philpem@0 642 movea 16 . d 0011...001000... .......... U U U 4 4 2
philpem@0 643 movea 16 . a 0011...001001... .......... U U U 4 4 2
philpem@0 644 movea 16 . . 0011...001...... A+-DXWLdxI U U U 4 4 2
philpem@0 645 movea 32 . d 0010...001000... .......... U U U 4 4 2
philpem@0 646 movea 32 . a 0010...001001... .......... U U U 4 4 2
philpem@0 647 movea 32 . . 0010...001...... A+-DXWLdxI U U U 4 4 2
philpem@0 648 move 16 frc d 0100001011000... .......... . U U . 4 4
philpem@0 649 move 16 frc . 0100001011...... A+-DXWL... . U U . 8 4
philpem@0 650 move 16 toc d 0100010011000... .......... U U U 12 12 4
philpem@0 651 move 16 toc . 0100010011...... A+-DXWLdxI U U U 12 12 4
philpem@0 652 move 16 frs d 0100000011000... .......... U S S 6 4 8 U only for 000
philpem@0 653 move 16 frs . 0100000011...... A+-DXWL... U S S 8 8 8 U only for 000
philpem@0 654 move 16 tos d 0100011011000... .......... S S S 12 12 8
philpem@0 655 move 16 tos . 0100011011...... A+-DXWLdxI S S S 12 12 8
philpem@0 656 move 32 fru . 0100111001101... .......... S S S 4 6 2
philpem@0 657 move 32 tou . 0100111001100... .......... S S S 4 6 2
philpem@0 658 movec 32 cr . 0100111001111010 .......... . S S . 12 6
philpem@0 659 movec 32 rc . 0100111001111011 .......... . S S . 10 12
philpem@0 660 movem 16 re pd 0100100010100... .......... U U U 8 8 4
philpem@0 661 movem 16 re . 0100100010...... A..DXWL... U U U 8 8 4
philpem@0 662 movem 32 re pd 0100100011100... .......... U U U 8 8 4
philpem@0 663 movem 32 re . 0100100011...... A..DXWL... U U U 8 8 4
philpem@0 664 movem 16 er pi 0100110010011... .......... U U U 12 12 8
philpem@0 665 movem 16 er . 0100110010...... A..DXWLdx. U U U 12 12 8
philpem@0 666 movem 32 er pi 0100110011011... .......... U U U 12 12 8
philpem@0 667 movem 32 er . 0100110011...... A..DXWLdx. U U U 12 12 8
philpem@0 668 movep 16 er . 0000...100001... .......... U U U 16 16 12
philpem@0 669 movep 32 er . 0000...101001... .......... U U U 24 24 18
philpem@0 670 movep 16 re . 0000...110001... .......... U U U 16 16 11
philpem@0 671 movep 32 re . 0000...111001... .......... U U U 24 24 17
philpem@0 672 moveq 32 . . 0111...0........ .......... U U U 4 4 2
philpem@0 673 moves 8 . . 0000111000...... A+-DXWL... . S S . 14 5
philpem@0 674 moves 16 . . 0000111001...... A+-DXWL... . S S . 14 5
philpem@0 675 moves 32 . . 0000111010...... A+-DXWL... . S S . 16 5
philpem@0 676 muls 16 . d 1100...111000... .......... U U U 54 32 27
philpem@0 677 muls 16 . . 1100...111...... A+-DXWLdxI U U U 54 32 27
philpem@0 678 mulu 16 . d 1100...011000... .......... U U U 54 30 27
philpem@0 679 mulu 16 . . 1100...011...... A+-DXWLdxI U U U 54 30 27
philpem@0 680 mull 32 . d 0100110000000... .......... . . U . . 43
philpem@0 681 mull 32 . . 0100110000...... A+-DXWLdxI . . U . . 43
philpem@0 682 nbcd 8 . d 0100100000000... .......... U U U 6 6 6
philpem@0 683 nbcd 8 . . 0100100000...... A+-DXWL... U U U 8 8 6
philpem@0 684 neg 8 . d 0100010000000... .......... U U U 4 4 2
philpem@0 685 neg 8 . . 0100010000...... A+-DXWL... U U U 8 8 4
philpem@0 686 neg 16 . d 0100010001000... .......... U U U 4 4 2
philpem@0 687 neg 16 . . 0100010001...... A+-DXWL... U U U 8 8 4
philpem@0 688 neg 32 . d 0100010010000... .......... U U U 6 6 2
philpem@0 689 neg 32 . . 0100010010...... A+-DXWL... U U U 12 12 4
philpem@0 690 negx 8 . d 0100000000000... .......... U U U 4 4 2
philpem@0 691 negx 8 . . 0100000000...... A+-DXWL... U U U 8 8 4
philpem@0 692 negx 16 . d 0100000001000... .......... U U U 4 4 2
philpem@0 693 negx 16 . . 0100000001...... A+-DXWL... U U U 8 8 4
philpem@0 694 negx 32 . d 0100000010000... .......... U U U 6 6 2
philpem@0 695 negx 32 . . 0100000010...... A+-DXWL... U U U 12 12 4
philpem@0 696 nop 0 . . 0100111001110001 .......... U U U 4 4 2
philpem@0 697 not 8 . d 0100011000000... .......... U U U 4 4 2
philpem@0 698 not 8 . . 0100011000...... A+-DXWL... U U U 8 8 4
philpem@0 699 not 16 . d 0100011001000... .......... U U U 4 4 2
philpem@0 700 not 16 . . 0100011001...... A+-DXWL... U U U 8 8 4
philpem@0 701 not 32 . d 0100011010000... .......... U U U 6 6 2
philpem@0 702 not 32 . . 0100011010...... A+-DXWL... U U U 12 12 4
philpem@0 703 or 8 er d 1000...000000... .......... U U U 4 4 2
philpem@0 704 or 8 er . 1000...000...... A+-DXWLdxI U U U 4 4 2
philpem@0 705 or 16 er d 1000...001000... .......... U U U 4 4 2
philpem@0 706 or 16 er . 1000...001...... A+-DXWLdxI U U U 4 4 2
philpem@0 707 or 32 er d 1000...010000... .......... U U U 6 6 2
philpem@0 708 or 32 er . 1000...010...... A+-DXWLdxI U U U 6 6 2
philpem@0 709 or 8 re . 1000...100...... A+-DXWL... U U U 8 8 4
philpem@0 710 or 16 re . 1000...101...... A+-DXWL... U U U 8 8 4
philpem@0 711 or 32 re . 1000...110...... A+-DXWL... U U U 12 12 4
philpem@0 712 ori 16 toc . 0000000000111100 .......... U U U 20 16 12
philpem@0 713 ori 16 tos . 0000000001111100 .......... S S S 20 16 12
philpem@0 714 ori 8 . d 0000000000000... .......... U U U 8 8 2
philpem@0 715 ori 8 . . 0000000000...... A+-DXWL... U U U 12 12 4
philpem@0 716 ori 16 . d 0000000001000... .......... U U U 8 8 2
philpem@0 717 ori 16 . . 0000000001...... A+-DXWL... U U U 12 12 4
philpem@0 718 ori 32 . d 0000000010000... .......... U U U 16 14 2
philpem@0 719 ori 32 . . 0000000010...... A+-DXWL... U U U 20 20 4
philpem@0 720 pack 16 rr . 1000...101000... .......... . . U . . 6
philpem@0 721 pack 16 mm ax7 1000111101001... .......... . . U . . 13
philpem@0 722 pack 16 mm ay7 1000...101001111 .......... . . U . . 13
philpem@0 723 pack 16 mm axy7 1000111101001111 .......... . . U . . 13
philpem@0 724 pack 16 mm . 1000...101001... .......... . . U . . 13
philpem@0 725 pea 32 . . 0100100001...... A..DXWLdx. U U U 6 6 5
philpem@0 726 reset 0 . . 0100111001110000 .......... S S S 0 0 0
philpem@0 727 ror 8 s . 1110...000011... .......... U U U 6 6 8
philpem@0 728 ror 16 s . 1110...001011... .......... U U U 6 6 8
philpem@0 729 ror 32 s . 1110...010011... .......... U U U 8 8 8
philpem@0 730 ror 8 r . 1110...000111... .......... U U U 6 6 8
philpem@0 731 ror 16 r . 1110...001111... .......... U U U 6 6 8
philpem@0 732 ror 32 r . 1110...010111... .......... U U U 8 8 8
philpem@0 733 ror 16 . . 1110011011...... A+-DXWL... U U U 8 8 7
philpem@0 734 rol 8 s . 1110...100011... .......... U U U 6 6 8
philpem@0 735 rol 16 s . 1110...101011... .......... U U U 6 6 8
philpem@0 736 rol 32 s . 1110...110011... .......... U U U 8 8 8
philpem@0 737 rol 8 r . 1110...100111... .......... U U U 6 6 8
philpem@0 738 rol 16 r . 1110...101111... .......... U U U 6 6 8
philpem@0 739 rol 32 r . 1110...110111... .......... U U U 8 8 8
philpem@0 740 rol 16 . . 1110011111...... A+-DXWL... U U U 8 8 7
philpem@0 741 roxr 8 s . 1110...000010... .......... U U U 6 6 12
philpem@0 742 roxr 16 s . 1110...001010... .......... U U U 6 6 12
philpem@0 743 roxr 32 s . 1110...010010... .......... U U U 8 8 12
philpem@0 744 roxr 8 r . 1110...000110... .......... U U U 6 6 12
philpem@0 745 roxr 16 r . 1110...001110... .......... U U U 6 6 12
philpem@0 746 roxr 32 r . 1110...010110... .......... U U U 8 8 12
philpem@0 747 roxr 16 . . 1110010011...... A+-DXWL... U U U 8 8 5
philpem@0 748 roxl 8 s . 1110...100010... .......... U U U 6 6 12
philpem@0 749 roxl 16 s . 1110...101010... .......... U U U 6 6 12
philpem@0 750 roxl 32 s . 1110...110010... .......... U U U 8 8 12
philpem@0 751 roxl 8 r . 1110...100110... .......... U U U 6 6 12
philpem@0 752 roxl 16 r . 1110...101110... .......... U U U 6 6 12
philpem@0 753 roxl 32 r . 1110...110110... .......... U U U 8 8 12
philpem@0 754 roxl 16 . . 1110010111...... A+-DXWL... U U U 8 8 5
philpem@0 755 rtd 32 . . 0100111001110100 .......... . U U . 16 10
philpem@0 756 rte 32 . . 0100111001110011 .......... S S S 20 24 20 bus fault not emulated
philpem@0 757 rtm 32 . . 000001101100.... .......... . . U . . 19 not properly emulated
philpem@0 758 rtr 32 . . 0100111001110111 .......... U U U 20 20 14
philpem@0 759 rts 32 . . 0100111001110101 .......... U U U 16 16 10
philpem@0 760 sbcd 8 rr . 1000...100000... .......... U U U 6 6 4
philpem@0 761 sbcd 8 mm ax7 1000111100001... .......... U U U 18 18 16
philpem@0 762 sbcd 8 mm ay7 1000...100001111 .......... U U U 18 18 16
philpem@0 763 sbcd 8 mm axy7 1000111100001111 .......... U U U 18 18 16
philpem@0 764 sbcd 8 mm . 1000...100001... .......... U U U 18 18 16
philpem@0 765 st 8 . d 0101000011000... .......... U U U 6 4 4
philpem@0 766 st 8 . . 0101000011...... A+-DXWL... U U U 8 8 6
philpem@0 767 sf 8 . d 0101000111000... .......... U U U 4 4 4
philpem@0 768 sf 8 . . 0101000111...... A+-DXWL... U U U 8 8 6
philpem@0 769 scc 8 . d 0101....11000... .......... U U U 4 4 4
philpem@0 770 scc 8 . . 0101....11...... A+-DXWL... U U U 8 8 6
philpem@0 771 stop 0 . . 0100111001110010 .......... S S S 4 4 8
philpem@0 772 sub 8 er d 1001...000000... .......... U U U 4 4 2
philpem@0 773 sub 8 er . 1001...000...... A+-DXWLdxI U U U 4 4 2
philpem@0 774 sub 16 er d 1001...001000... .......... U U U 4 4 2
philpem@0 775 sub 16 er a 1001...001001... .......... U U U 4 4 2
philpem@0 776 sub 16 er . 1001...001...... A+-DXWLdxI U U U 4 4 2
philpem@0 777 sub 32 er d 1001...010000... .......... U U U 6 6 2
philpem@0 778 sub 32 er a 1001...010001... .......... U U U 6 6 2
philpem@0 779 sub 32 er . 1001...010...... A+-DXWLdxI U U U 6 6 2
philpem@0 780 sub 8 re . 1001...100...... A+-DXWL... U U U 8 8 4
philpem@0 781 sub 16 re . 1001...101...... A+-DXWL... U U U 8 8 4
philpem@0 782 sub 32 re . 1001...110...... A+-DXWL... U U U 12 12 4
philpem@0 783 suba 16 . d 1001...011000... .......... U U U 8 8 2
philpem@0 784 suba 16 . a 1001...011001... .......... U U U 8 8 2
philpem@0 785 suba 16 . . 1001...011...... A+-DXWLdxI U U U 8 8 2
philpem@0 786 suba 32 . d 1001...111000... .......... U U U 6 6 2
philpem@0 787 suba 32 . a 1001...111001... .......... U U U 6 6 2
philpem@0 788 suba 32 . . 1001...111...... A+-DXWLdxI U U U 6 6 2
philpem@0 789 subi 8 . d 0000010000000... .......... U U U 8 8 2
philpem@0 790 subi 8 . . 0000010000...... A+-DXWL... U U U 12 12 4
philpem@0 791 subi 16 . d 0000010001000... .......... U U U 8 8 2
philpem@0 792 subi 16 . . 0000010001...... A+-DXWL... U U U 12 12 4
philpem@0 793 subi 32 . d 0000010010000... .......... U U U 16 14 2
philpem@0 794 subi 32 . . 0000010010...... A+-DXWL... U U U 20 20 4
philpem@0 795 subq 8 . d 0101...100000... .......... U U U 4 4 2
philpem@0 796 subq 8 . . 0101...100...... A+-DXWL... U U U 8 8 4
philpem@0 797 subq 16 . d 0101...101000... .......... U U U 4 4 2
philpem@0 798 subq 16 . a 0101...101001... .......... U U U 8 4 2
philpem@0 799 subq 16 . . 0101...101...... A+-DXWL... U U U 8 8 4
philpem@0 800 subq 32 . d 0101...110000... .......... U U U 8 8 2
philpem@0 801 subq 32 . a 0101...110001... .......... U U U 8 8 2
philpem@0 802 subq 32 . . 0101...110...... A+-DXWL... U U U 12 12 4
philpem@0 803 subx 8 rr . 1001...100000... .......... U U U 4 4 2
philpem@0 804 subx 16 rr . 1001...101000... .......... U U U 4 4 2
philpem@0 805 subx 32 rr . 1001...110000... .......... U U U 8 6 2
philpem@0 806 subx 8 mm ax7 1001111100001... .......... U U U 18 18 12
philpem@0 807 subx 8 mm ay7 1001...100001111 .......... U U U 18 18 12
philpem@0 808 subx 8 mm axy7 1001111100001111 .......... U U U 18 18 12
philpem@0 809 subx 8 mm . 1001...100001... .......... U U U 18 18 12
philpem@0 810 subx 16 mm . 1001...101001... .......... U U U 18 18 12
philpem@0 811 subx 32 mm . 1001...110001... .......... U U U 30 30 12
philpem@0 812 swap 32 . . 0100100001000... .......... U U U 4 4 4
philpem@0 813 tas 8 . d 0100101011000... .......... U U U 4 4 4
philpem@0 814 tas 8 . . 0100101011...... A+-DXWL... U U U 14 14 12
philpem@0 815 trap 0 . . 010011100100.... .......... U U U 4 4 4
philpem@0 816 trapt 0 . . 0101000011111100 .......... . . U . . 4
philpem@0 817 trapt 16 . . 0101000011111010 .......... . . U . . 6
philpem@0 818 trapt 32 . . 0101000011111011 .......... . . U . . 8
philpem@0 819 trapf 0 . . 0101000111111100 .......... . . U . . 4
philpem@0 820 trapf 16 . . 0101000111111010 .......... . . U . . 6
philpem@0 821 trapf 32 . . 0101000111111011 .......... . . U . . 8
philpem@0 822 trapcc 0 . . 0101....11111100 .......... . . U . . 4
philpem@0 823 trapcc 16 . . 0101....11111010 .......... . . U . . 6
philpem@0 824 trapcc 32 . . 0101....11111011 .......... . . U . . 8
philpem@0 825 trapv 0 . . 0100111001110110 .......... U U U 4 4 4
philpem@0 826 tst 8 . d 0100101000000... .......... U U U 4 4 2
philpem@0 827 tst 8 . . 0100101000...... A+-DXWL... U U U 4 4 2
philpem@0 828 tst 8 . pcdi 0100101000111010 .......... . . U . . 7
philpem@0 829 tst 8 . pcix 0100101000111011 .......... . . U . . 9
philpem@0 830 tst 8 . i 0100101000111100 .......... . . U . . 6
philpem@0 831 tst 16 . d 0100101001000... .......... U U U 4 4 2
philpem@0 832 tst 16 . a 0100101001001... .......... . . U . . 2
philpem@0 833 tst 16 . . 0100101001...... A+-DXWL... U U U 4 4 2
philpem@0 834 tst 16 . pcdi 0100101001111010 .......... . . U . . 7
philpem@0 835 tst 16 . pcix 0100101001111011 .......... . . U . . 9
philpem@0 836 tst 16 . i 0100101001111100 .......... . . U . . 6
philpem@0 837 tst 32 . d 0100101010000... .......... U U U 4 4 2
philpem@0 838 tst 32 . a 0100101010001... .......... . . U . . 2
philpem@0 839 tst 32 . . 0100101010...... A+-DXWL... U U U 4 4 2
philpem@0 840 tst 32 . pcdi 0100101010111010 .......... . . U . . 7
philpem@0 841 tst 32 . pcix 0100101010111011 .......... . . U . . 9
philpem@0 842 tst 32 . i 0100101010111100 .......... . . U . . 6
philpem@0 843 unlk 32 . a7 0100111001011111 .......... U U U 12 12 6
philpem@0 844 unlk 32 . . 0100111001011... .......... U U U 12 12 6
philpem@0 845 unpk 16 rr . 1000...110000... .......... . . U . . 8
philpem@0 846 unpk 16 mm ax7 1000111110001... .......... . . U . . 13
philpem@0 847 unpk 16 mm ay7 1000...110001111 .......... . . U . . 13
philpem@0 848 unpk 16 mm axy7 1000111110001111 .......... . . U . . 13
philpem@0 849 unpk 16 mm . 1000...110001... .......... . . U . . 13
philpem@0 850
philpem@0 851
philpem@0 852
philpem@0 853 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
philpem@0 854 M68KMAKE_OPCODE_HANDLER_BODY
philpem@0 855
philpem@0 856 M68KMAKE_OP(1010, 0, ., .)
philpem@0 857 {
philpem@0 858 m68ki_exception_1010();
philpem@0 859 }
philpem@0 860
philpem@0 861
philpem@0 862 M68KMAKE_OP(1111, 0, ., .)
philpem@0 863 {
philpem@0 864 m68ki_exception_1111();
philpem@0 865 }
philpem@0 866
philpem@0 867
philpem@0 868 M68KMAKE_OP(abcd, 8, rr, .)
philpem@0 869 {
philpem@0 870 uint* r_dst = &DX;
philpem@0 871 uint src = DY;
philpem@0 872 uint dst = *r_dst;
philpem@0 873 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
philpem@0 874
philpem@0 875 if(res > 9)
philpem@0 876 res += 6;
philpem@0 877 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
philpem@0 878 FLAG_X = FLAG_C = (res > 0x99) << 8;
philpem@0 879 if(FLAG_C)
philpem@0 880 res -= 0xa0;
philpem@0 881
philpem@0 882 FLAG_N = NFLAG_8(res); /* officially undefined */
philpem@0 883
philpem@0 884 res = MASK_OUT_ABOVE_8(res);
philpem@0 885 FLAG_Z |= res;
philpem@0 886
philpem@0 887 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
philpem@0 888 }
philpem@0 889
philpem@0 890
philpem@0 891 M68KMAKE_OP(abcd, 8, mm, ax7)
philpem@0 892 {
philpem@0 893 uint src = OPER_AY_PD_8();
philpem@0 894 uint ea = EA_A7_PD_8();
philpem@0 895 uint dst = m68ki_read_8(ea);
philpem@0 896 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
philpem@0 897
philpem@0 898 if(res > 9)
philpem@0 899 res += 6;
philpem@0 900 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
philpem@0 901 FLAG_X = FLAG_C = (res > 0x99) << 8;
philpem@0 902 if(FLAG_C)
philpem@0 903 res -= 0xa0;
philpem@0 904
philpem@0 905 FLAG_N = NFLAG_8(res); /* officially undefined */
philpem@0 906
philpem@0 907 res = MASK_OUT_ABOVE_8(res);
philpem@0 908 FLAG_Z |= res;
philpem@0 909
philpem@0 910 m68ki_write_8(ea, res);
philpem@0 911 }
philpem@0 912
philpem@0 913
philpem@0 914 M68KMAKE_OP(abcd, 8, mm, ay7)
philpem@0 915 {
philpem@0 916 uint src = OPER_A7_PD_8();
philpem@0 917 uint ea = EA_AX_PD_8();
philpem@0 918 uint dst = m68ki_read_8(ea);
philpem@0 919 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
philpem@0 920
philpem@0 921 if(res > 9)
philpem@0 922 res += 6;
philpem@0 923 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
philpem@0 924 FLAG_X = FLAG_C = (res > 0x99) << 8;
philpem@0 925 if(FLAG_C)
philpem@0 926 res -= 0xa0;
philpem@0 927
philpem@0 928 FLAG_N = NFLAG_8(res); /* officially undefined */
philpem@0 929
philpem@0 930 res = MASK_OUT_ABOVE_8(res);
philpem@0 931 FLAG_Z |= res;
philpem@0 932
philpem@0 933 m68ki_write_8(ea, res);
philpem@0 934 }
philpem@0 935
philpem@0 936
philpem@0 937 M68KMAKE_OP(abcd, 8, mm, axy7)
philpem@0 938 {
philpem@0 939 uint src = OPER_A7_PD_8();
philpem@0 940 uint ea = EA_A7_PD_8();
philpem@0 941 uint dst = m68ki_read_8(ea);
philpem@0 942 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
philpem@0 943
philpem@0 944 if(res > 9)
philpem@0 945 res += 6;
philpem@0 946 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
philpem@0 947 FLAG_X = FLAG_C = (res > 0x99) << 8;
philpem@0 948 if(FLAG_C)
philpem@0 949 res -= 0xa0;
philpem@0 950
philpem@0 951 FLAG_N = NFLAG_8(res); /* officially undefined */
philpem@0 952
philpem@0 953 res = MASK_OUT_ABOVE_8(res);
philpem@0 954 FLAG_Z |= res;
philpem@0 955
philpem@0 956 m68ki_write_8(ea, res);
philpem@0 957 }
philpem@0 958
philpem@0 959
philpem@0 960 M68KMAKE_OP(abcd, 8, mm, .)
philpem@0 961 {
philpem@0 962 uint src = OPER_AY_PD_8();
philpem@0 963 uint ea = EA_AX_PD_8();
philpem@0 964 uint dst = m68ki_read_8(ea);
philpem@0 965 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
philpem@0 966
philpem@0 967 if(res > 9)
philpem@0 968 res += 6;
philpem@0 969 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
philpem@0 970 FLAG_X = FLAG_C = (res > 0x99) << 8;
philpem@0 971 if(FLAG_C)
philpem@0 972 res -= 0xa0;
philpem@0 973
philpem@0 974 FLAG_N = NFLAG_8(res); /* officially undefined */
philpem@0 975
philpem@0 976 res = MASK_OUT_ABOVE_8(res);
philpem@0 977 FLAG_Z |= res;
philpem@0 978
philpem@0 979 m68ki_write_8(ea, res);
philpem@0 980 }
philpem@0 981
philpem@0 982
philpem@0 983 M68KMAKE_OP(add, 8, er, d)
philpem@0 984 {
philpem@0 985 uint* r_dst = &DX;
philpem@0 986 uint src = MASK_OUT_ABOVE_8(DY);
philpem@0 987 uint dst = MASK_OUT_ABOVE_8(*r_dst);
philpem@0 988 uint res = src + dst;
philpem@0 989
philpem@0 990 FLAG_N = NFLAG_8(res);
philpem@0 991 FLAG_V = VFLAG_ADD_8(src, dst, res);
philpem@0 992 FLAG_X = FLAG_C = CFLAG_8(res);
philpem@0 993 FLAG_Z = MASK_OUT_ABOVE_8(res);
philpem@0 994
philpem@0 995 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
philpem@0 996 }
philpem@0 997
philpem@0 998
philpem@0 999 M68KMAKE_OP(add, 8, er, .)
philpem@0 1000 {
philpem@0 1001 uint* r_dst = &DX;
philpem@0 1002 uint src = M68KMAKE_GET_OPER_AY_8;
philpem@0 1003 uint dst = MASK_OUT_ABOVE_8(*r_dst);
philpem@0 1004 uint res = src + dst;
philpem@0 1005
philpem@0 1006 FLAG_N = NFLAG_8(res);
philpem@0 1007 FLAG_V = VFLAG_ADD_8(src, dst, res);
philpem@0 1008 FLAG_X = FLAG_C = CFLAG_8(res);
philpem@0 1009 FLAG_Z = MASK_OUT_ABOVE_8(res);
philpem@0 1010
philpem@0 1011 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
philpem@0 1012 }
philpem@0 1013
philpem@0 1014
philpem@0 1015 M68KMAKE_OP(add, 16, er, d)
philpem@0 1016 {
philpem@0 1017 uint* r_dst = &DX;
philpem@0 1018 uint src = MASK_OUT_ABOVE_16(DY);
philpem@0 1019 uint dst = MASK_OUT_ABOVE_16(*r_dst);
philpem@0 1020 uint res = src + dst;
philpem@0 1021
philpem@0 1022 FLAG_N = NFLAG_16(res);
philpem@0 1023 FLAG_V = VFLAG_ADD_16(src, dst, res);
philpem@0 1024 FLAG_X = FLAG_C = CFLAG_16(res);
philpem@0 1025 FLAG_Z = MASK_OUT_ABOVE_16(res);
philpem@0 1026
philpem@0 1027 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
philpem@0 1028 }
philpem@0 1029
philpem@0 1030
philpem@0 1031 M68KMAKE_OP(add, 16, er, a)
philpem@0 1032 {
philpem@0 1033 uint* r_dst = &DX;
philpem@0 1034 uint src = MASK_OUT_ABOVE_16(AY);
philpem@0 1035 uint dst = MASK_OUT_ABOVE_16(*r_dst);
philpem@0 1036 uint res = src + dst;
philpem@0 1037
philpem@0 1038 FLAG_N = NFLAG_16(res);
philpem@0 1039 FLAG_V = VFLAG_ADD_16(src, dst, res);
philpem@0 1040 FLAG_X = FLAG_C = CFLAG_16(res);
philpem@0 1041 FLAG_Z = MASK_OUT_ABOVE_16(res);
philpem@0 1042
philpem@0 1043 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
philpem@0 1044 }
philpem@0 1045
philpem@0 1046
philpem@0 1047 M68KMAKE_OP(add, 16, er, .)
philpem@0 1048 {
philpem@0 1049 uint* r_dst = &DX;
philpem@0 1050 uint src = M68KMAKE_GET_OPER_AY_16;
philpem@0 1051 uint dst = MASK_OUT_ABOVE_16(*r_dst);
philpem@0 1052 uint res = src + dst;
philpem@0 1053
philpem@0 1054 FLAG_N = NFLAG_16(res);
philpem@0 1055 FLAG_V = VFLAG_ADD_16(src, dst, res);
philpem@0 1056 FLAG_X = FLAG_C = CFLAG_16(res);
philpem@0 1057 FLAG_Z = MASK_OUT_ABOVE_16(res);
philpem@0 1058
philpem@0 1059 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
philpem@0 1060 }
philpem@0 1061
philpem@0 1062
philpem@0 1063 M68KMAKE_OP(add, 32, er, d)
philpem@0 1064 {
philpem@0 1065 uint* r_dst = &DX;
philpem@0 1066 uint src = DY;
philpem@0 1067 uint dst = *r_dst;
philpem@0 1068 uint res = src + dst;
philpem@0 1069
philpem@0 1070 FLAG_N = NFLAG_32(res);
philpem@0 1071 FLAG_V = VFLAG_ADD_32(src, dst, res);
philpem@0 1072 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
philpem@0 1073 FLAG_Z = MASK_OUT_ABOVE_32(res);
philpem@0 1074
philpem@0 1075 *r_dst = FLAG_Z;
philpem@0 1076 }
philpem@0 1077
philpem@0 1078
philpem@0 1079 M68KMAKE_OP(add, 32, er, a)
philpem@0 1080 {
philpem@0 1081 uint* r_dst = &DX;
philpem@0 1082 uint src = AY;
philpem@0 1083 uint dst = *r_dst;
philpem@0 1084 uint res = src + dst;
philpem@0 1085
philpem@0 1086 FLAG_N = NFLAG_32(res);
philpem@0 1087 FLAG_V = VFLAG_ADD_32(src, dst, res);
philpem@0 1088 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
philpem@0 1089 FLAG_Z = MASK_OUT_ABOVE_32(res);
philpem@0 1090
philpem@0 1091 *r_dst = FLAG_Z;
philpem@0 1092 }
philpem@0 1093
philpem@0 1094
philpem@0 1095 M68KMAKE_OP(add, 32, er, .)
philpem@0 1096 {
philpem@0 1097 uint* r_dst = &DX;
philpem@0 1098 uint src = M68KMAKE_GET_OPER_AY_32;
philpem@0 1099 uint dst = *r_dst;
philpem@0 1100 uint res = src + dst;
philpem@0 1101
philpem@0 1102 FLAG_N = NFLAG_32(res);
philpem@0 1103 FLAG_V = VFLAG_ADD_32(src, dst, res);
philpem@0 1104 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
philpem@0 1105 FLAG_Z = MASK_OUT_ABOVE_32(res);
philpem@0 1106
philpem@0 1107 *r_dst = FLAG_Z;
philpem@0 1108 }
philpem@0 1109
philpem@0 1110
philpem@0 1111 M68KMAKE_OP(add, 8, re, .)
philpem@0 1112 {
philpem@0 1113 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 1114 uint src = MASK_OUT_ABOVE_8(DX);
philpem@0 1115 uint dst = m68ki_read_8(ea);
philpem@0 1116 uint res = src + dst;
philpem@0 1117
philpem@0 1118 FLAG_N = NFLAG_8(res);
philpem@0 1119 FLAG_V = VFLAG_ADD_8(src, dst, res);
philpem@0 1120 FLAG_X = FLAG_C = CFLAG_8(res);
philpem@0 1121 FLAG_Z = MASK_OUT_ABOVE_8(res);
philpem@0 1122
philpem@0 1123 m68ki_write_8(ea, FLAG_Z);
philpem@0 1124 }
philpem@0 1125
philpem@0 1126
philpem@0 1127 M68KMAKE_OP(add, 16, re, .)
philpem@0 1128 {
philpem@0 1129 uint ea = M68KMAKE_GET_EA_AY_16;
philpem@0 1130 uint src = MASK_OUT_ABOVE_16(DX);
philpem@0 1131 uint dst = m68ki_read_16(ea);
philpem@0 1132 uint res = src + dst;
philpem@0 1133
philpem@0 1134 FLAG_N = NFLAG_16(res);
philpem@0 1135 FLAG_V = VFLAG_ADD_16(src, dst, res);
philpem@0 1136 FLAG_X = FLAG_C = CFLAG_16(res);
philpem@0 1137 FLAG_Z = MASK_OUT_ABOVE_16(res);
philpem@0 1138
philpem@0 1139 m68ki_write_16(ea, FLAG_Z);
philpem@0 1140 }
philpem@0 1141
philpem@0 1142
philpem@0 1143 M68KMAKE_OP(add, 32, re, .)
philpem@0 1144 {
philpem@0 1145 uint ea = M68KMAKE_GET_EA_AY_32;
philpem@0 1146 uint src = DX;
philpem@0 1147 uint dst = m68ki_read_32(ea);
philpem@0 1148 uint res = src + dst;
philpem@0 1149
philpem@0 1150 FLAG_N = NFLAG_32(res);
philpem@0 1151 FLAG_V = VFLAG_ADD_32(src, dst, res);
philpem@0 1152 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
philpem@0 1153 FLAG_Z = MASK_OUT_ABOVE_32(res);
philpem@0 1154
philpem@0 1155 m68ki_write_32(ea, FLAG_Z);
philpem@0 1156 }
philpem@0 1157
philpem@0 1158
philpem@0 1159 M68KMAKE_OP(adda, 16, ., d)
philpem@0 1160 {
philpem@0 1161 uint* r_dst = &AX;
philpem@0 1162
philpem@0 1163 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));
philpem@0 1164 }
philpem@0 1165
philpem@0 1166
philpem@0 1167 M68KMAKE_OP(adda, 16, ., a)
philpem@0 1168 {
philpem@0 1169 uint* r_dst = &AX;
philpem@0 1170
philpem@0 1171 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));
philpem@0 1172 }
philpem@0 1173
philpem@0 1174
philpem@0 1175 M68KMAKE_OP(adda, 16, ., .)
philpem@0 1176 {
philpem@0 1177 uint* r_dst = &AX;
philpem@0 1178
philpem@0 1179 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(M68KMAKE_GET_OPER_AY_16));
philpem@0 1180 }
philpem@0 1181
philpem@0 1182
philpem@0 1183 M68KMAKE_OP(adda, 32, ., d)
philpem@0 1184 {
philpem@0 1185 uint* r_dst = &AX;
philpem@0 1186
philpem@0 1187 *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);
philpem@0 1188 }
philpem@0 1189
philpem@0 1190
philpem@0 1191 M68KMAKE_OP(adda, 32, ., a)
philpem@0 1192 {
philpem@0 1193 uint* r_dst = &AX;
philpem@0 1194
philpem@0 1195 *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);
philpem@0 1196 }
philpem@0 1197
philpem@0 1198
philpem@0 1199 M68KMAKE_OP(adda, 32, ., .)
philpem@0 1200 {
philpem@0 1201 uint* r_dst = &AX;
philpem@0 1202
philpem@0 1203 *r_dst = MASK_OUT_ABOVE_32(*r_dst + M68KMAKE_GET_OPER_AY_32);
philpem@0 1204 }
philpem@0 1205
philpem@0 1206
philpem@0 1207 M68KMAKE_OP(addi, 8, ., d)
philpem@0 1208 {
philpem@0 1209 uint* r_dst = &DY;
philpem@0 1210 uint src = OPER_I_8();
philpem@0 1211 uint dst = MASK_OUT_ABOVE_8(*r_dst);
philpem@0 1212 uint res = src + dst;
philpem@0 1213
philpem@0 1214 FLAG_N = NFLAG_8(res);
philpem@0 1215 FLAG_V = VFLAG_ADD_8(src, dst, res);
philpem@0 1216 FLAG_X = FLAG_C = CFLAG_8(res);
philpem@0 1217 FLAG_Z = MASK_OUT_ABOVE_8(res);
philpem@0 1218
philpem@0 1219 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
philpem@0 1220 }
philpem@0 1221
philpem@0 1222
philpem@0 1223 M68KMAKE_OP(addi, 8, ., .)
philpem@0 1224 {
philpem@0 1225 uint src = OPER_I_8();
philpem@0 1226 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 1227 uint dst = m68ki_read_8(ea);
philpem@0 1228 uint res = src + dst;
philpem@0 1229
philpem@0 1230 FLAG_N = NFLAG_8(res);
philpem@0 1231 FLAG_V = VFLAG_ADD_8(src, dst, res);
philpem@0 1232 FLAG_X = FLAG_C = CFLAG_8(res);
philpem@0 1233 FLAG_Z = MASK_OUT_ABOVE_8(res);
philpem@0 1234
philpem@0 1235 m68ki_write_8(ea, FLAG_Z);
philpem@0 1236 }
philpem@0 1237
philpem@0 1238
philpem@0 1239 M68KMAKE_OP(addi, 16, ., d)
philpem@0 1240 {
philpem@0 1241 uint* r_dst = &DY;
philpem@0 1242 uint src = OPER_I_16();
philpem@0 1243 uint dst = MASK_OUT_ABOVE_16(*r_dst);
philpem@0 1244 uint res = src + dst;
philpem@0 1245
philpem@0 1246 FLAG_N = NFLAG_16(res);
philpem@0 1247 FLAG_V = VFLAG_ADD_16(src, dst, res);
philpem@0 1248 FLAG_X = FLAG_C = CFLAG_16(res);
philpem@0 1249 FLAG_Z = MASK_OUT_ABOVE_16(res);
philpem@0 1250
philpem@0 1251 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
philpem@0 1252 }
philpem@0 1253
philpem@0 1254
philpem@0 1255 M68KMAKE_OP(addi, 16, ., .)
philpem@0 1256 {
philpem@0 1257 uint src = OPER_I_16();
philpem@0 1258 uint ea = M68KMAKE_GET_EA_AY_16;
philpem@0 1259 uint dst = m68ki_read_16(ea);
philpem@0 1260 uint res = src + dst;
philpem@0 1261
philpem@0 1262 FLAG_N = NFLAG_16(res);
philpem@0 1263 FLAG_V = VFLAG_ADD_16(src, dst, res);
philpem@0 1264 FLAG_X = FLAG_C = CFLAG_16(res);
philpem@0 1265 FLAG_Z = MASK_OUT_ABOVE_16(res);
philpem@0 1266
philpem@0 1267 m68ki_write_16(ea, FLAG_Z);
philpem@0 1268 }
philpem@0 1269
philpem@0 1270
philpem@0 1271 M68KMAKE_OP(addi, 32, ., d)
philpem@0 1272 {
philpem@0 1273 uint* r_dst = &DY;
philpem@0 1274 uint src = OPER_I_32();
philpem@0 1275 uint dst = *r_dst;
philpem@0 1276 uint res = src + dst;
philpem@0 1277
philpem@0 1278 FLAG_N = NFLAG_32(res);
philpem@0 1279 FLAG_V = VFLAG_ADD_32(src, dst, res);
philpem@0 1280 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
philpem@0 1281 FLAG_Z = MASK_OUT_ABOVE_32(res);
philpem@0 1282
philpem@0 1283 *r_dst = FLAG_Z;
philpem@0 1284 }
philpem@0 1285
philpem@0 1286
philpem@0 1287 M68KMAKE_OP(addi, 32, ., .)
philpem@0 1288 {
philpem@0 1289 uint src = OPER_I_32();
philpem@0 1290 uint ea = M68KMAKE_GET_EA_AY_32;
philpem@0 1291 uint dst = m68ki_read_32(ea);
philpem@0 1292 uint res = src + dst;
philpem@0 1293
philpem@0 1294 FLAG_N = NFLAG_32(res);
philpem@0 1295 FLAG_V = VFLAG_ADD_32(src, dst, res);
philpem@0 1296 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
philpem@0 1297 FLAG_Z = MASK_OUT_ABOVE_32(res);
philpem@0 1298
philpem@0 1299 m68ki_write_32(ea, FLAG_Z);
philpem@0 1300 }
philpem@0 1301
philpem@0 1302
philpem@0 1303 M68KMAKE_OP(addq, 8, ., d)
philpem@0 1304 {
philpem@0 1305 uint* r_dst = &DY;
philpem@0 1306 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
philpem@0 1307 uint dst = MASK_OUT_ABOVE_8(*r_dst);
philpem@0 1308 uint res = src + dst;
philpem@0 1309
philpem@0 1310 FLAG_N = NFLAG_8(res);
philpem@0 1311 FLAG_V = VFLAG_ADD_8(src, dst, res);
philpem@0 1312 FLAG_X = FLAG_C = CFLAG_8(res);
philpem@0 1313 FLAG_Z = MASK_OUT_ABOVE_8(res);
philpem@0 1314
philpem@0 1315 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
philpem@0 1316 }
philpem@0 1317
philpem@0 1318
philpem@0 1319 M68KMAKE_OP(addq, 8, ., .)
philpem@0 1320 {
philpem@0 1321 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
philpem@0 1322 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 1323 uint dst = m68ki_read_8(ea);
philpem@0 1324 uint res = src + dst;
philpem@0 1325
philpem@0 1326 FLAG_N = NFLAG_8(res);
philpem@0 1327 FLAG_V = VFLAG_ADD_8(src, dst, res);
philpem@0 1328 FLAG_X = FLAG_C = CFLAG_8(res);
philpem@0 1329 FLAG_Z = MASK_OUT_ABOVE_8(res);
philpem@0 1330
philpem@0 1331 m68ki_write_8(ea, FLAG_Z);
philpem@0 1332 }
philpem@0 1333
philpem@0 1334
philpem@0 1335 M68KMAKE_OP(addq, 16, ., d)
philpem@0 1336 {
philpem@0 1337 uint* r_dst = &DY;
philpem@0 1338 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
philpem@0 1339 uint dst = MASK_OUT_ABOVE_16(*r_dst);
philpem@0 1340 uint res = src + dst;
philpem@0 1341
philpem@0 1342 FLAG_N = NFLAG_16(res);
philpem@0 1343 FLAG_V = VFLAG_ADD_16(src, dst, res);
philpem@0 1344 FLAG_X = FLAG_C = CFLAG_16(res);
philpem@0 1345 FLAG_Z = MASK_OUT_ABOVE_16(res);
philpem@0 1346
philpem@0 1347 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
philpem@0 1348 }
philpem@0 1349
philpem@0 1350
philpem@0 1351 M68KMAKE_OP(addq, 16, ., a)
philpem@0 1352 {
philpem@0 1353 uint* r_dst = &AY;
philpem@0 1354
philpem@0 1355 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
philpem@0 1356 }
philpem@0 1357
philpem@0 1358
philpem@0 1359 M68KMAKE_OP(addq, 16, ., .)
philpem@0 1360 {
philpem@0 1361 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
philpem@0 1362 uint ea = M68KMAKE_GET_EA_AY_16;
philpem@0 1363 uint dst = m68ki_read_16(ea);
philpem@0 1364 uint res = src + dst;
philpem@0 1365
philpem@0 1366 FLAG_N = NFLAG_16(res);
philpem@0 1367 FLAG_V = VFLAG_ADD_16(src, dst, res);
philpem@0 1368 FLAG_X = FLAG_C = CFLAG_16(res);
philpem@0 1369 FLAG_Z = MASK_OUT_ABOVE_16(res);
philpem@0 1370
philpem@0 1371 m68ki_write_16(ea, FLAG_Z);
philpem@0 1372 }
philpem@0 1373
philpem@0 1374
philpem@0 1375 M68KMAKE_OP(addq, 32, ., d)
philpem@0 1376 {
philpem@0 1377 uint* r_dst = &DY;
philpem@0 1378 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
philpem@0 1379 uint dst = *r_dst;
philpem@0 1380 uint res = src + dst;
philpem@0 1381
philpem@0 1382 FLAG_N = NFLAG_32(res);
philpem@0 1383 FLAG_V = VFLAG_ADD_32(src, dst, res);
philpem@0 1384 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
philpem@0 1385 FLAG_Z = MASK_OUT_ABOVE_32(res);
philpem@0 1386
philpem@0 1387 *r_dst = FLAG_Z;
philpem@0 1388 }
philpem@0 1389
philpem@0 1390
philpem@0 1391 M68KMAKE_OP(addq, 32, ., a)
philpem@0 1392 {
philpem@0 1393 uint* r_dst = &AY;
philpem@0 1394
philpem@0 1395 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
philpem@0 1396 }
philpem@0 1397
philpem@0 1398
philpem@0 1399 M68KMAKE_OP(addq, 32, ., .)
philpem@0 1400 {
philpem@0 1401 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
philpem@0 1402 uint ea = M68KMAKE_GET_EA_AY_32;
philpem@0 1403 uint dst = m68ki_read_32(ea);
philpem@0 1404 uint res = src + dst;
philpem@0 1405
philpem@0 1406
philpem@0 1407 FLAG_N = NFLAG_32(res);
philpem@0 1408 FLAG_V = VFLAG_ADD_32(src, dst, res);
philpem@0 1409 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
philpem@0 1410 FLAG_Z = MASK_OUT_ABOVE_32(res);
philpem@0 1411
philpem@0 1412 m68ki_write_32(ea, FLAG_Z);
philpem@0 1413 }
philpem@0 1414
philpem@0 1415
philpem@0 1416 M68KMAKE_OP(addx, 8, rr, .)
philpem@0 1417 {
philpem@0 1418 uint* r_dst = &DX;
philpem@0 1419 uint src = MASK_OUT_ABOVE_8(DY);
philpem@0 1420 uint dst = MASK_OUT_ABOVE_8(*r_dst);
philpem@0 1421 uint res = src + dst + XFLAG_AS_1();
philpem@0 1422
philpem@0 1423 FLAG_N = NFLAG_8(res);
philpem@0 1424 FLAG_V = VFLAG_ADD_8(src, dst, res);
philpem@0 1425 FLAG_X = FLAG_C = CFLAG_8(res);
philpem@0 1426
philpem@0 1427 res = MASK_OUT_ABOVE_8(res);
philpem@0 1428 FLAG_Z |= res;
philpem@0 1429
philpem@0 1430 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
philpem@0 1431 }
philpem@0 1432
philpem@0 1433
philpem@0 1434 M68KMAKE_OP(addx, 16, rr, .)
philpem@0 1435 {
philpem@0 1436 uint* r_dst = &DX;
philpem@0 1437 uint src = MASK_OUT_ABOVE_16(DY);
philpem@0 1438 uint dst = MASK_OUT_ABOVE_16(*r_dst);
philpem@0 1439 uint res = src + dst + XFLAG_AS_1();
philpem@0 1440
philpem@0 1441 FLAG_N = NFLAG_16(res);
philpem@0 1442 FLAG_V = VFLAG_ADD_16(src, dst, res);
philpem@0 1443 FLAG_X = FLAG_C = CFLAG_16(res);
philpem@0 1444
philpem@0 1445 res = MASK_OUT_ABOVE_16(res);
philpem@0 1446 FLAG_Z |= res;
philpem@0 1447
philpem@0 1448 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
philpem@0 1449 }
philpem@0 1450
philpem@0 1451
philpem@0 1452 M68KMAKE_OP(addx, 32, rr, .)
philpem@0 1453 {
philpem@0 1454 uint* r_dst = &DX;
philpem@0 1455 uint src = DY;
philpem@0 1456 uint dst = *r_dst;
philpem@0 1457 uint res = src + dst + XFLAG_AS_1();
philpem@0 1458
philpem@0 1459 FLAG_N = NFLAG_32(res);
philpem@0 1460 FLAG_V = VFLAG_ADD_32(src, dst, res);
philpem@0 1461 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
philpem@0 1462
philpem@0 1463 res = MASK_OUT_ABOVE_32(res);
philpem@0 1464 FLAG_Z |= res;
philpem@0 1465
philpem@0 1466 *r_dst = res;
philpem@0 1467 }
philpem@0 1468
philpem@0 1469
philpem@0 1470 M68KMAKE_OP(addx, 8, mm, ax7)
philpem@0 1471 {
philpem@0 1472 uint src = OPER_AY_PD_8();
philpem@0 1473 uint ea = EA_A7_PD_8();
philpem@0 1474 uint dst = m68ki_read_8(ea);
philpem@0 1475 uint res = src + dst + XFLAG_AS_1();
philpem@0 1476
philpem@0 1477 FLAG_N = NFLAG_8(res);
philpem@0 1478 FLAG_V = VFLAG_ADD_8(src, dst, res);
philpem@0 1479 FLAG_X = FLAG_C = CFLAG_8(res);
philpem@0 1480
philpem@0 1481 res = MASK_OUT_ABOVE_8(res);
philpem@0 1482 FLAG_Z |= res;
philpem@0 1483
philpem@0 1484 m68ki_write_8(ea, res);
philpem@0 1485 }
philpem@0 1486
philpem@0 1487
philpem@0 1488 M68KMAKE_OP(addx, 8, mm, ay7)
philpem@0 1489 {
philpem@0 1490 uint src = OPER_A7_PD_8();
philpem@0 1491 uint ea = EA_AX_PD_8();
philpem@0 1492 uint dst = m68ki_read_8(ea);
philpem@0 1493 uint res = src + dst + XFLAG_AS_1();
philpem@0 1494
philpem@0 1495 FLAG_N = NFLAG_8(res);
philpem@0 1496 FLAG_V = VFLAG_ADD_8(src, dst, res);
philpem@0 1497 FLAG_X = FLAG_C = CFLAG_8(res);
philpem@0 1498
philpem@0 1499 res = MASK_OUT_ABOVE_8(res);
philpem@0 1500 FLAG_Z |= res;
philpem@0 1501
philpem@0 1502 m68ki_write_8(ea, res);
philpem@0 1503 }
philpem@0 1504
philpem@0 1505
philpem@0 1506 M68KMAKE_OP(addx, 8, mm, axy7)
philpem@0 1507 {
philpem@0 1508 uint src = OPER_A7_PD_8();
philpem@0 1509 uint ea = EA_A7_PD_8();
philpem@0 1510 uint dst = m68ki_read_8(ea);
philpem@0 1511 uint res = src + dst + XFLAG_AS_1();
philpem@0 1512
philpem@0 1513 FLAG_N = NFLAG_8(res);
philpem@0 1514 FLAG_V = VFLAG_ADD_8(src, dst, res);
philpem@0 1515 FLAG_X = FLAG_C = CFLAG_8(res);
philpem@0 1516
philpem@0 1517 res = MASK_OUT_ABOVE_8(res);
philpem@0 1518 FLAG_Z |= res;
philpem@0 1519
philpem@0 1520 m68ki_write_8(ea, res);
philpem@0 1521 }
philpem@0 1522
philpem@0 1523
philpem@0 1524 M68KMAKE_OP(addx, 8, mm, .)
philpem@0 1525 {
philpem@0 1526 uint src = OPER_AY_PD_8();
philpem@0 1527 uint ea = EA_AX_PD_8();
philpem@0 1528 uint dst = m68ki_read_8(ea);
philpem@0 1529 uint res = src + dst + XFLAG_AS_1();
philpem@0 1530
philpem@0 1531 FLAG_N = NFLAG_8(res);
philpem@0 1532 FLAG_V = VFLAG_ADD_8(src, dst, res);
philpem@0 1533 FLAG_X = FLAG_C = CFLAG_8(res);
philpem@0 1534
philpem@0 1535 res = MASK_OUT_ABOVE_8(res);
philpem@0 1536 FLAG_Z |= res;
philpem@0 1537
philpem@0 1538 m68ki_write_8(ea, res);
philpem@0 1539 }
philpem@0 1540
philpem@0 1541
philpem@0 1542 M68KMAKE_OP(addx, 16, mm, .)
philpem@0 1543 {
philpem@0 1544 uint src = OPER_AY_PD_16();
philpem@0 1545 uint ea = EA_AX_PD_16();
philpem@0 1546 uint dst = m68ki_read_16(ea);
philpem@0 1547 uint res = src + dst + XFLAG_AS_1();
philpem@0 1548
philpem@0 1549 FLAG_N = NFLAG_16(res);
philpem@0 1550 FLAG_V = VFLAG_ADD_16(src, dst, res);
philpem@0 1551 FLAG_X = FLAG_C = CFLAG_16(res);
philpem@0 1552
philpem@0 1553 res = MASK_OUT_ABOVE_16(res);
philpem@0 1554 FLAG_Z |= res;
philpem@0 1555
philpem@0 1556 m68ki_write_16(ea, res);
philpem@0 1557 }
philpem@0 1558
philpem@0 1559
philpem@0 1560 M68KMAKE_OP(addx, 32, mm, .)
philpem@0 1561 {
philpem@0 1562 uint src = OPER_AY_PD_32();
philpem@0 1563 uint ea = EA_AX_PD_32();
philpem@0 1564 uint dst = m68ki_read_32(ea);
philpem@0 1565 uint res = src + dst + XFLAG_AS_1();
philpem@0 1566
philpem@0 1567 FLAG_N = NFLAG_32(res);
philpem@0 1568 FLAG_V = VFLAG_ADD_32(src, dst, res);
philpem@0 1569 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
philpem@0 1570
philpem@0 1571 res = MASK_OUT_ABOVE_32(res);
philpem@0 1572 FLAG_Z |= res;
philpem@0 1573
philpem@0 1574 m68ki_write_32(ea, res);
philpem@0 1575 }
philpem@0 1576
philpem@0 1577
philpem@0 1578 M68KMAKE_OP(and, 8, er, d)
philpem@0 1579 {
philpem@0 1580 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));
philpem@0 1581
philpem@0 1582 FLAG_N = NFLAG_8(FLAG_Z);
philpem@0 1583 FLAG_C = CFLAG_CLEAR;
philpem@0 1584 FLAG_V = VFLAG_CLEAR;
philpem@0 1585 }
philpem@0 1586
philpem@0 1587
philpem@0 1588 M68KMAKE_OP(and, 8, er, .)
philpem@0 1589 {
philpem@0 1590 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));
philpem@0 1591
philpem@0 1592 FLAG_N = NFLAG_8(FLAG_Z);
philpem@0 1593 FLAG_C = CFLAG_CLEAR;
philpem@0 1594 FLAG_V = VFLAG_CLEAR;
philpem@0 1595 }
philpem@0 1596
philpem@0 1597
philpem@0 1598 M68KMAKE_OP(and, 16, er, d)
philpem@0 1599 {
philpem@0 1600 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));
philpem@0 1601
philpem@0 1602 FLAG_N = NFLAG_16(FLAG_Z);
philpem@0 1603 FLAG_C = CFLAG_CLEAR;
philpem@0 1604 FLAG_V = VFLAG_CLEAR;
philpem@0 1605 }
philpem@0 1606
philpem@0 1607
philpem@0 1608 M68KMAKE_OP(and, 16, er, .)
philpem@0 1609 {
philpem@0 1610 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));
philpem@0 1611
philpem@0 1612 FLAG_N = NFLAG_16(FLAG_Z);
philpem@0 1613 FLAG_C = CFLAG_CLEAR;
philpem@0 1614 FLAG_V = VFLAG_CLEAR;
philpem@0 1615 }
philpem@0 1616
philpem@0 1617
philpem@0 1618 M68KMAKE_OP(and, 32, er, d)
philpem@0 1619 {
philpem@0 1620 FLAG_Z = DX &= DY;
philpem@0 1621
philpem@0 1622 FLAG_N = NFLAG_32(FLAG_Z);
philpem@0 1623 FLAG_C = CFLAG_CLEAR;
philpem@0 1624 FLAG_V = VFLAG_CLEAR;
philpem@0 1625 }
philpem@0 1626
philpem@0 1627
philpem@0 1628 M68KMAKE_OP(and, 32, er, .)
philpem@0 1629 {
philpem@0 1630 FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;
philpem@0 1631
philpem@0 1632 FLAG_N = NFLAG_32(FLAG_Z);
philpem@0 1633 FLAG_C = CFLAG_CLEAR;
philpem@0 1634 FLAG_V = VFLAG_CLEAR;
philpem@0 1635 }
philpem@0 1636
philpem@0 1637
philpem@0 1638 M68KMAKE_OP(and, 8, re, .)
philpem@0 1639 {
philpem@0 1640 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 1641 uint res = DX & m68ki_read_8(ea);
philpem@0 1642
philpem@0 1643 FLAG_N = NFLAG_8(res);
philpem@0 1644 FLAG_C = CFLAG_CLEAR;
philpem@0 1645 FLAG_V = VFLAG_CLEAR;
philpem@0 1646 FLAG_Z = MASK_OUT_ABOVE_8(res);
philpem@0 1647
philpem@0 1648 m68ki_write_8(ea, FLAG_Z);
philpem@0 1649 }
philpem@0 1650
philpem@0 1651
philpem@0 1652 M68KMAKE_OP(and, 16, re, .)
philpem@0 1653 {
philpem@0 1654 uint ea = M68KMAKE_GET_EA_AY_16;
philpem@0 1655 uint res = DX & m68ki_read_16(ea);
philpem@0 1656
philpem@0 1657 FLAG_N = NFLAG_16(res);
philpem@0 1658 FLAG_C = CFLAG_CLEAR;
philpem@0 1659 FLAG_V = VFLAG_CLEAR;
philpem@0 1660 FLAG_Z = MASK_OUT_ABOVE_16(res);
philpem@0 1661
philpem@0 1662 m68ki_write_16(ea, FLAG_Z);
philpem@0 1663 }
philpem@0 1664
philpem@0 1665
philpem@0 1666 M68KMAKE_OP(and, 32, re, .)
philpem@0 1667 {
philpem@0 1668 uint ea = M68KMAKE_GET_EA_AY_32;
philpem@0 1669 uint res = DX & m68ki_read_32(ea);
philpem@0 1670
philpem@0 1671 FLAG_N = NFLAG_32(res);
philpem@0 1672 FLAG_Z = res;
philpem@0 1673 FLAG_C = CFLAG_CLEAR;
philpem@0 1674 FLAG_V = VFLAG_CLEAR;
philpem@0 1675
philpem@0 1676 m68ki_write_32(ea, res);
philpem@0 1677 }
philpem@0 1678
philpem@0 1679
philpem@0 1680 M68KMAKE_OP(andi, 8, ., d)
philpem@0 1681 {
philpem@0 1682 FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
philpem@0 1683
philpem@0 1684 FLAG_N = NFLAG_8(FLAG_Z);
philpem@0 1685 FLAG_C = CFLAG_CLEAR;
philpem@0 1686 FLAG_V = VFLAG_CLEAR;
philpem@0 1687 }
philpem@0 1688
philpem@0 1689
philpem@0 1690 M68KMAKE_OP(andi, 8, ., .)
philpem@0 1691 {
philpem@0 1692 uint src = OPER_I_8();
philpem@0 1693 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 1694 uint res = src & m68ki_read_8(ea);
philpem@0 1695
philpem@0 1696 FLAG_N = NFLAG_8(res);
philpem@0 1697 FLAG_Z = res;
philpem@0 1698 FLAG_C = CFLAG_CLEAR;
philpem@0 1699 FLAG_V = VFLAG_CLEAR;
philpem@0 1700
philpem@0 1701 m68ki_write_8(ea, res);
philpem@0 1702 }
philpem@0 1703
philpem@0 1704
philpem@0 1705 M68KMAKE_OP(andi, 16, ., d)
philpem@0 1706 {
philpem@0 1707 FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
philpem@0 1708
philpem@0 1709 FLAG_N = NFLAG_16(FLAG_Z);
philpem@0 1710 FLAG_C = CFLAG_CLEAR;
philpem@0 1711 FLAG_V = VFLAG_CLEAR;
philpem@0 1712 }
philpem@0 1713
philpem@0 1714
philpem@0 1715 M68KMAKE_OP(andi, 16, ., .)
philpem@0 1716 {
philpem@0 1717 uint src = OPER_I_16();
philpem@0 1718 uint ea = M68KMAKE_GET_EA_AY_16;
philpem@0 1719 uint res = src & m68ki_read_16(ea);
philpem@0 1720
philpem@0 1721 FLAG_N = NFLAG_16(res);
philpem@0 1722 FLAG_Z = res;
philpem@0 1723 FLAG_C = CFLAG_CLEAR;
philpem@0 1724 FLAG_V = VFLAG_CLEAR;
philpem@0 1725
philpem@0 1726 m68ki_write_16(ea, res);
philpem@0 1727 }
philpem@0 1728
philpem@0 1729
philpem@0 1730 M68KMAKE_OP(andi, 32, ., d)
philpem@0 1731 {
philpem@0 1732 FLAG_Z = DY &= (OPER_I_32());
philpem@0 1733
philpem@0 1734 FLAG_N = NFLAG_32(FLAG_Z);
philpem@0 1735 FLAG_C = CFLAG_CLEAR;
philpem@0 1736 FLAG_V = VFLAG_CLEAR;
philpem@0 1737 }
philpem@0 1738
philpem@0 1739
philpem@0 1740 M68KMAKE_OP(andi, 32, ., .)
philpem@0 1741 {
philpem@0 1742 uint src = OPER_I_32();
philpem@0 1743 uint ea = M68KMAKE_GET_EA_AY_32;
philpem@0 1744 uint res = src & m68ki_read_32(ea);
philpem@0 1745
philpem@0 1746 FLAG_N = NFLAG_32(res);
philpem@0 1747 FLAG_Z = res;
philpem@0 1748 FLAG_C = CFLAG_CLEAR;
philpem@0 1749 FLAG_V = VFLAG_CLEAR;
philpem@0 1750
philpem@0 1751 m68ki_write_32(ea, res);
philpem@0 1752 }
philpem@0 1753
philpem@0 1754
philpem@0 1755 M68KMAKE_OP(andi, 16, toc, .)
philpem@0 1756 {
philpem@0 1757 m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());
philpem@0 1758 }
philpem@0 1759
philpem@0 1760
philpem@0 1761 M68KMAKE_OP(andi, 16, tos, .)
philpem@0 1762 {
philpem@0 1763 if(FLAG_S)
philpem@0 1764 {
philpem@0 1765 uint src = OPER_I_16();
philpem@0 1766 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
philpem@0 1767 m68ki_set_sr(m68ki_get_sr() & src);
philpem@0 1768 return;
philpem@0 1769 }
philpem@0 1770 m68ki_exception_privilege_violation();
philpem@0 1771 }
philpem@0 1772
philpem@0 1773
philpem@0 1774 M68KMAKE_OP(asr, 8, s, .)
philpem@0 1775 {
philpem@0 1776 uint* r_dst = &DY;
philpem@0 1777 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
philpem@0 1778 uint src = MASK_OUT_ABOVE_8(*r_dst);
philpem@0 1779 uint res = src >> shift;
philpem@0 1780
philpem@0 1781 if(GET_MSB_8(src))
philpem@0 1782 res |= m68ki_shift_8_table[shift];
philpem@0 1783
philpem@0 1784 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
philpem@0 1785
philpem@0 1786 FLAG_N = NFLAG_8(res);
philpem@0 1787 FLAG_Z = res;
philpem@0 1788 FLAG_V = VFLAG_CLEAR;
philpem@0 1789 FLAG_X = FLAG_C = src << (9-shift);
philpem@0 1790 }
philpem@0 1791
philpem@0 1792
philpem@0 1793 M68KMAKE_OP(asr, 16, s, .)
philpem@0 1794 {
philpem@0 1795 uint* r_dst = &DY;
philpem@0 1796 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
philpem@0 1797 uint src = MASK_OUT_ABOVE_16(*r_dst);
philpem@0 1798 uint res = src >> shift;
philpem@0 1799
philpem@0 1800 if(GET_MSB_16(src))
philpem@0 1801 res |= m68ki_shift_16_table[shift];
philpem@0 1802
philpem@0 1803 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
philpem@0 1804
philpem@0 1805 FLAG_N = NFLAG_16(res);
philpem@0 1806 FLAG_Z = res;
philpem@0 1807 FLAG_V = VFLAG_CLEAR;
philpem@0 1808 FLAG_X = FLAG_C = src << (9-shift);
philpem@0 1809 }
philpem@0 1810
philpem@0 1811
philpem@0 1812 M68KMAKE_OP(asr, 32, s, .)
philpem@0 1813 {
philpem@0 1814 uint* r_dst = &DY;
philpem@0 1815 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
philpem@0 1816 uint src = *r_dst;
philpem@0 1817 uint res = src >> shift;
philpem@0 1818
philpem@0 1819 if(GET_MSB_32(src))
philpem@0 1820 res |= m68ki_shift_32_table[shift];
philpem@0 1821
philpem@0 1822 *r_dst = res;
philpem@0 1823
philpem@0 1824 FLAG_N = NFLAG_32(res);
philpem@0 1825 FLAG_Z = res;
philpem@0 1826 FLAG_V = VFLAG_CLEAR;
philpem@0 1827 FLAG_X = FLAG_C = src << (9-shift);
philpem@0 1828 }
philpem@0 1829
philpem@0 1830
philpem@0 1831 M68KMAKE_OP(asr, 8, r, .)
philpem@0 1832 {
philpem@0 1833 uint* r_dst = &DY;
philpem@0 1834 uint shift = DX & 0x3f;
philpem@0 1835 uint src = MASK_OUT_ABOVE_8(*r_dst);
philpem@0 1836 uint res = src >> shift;
philpem@0 1837
philpem@0 1838 if(shift != 0)
philpem@0 1839 {
philpem@0 1840 USE_CYCLES(shift<<CYC_SHIFT);
philpem@0 1841
philpem@0 1842 if(shift < 8)
philpem@0 1843 {
philpem@0 1844 if(GET_MSB_8(src))
philpem@0 1845 res |= m68ki_shift_8_table[shift];
philpem@0 1846
philpem@0 1847 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
philpem@0 1848
philpem@0 1849 FLAG_X = FLAG_C = src << (9-shift);
philpem@0 1850 FLAG_N = NFLAG_8(res);
philpem@0 1851 FLAG_Z = res;
philpem@0 1852 FLAG_V = VFLAG_CLEAR;
philpem@0 1853 return;
philpem@0 1854 }
philpem@0 1855
philpem@0 1856 if(GET_MSB_8(src))
philpem@0 1857 {
philpem@0 1858 *r_dst |= 0xff;
philpem@0 1859 FLAG_C = CFLAG_SET;
philpem@0 1860 FLAG_X = XFLAG_SET;
philpem@0 1861 FLAG_N = NFLAG_SET;
philpem@0 1862 FLAG_Z = ZFLAG_CLEAR;
philpem@0 1863 FLAG_V = VFLAG_CLEAR;
philpem@0 1864 return;
philpem@0 1865 }
philpem@0 1866
philpem@0 1867 *r_dst &= 0xffffff00;
philpem@0 1868 FLAG_C = CFLAG_CLEAR;
philpem@0 1869 FLAG_X = XFLAG_CLEAR;
philpem@0 1870 FLAG_N = NFLAG_CLEAR;
philpem@0 1871 FLAG_Z = ZFLAG_SET;
philpem@0 1872 FLAG_V = VFLAG_CLEAR;
philpem@0 1873 return;
philpem@0 1874 }
philpem@0 1875
philpem@0 1876 FLAG_C = CFLAG_CLEAR;
philpem@0 1877 FLAG_N = NFLAG_8(src);
philpem@0 1878 FLAG_Z = src;
philpem@0 1879 FLAG_V = VFLAG_CLEAR;
philpem@0 1880 }
philpem@0 1881
philpem@0 1882
philpem@0 1883 M68KMAKE_OP(asr, 16, r, .)
philpem@0 1884 {
philpem@0 1885 uint* r_dst = &DY;
philpem@0 1886 uint shift = DX & 0x3f;
philpem@0 1887 uint src = MASK_OUT_ABOVE_16(*r_dst);
philpem@0 1888 uint res = src >> shift;
philpem@0 1889
philpem@0 1890 if(shift != 0)
philpem@0 1891 {
philpem@0 1892 USE_CYCLES(shift<<CYC_SHIFT);
philpem@0 1893
philpem@0 1894 if(shift < 16)
philpem@0 1895 {
philpem@0 1896 if(GET_MSB_16(src))
philpem@0 1897 res |= m68ki_shift_16_table[shift];
philpem@0 1898
philpem@0 1899 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
philpem@0 1900
philpem@0 1901 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
philpem@0 1902 FLAG_N = NFLAG_16(res);
philpem@0 1903 FLAG_Z = res;
philpem@0 1904 FLAG_V = VFLAG_CLEAR;
philpem@0 1905 return;
philpem@0 1906 }
philpem@0 1907
philpem@0 1908 if(GET_MSB_16(src))
philpem@0 1909 {
philpem@0 1910 *r_dst |= 0xffff;
philpem@0 1911 FLAG_C = CFLAG_SET;
philpem@0 1912 FLAG_X = XFLAG_SET;
philpem@0 1913 FLAG_N = NFLAG_SET;
philpem@0 1914 FLAG_Z = ZFLAG_CLEAR;
philpem@0 1915 FLAG_V = VFLAG_CLEAR;
philpem@0 1916 return;
philpem@0 1917 }
philpem@0 1918
philpem@0 1919 *r_dst &= 0xffff0000;
philpem@0 1920 FLAG_C = CFLAG_CLEAR;
philpem@0 1921 FLAG_X = XFLAG_CLEAR;
philpem@0 1922 FLAG_N = NFLAG_CLEAR;
philpem@0 1923 FLAG_Z = ZFLAG_SET;
philpem@0 1924 FLAG_V = VFLAG_CLEAR;
philpem@0 1925 return;
philpem@0 1926 }
philpem@0 1927
philpem@0 1928 FLAG_C = CFLAG_CLEAR;
philpem@0 1929 FLAG_N = NFLAG_16(src);
philpem@0 1930 FLAG_Z = src;
philpem@0 1931 FLAG_V = VFLAG_CLEAR;
philpem@0 1932 }
philpem@0 1933
philpem@0 1934
philpem@0 1935 M68KMAKE_OP(asr, 32, r, .)
philpem@0 1936 {
philpem@0 1937 uint* r_dst = &DY;
philpem@0 1938 uint shift = DX & 0x3f;
philpem@0 1939 uint src = *r_dst;
philpem@0 1940 uint res = src >> shift;
philpem@0 1941
philpem@0 1942 if(shift != 0)
philpem@0 1943 {
philpem@0 1944 USE_CYCLES(shift<<CYC_SHIFT);
philpem@0 1945
philpem@0 1946 if(shift < 32)
philpem@0 1947 {
philpem@0 1948 if(GET_MSB_32(src))
philpem@0 1949 res |= m68ki_shift_32_table[shift];
philpem@0 1950
philpem@0 1951 *r_dst = res;
philpem@0 1952
philpem@0 1953 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
philpem@0 1954 FLAG_N = NFLAG_32(res);
philpem@0 1955 FLAG_Z = res;
philpem@0 1956 FLAG_V = VFLAG_CLEAR;
philpem@0 1957 return;
philpem@0 1958 }
philpem@0 1959
philpem@0 1960 if(GET_MSB_32(src))
philpem@0 1961 {
philpem@0 1962 *r_dst = 0xffffffff;
philpem@0 1963 FLAG_C = CFLAG_SET;
philpem@0 1964 FLAG_X = XFLAG_SET;
philpem@0 1965 FLAG_N = NFLAG_SET;
philpem@0 1966 FLAG_Z = ZFLAG_CLEAR;
philpem@0 1967 FLAG_V = VFLAG_CLEAR;
philpem@0 1968 return;
philpem@0 1969 }
philpem@0 1970
philpem@0 1971 *r_dst = 0;
philpem@0 1972 FLAG_C = CFLAG_CLEAR;
philpem@0 1973 FLAG_X = XFLAG_CLEAR;
philpem@0 1974 FLAG_N = NFLAG_CLEAR;
philpem@0 1975 FLAG_Z = ZFLAG_SET;
philpem@0 1976 FLAG_V = VFLAG_CLEAR;
philpem@0 1977 return;
philpem@0 1978 }
philpem@0 1979
philpem@0 1980 FLAG_C = CFLAG_CLEAR;
philpem@0 1981 FLAG_N = NFLAG_32(src);
philpem@0 1982 FLAG_Z = src;
philpem@0 1983 FLAG_V = VFLAG_CLEAR;
philpem@0 1984 }
philpem@0 1985
philpem@0 1986
philpem@0 1987 M68KMAKE_OP(asr, 16, ., .)
philpem@0 1988 {
philpem@0 1989 uint ea = M68KMAKE_GET_EA_AY_16;
philpem@0 1990 uint src = m68ki_read_16(ea);
philpem@0 1991 uint res = src >> 1;
philpem@0 1992
philpem@0 1993 if(GET_MSB_16(src))
philpem@0 1994 res |= 0x8000;
philpem@0 1995
philpem@0 1996 m68ki_write_16(ea, res);
philpem@0 1997
philpem@0 1998 FLAG_N = NFLAG_16(res);
philpem@0 1999 FLAG_Z = res;
philpem@0 2000 FLAG_V = VFLAG_CLEAR;
philpem@0 2001 FLAG_C = FLAG_X = src << 8;
philpem@0 2002 }
philpem@0 2003
philpem@0 2004
philpem@0 2005 M68KMAKE_OP(asl, 8, s, .)
philpem@0 2006 {
philpem@0 2007 uint* r_dst = &DY;
philpem@0 2008 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
philpem@0 2009 uint src = MASK_OUT_ABOVE_8(*r_dst);
philpem@0 2010 uint res = MASK_OUT_ABOVE_8(src << shift);
philpem@0 2011
philpem@0 2012 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
philpem@0 2013
philpem@0 2014 FLAG_X = FLAG_C = src << shift;
philpem@0 2015 FLAG_N = NFLAG_8(res);
philpem@0 2016 FLAG_Z = res;
philpem@0 2017 src &= m68ki_shift_8_table[shift + 1];
philpem@0 2018 FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
philpem@0 2019 }
philpem@0 2020
philpem@0 2021
philpem@0 2022 M68KMAKE_OP(asl, 16, s, .)
philpem@0 2023 {
philpem@0 2024 uint* r_dst = &DY;
philpem@0 2025 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
philpem@0 2026 uint src = MASK_OUT_ABOVE_16(*r_dst);
philpem@0 2027 uint res = MASK_OUT_ABOVE_16(src << shift);
philpem@0 2028
philpem@0 2029 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
philpem@0 2030
philpem@0 2031 FLAG_N = NFLAG_16(res);
philpem@0 2032 FLAG_Z = res;
philpem@0 2033 FLAG_X = FLAG_C = src >> (8-shift);
philpem@0 2034 src &= m68ki_shift_16_table[shift + 1];
philpem@0 2035 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
philpem@0 2036 }
philpem@0 2037
philpem@0 2038
philpem@0 2039 M68KMAKE_OP(asl, 32, s, .)
philpem@0 2040 {
philpem@0 2041 uint* r_dst = &DY;
philpem@0 2042 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
philpem@0 2043 uint src = *r_dst;
philpem@0 2044 uint res = MASK_OUT_ABOVE_32(src << shift);
philpem@0 2045
philpem@0 2046 *r_dst = res;
philpem@0 2047
philpem@0 2048 FLAG_N = NFLAG_32(res);
philpem@0 2049 FLAG_Z = res;
philpem@0 2050 FLAG_X = FLAG_C = src >> (24-shift);
philpem@0 2051 src &= m68ki_shift_32_table[shift + 1];
philpem@0 2052 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
philpem@0 2053 }
philpem@0 2054
philpem@0 2055
philpem@0 2056 M68KMAKE_OP(asl, 8, r, .)
philpem@0 2057 {
philpem@0 2058 uint* r_dst = &DY;
philpem@0 2059 uint shift = DX & 0x3f;
philpem@0 2060 uint src = MASK_OUT_ABOVE_8(*r_dst);
philpem@0 2061 uint res = MASK_OUT_ABOVE_8(src << shift);
philpem@0 2062
philpem@0 2063 if(shift != 0)
philpem@0 2064 {
philpem@0 2065 USE_CYCLES(shift<<CYC_SHIFT);
philpem@0 2066
philpem@0 2067 if(shift < 8)
philpem@0 2068 {
philpem@0 2069 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
philpem@0 2070 FLAG_X = FLAG_C = src << shift;
philpem@0 2071 FLAG_N = NFLAG_8(res);
philpem@0 2072 FLAG_Z = res;
philpem@0 2073 src &= m68ki_shift_8_table[shift + 1];
philpem@0 2074 FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;
philpem@0 2075 return;
philpem@0 2076 }
philpem@0 2077
philpem@0 2078 *r_dst &= 0xffffff00;
philpem@0 2079 FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;
philpem@0 2080 FLAG_N = NFLAG_CLEAR;
philpem@0 2081 FLAG_Z = ZFLAG_SET;
philpem@0 2082 FLAG_V = (!(src == 0))<<7;
philpem@0 2083 return;
philpem@0 2084 }
philpem@0 2085
philpem@0 2086 FLAG_C = CFLAG_CLEAR;
philpem@0 2087 FLAG_N = NFLAG_8(src);
philpem@0 2088 FLAG_Z = src;
philpem@0 2089 FLAG_V = VFLAG_CLEAR;
philpem@0 2090 }
philpem@0 2091
philpem@0 2092
philpem@0 2093 M68KMAKE_OP(asl, 16, r, .)
philpem@0 2094 {
philpem@0 2095 uint* r_dst = &DY;
philpem@0 2096 uint shift = DX & 0x3f;
philpem@0 2097 uint src = MASK_OUT_ABOVE_16(*r_dst);
philpem@0 2098 uint res = MASK_OUT_ABOVE_16(src << shift);
philpem@0 2099
philpem@0 2100 if(shift != 0)
philpem@0 2101 {
philpem@0 2102 USE_CYCLES(shift<<CYC_SHIFT);
philpem@0 2103
philpem@0 2104 if(shift < 16)
philpem@0 2105 {
philpem@0 2106 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
philpem@0 2107 FLAG_X = FLAG_C = (src << shift) >> 8;
philpem@0 2108 FLAG_N = NFLAG_16(res);
philpem@0 2109 FLAG_Z = res;
philpem@0 2110 src &= m68ki_shift_16_table[shift + 1];
philpem@0 2111 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
philpem@0 2112 return;
philpem@0 2113 }
philpem@0 2114
philpem@0 2115 *r_dst &= 0xffff0000;
philpem@0 2116 FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;
philpem@0 2117 FLAG_N = NFLAG_CLEAR;
philpem@0 2118 FLAG_Z = ZFLAG_SET;
philpem@0 2119 FLAG_V = (!(src == 0))<<7;
philpem@0 2120 return;
philpem@0 2121 }
philpem@0 2122
philpem@0 2123 FLAG_C = CFLAG_CLEAR;
philpem@0 2124 FLAG_N = NFLAG_16(src);
philpem@0 2125 FLAG_Z = src;
philpem@0 2126 FLAG_V = VFLAG_CLEAR;
philpem@0 2127 }
philpem@0 2128
philpem@0 2129
philpem@0 2130 M68KMAKE_OP(asl, 32, r, .)
philpem@0 2131 {
philpem@0 2132 uint* r_dst = &DY;
philpem@0 2133 uint shift = DX & 0x3f;
philpem@0 2134 uint src = *r_dst;
philpem@0 2135 uint res = MASK_OUT_ABOVE_32(src << shift);
philpem@0 2136
philpem@0 2137 if(shift != 0)
philpem@0 2138 {
philpem@0 2139 USE_CYCLES(shift<<CYC_SHIFT);
philpem@0 2140
philpem@0 2141 if(shift < 32)
philpem@0 2142 {
philpem@0 2143 *r_dst = res;
philpem@0 2144 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
philpem@0 2145 FLAG_N = NFLAG_32(res);
philpem@0 2146 FLAG_Z = res;
philpem@0 2147 src &= m68ki_shift_32_table[shift + 1];
philpem@0 2148 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
philpem@0 2149 return;
philpem@0 2150 }
philpem@0 2151
philpem@0 2152 *r_dst = 0;
philpem@0 2153 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
philpem@0 2154 FLAG_N = NFLAG_CLEAR;
philpem@0 2155 FLAG_Z = ZFLAG_SET;
philpem@0 2156 FLAG_V = (!(src == 0))<<7;
philpem@0 2157 return;
philpem@0 2158 }
philpem@0 2159
philpem@0 2160 FLAG_C = CFLAG_CLEAR;
philpem@0 2161 FLAG_N = NFLAG_32(src);
philpem@0 2162 FLAG_Z = src;
philpem@0 2163 FLAG_V = VFLAG_CLEAR;
philpem@0 2164 }
philpem@0 2165
philpem@0 2166
philpem@0 2167 M68KMAKE_OP(asl, 16, ., .)
philpem@0 2168 {
philpem@0 2169 uint ea = M68KMAKE_GET_EA_AY_16;
philpem@0 2170 uint src = m68ki_read_16(ea);
philpem@0 2171 uint res = MASK_OUT_ABOVE_16(src << 1);
philpem@0 2172
philpem@0 2173 m68ki_write_16(ea, res);
philpem@0 2174
philpem@0 2175 FLAG_N = NFLAG_16(res);
philpem@0 2176 FLAG_Z = res;
philpem@0 2177 FLAG_X = FLAG_C = src >> 7;
philpem@0 2178 src &= 0xc000;
philpem@0 2179 FLAG_V = (!(src == 0 || src == 0xc000))<<7;
philpem@0 2180 }
philpem@0 2181
philpem@0 2182
philpem@0 2183 M68KMAKE_OP(bcc, 8, ., .)
philpem@0 2184 {
philpem@0 2185 if(M68KMAKE_CC)
philpem@0 2186 {
philpem@0 2187 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
philpem@0 2188 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
philpem@0 2189 return;
philpem@0 2190 }
philpem@0 2191 USE_CYCLES(CYC_BCC_NOTAKE_B);
philpem@0 2192 }
philpem@0 2193
philpem@0 2194
philpem@0 2195 M68KMAKE_OP(bcc, 16, ., .)
philpem@0 2196 {
philpem@0 2197 if(M68KMAKE_CC)
philpem@0 2198 {
philpem@0 2199 uint offset = OPER_I_16();
philpem@0 2200 REG_PC -= 2;
philpem@0 2201 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
philpem@0 2202 m68ki_branch_16(offset);
philpem@0 2203 return;
philpem@0 2204 }
philpem@0 2205 REG_PC += 2;
philpem@0 2206 USE_CYCLES(CYC_BCC_NOTAKE_W);
philpem@0 2207 }
philpem@0 2208
philpem@0 2209
philpem@0 2210 M68KMAKE_OP(bcc, 32, ., .)
philpem@0 2211 {
philpem@0 2212 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 2213 {
philpem@0 2214 if(M68KMAKE_CC)
philpem@0 2215 {
philpem@0 2216 uint offset = OPER_I_32();
philpem@0 2217 REG_PC -= 4;
philpem@0 2218 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
philpem@0 2219 m68ki_branch_32(offset);
philpem@0 2220 return;
philpem@0 2221 }
philpem@0 2222 REG_PC += 4;
philpem@0 2223 return;
philpem@0 2224 }
philpem@0 2225 m68ki_exception_illegal();
philpem@0 2226 }
philpem@0 2227
philpem@0 2228
philpem@0 2229 M68KMAKE_OP(bchg, 32, r, d)
philpem@0 2230 {
philpem@0 2231 uint* r_dst = &DY;
philpem@0 2232 uint mask = 1 << (DX & 0x1f);
philpem@0 2233
philpem@0 2234 FLAG_Z = *r_dst & mask;
philpem@0 2235 *r_dst ^= mask;
philpem@0 2236 }
philpem@0 2237
philpem@0 2238
philpem@0 2239 M68KMAKE_OP(bchg, 8, r, .)
philpem@0 2240 {
philpem@0 2241 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 2242 uint src = m68ki_read_8(ea);
philpem@0 2243 uint mask = 1 << (DX & 7);
philpem@0 2244
philpem@0 2245 FLAG_Z = src & mask;
philpem@0 2246 m68ki_write_8(ea, src ^ mask);
philpem@0 2247 }
philpem@0 2248
philpem@0 2249
philpem@0 2250 M68KMAKE_OP(bchg, 32, s, d)
philpem@0 2251 {
philpem@0 2252 uint* r_dst = &DY;
philpem@0 2253 uint mask = 1 << (OPER_I_8() & 0x1f);
philpem@0 2254
philpem@0 2255 FLAG_Z = *r_dst & mask;
philpem@0 2256 *r_dst ^= mask;
philpem@0 2257 }
philpem@0 2258
philpem@0 2259
philpem@0 2260 M68KMAKE_OP(bchg, 8, s, .)
philpem@0 2261 {
philpem@0 2262 uint mask = 1 << (OPER_I_8() & 7);
philpem@0 2263 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 2264 uint src = m68ki_read_8(ea);
philpem@0 2265
philpem@0 2266 FLAG_Z = src & mask;
philpem@0 2267 m68ki_write_8(ea, src ^ mask);
philpem@0 2268 }
philpem@0 2269
philpem@0 2270
philpem@0 2271 M68KMAKE_OP(bclr, 32, r, d)
philpem@0 2272 {
philpem@0 2273 uint* r_dst = &DY;
philpem@0 2274 uint mask = 1 << (DX & 0x1f);
philpem@0 2275
philpem@0 2276 FLAG_Z = *r_dst & mask;
philpem@0 2277 *r_dst &= ~mask;
philpem@0 2278 }
philpem@0 2279
philpem@0 2280
philpem@0 2281 M68KMAKE_OP(bclr, 8, r, .)
philpem@0 2282 {
philpem@0 2283 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 2284 uint src = m68ki_read_8(ea);
philpem@0 2285 uint mask = 1 << (DX & 7);
philpem@0 2286
philpem@0 2287 FLAG_Z = src & mask;
philpem@0 2288 m68ki_write_8(ea, src & ~mask);
philpem@0 2289 }
philpem@0 2290
philpem@0 2291
philpem@0 2292 M68KMAKE_OP(bclr, 32, s, d)
philpem@0 2293 {
philpem@0 2294 uint* r_dst = &DY;
philpem@0 2295 uint mask = 1 << (OPER_I_8() & 0x1f);
philpem@0 2296
philpem@0 2297 FLAG_Z = *r_dst & mask;
philpem@0 2298 *r_dst &= ~mask;
philpem@0 2299 }
philpem@0 2300
philpem@0 2301
philpem@0 2302 M68KMAKE_OP(bclr, 8, s, .)
philpem@0 2303 {
philpem@0 2304 uint mask = 1 << (OPER_I_8() & 7);
philpem@0 2305 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 2306 uint src = m68ki_read_8(ea);
philpem@0 2307
philpem@0 2308 FLAG_Z = src & mask;
philpem@0 2309 m68ki_write_8(ea, src & ~mask);
philpem@0 2310 }
philpem@0 2311
philpem@0 2312
philpem@0 2313 M68KMAKE_OP(bfchg, 32, ., d)
philpem@0 2314 {
philpem@0 2315 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 2316 {
philpem@0 2317 uint word2 = OPER_I_16();
philpem@0 2318 uint offset = (word2>>6)&31;
philpem@0 2319 uint width = word2;
philpem@0 2320 uint* data = &DY;
philpem@0 2321 uint64 mask;
philpem@0 2322
philpem@0 2323
philpem@0 2324 if(BIT_B(word2))
philpem@0 2325 offset = REG_D[offset&7];
philpem@0 2326 if(BIT_5(word2))
philpem@0 2327 width = REG_D[width&7];
philpem@0 2328
philpem@0 2329 offset &= 31;
philpem@0 2330 width = ((width-1) & 31) + 1;
philpem@0 2331
philpem@0 2332 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
philpem@0 2333 mask = ROR_32(mask, offset);
philpem@0 2334
philpem@0 2335 FLAG_N = NFLAG_32(*data<<offset);
philpem@0 2336 FLAG_Z = *data & mask;
philpem@0 2337 FLAG_V = VFLAG_CLEAR;
philpem@0 2338 FLAG_C = CFLAG_CLEAR;
philpem@0 2339
philpem@0 2340 *data ^= mask;
philpem@0 2341
philpem@0 2342 return;
philpem@0 2343 }
philpem@0 2344 m68ki_exception_illegal();
philpem@0 2345 }
philpem@0 2346
philpem@0 2347
philpem@0 2348 M68KMAKE_OP(bfchg, 32, ., .)
philpem@0 2349 {
philpem@0 2350 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 2351 {
philpem@0 2352 uint word2 = OPER_I_16();
philpem@0 2353 sint offset = (word2>>6)&31;
philpem@0 2354 uint width = word2;
philpem@0 2355 uint mask_base;
philpem@0 2356 uint data_long;
philpem@0 2357 uint mask_long;
philpem@0 2358 uint data_byte = 0;
philpem@0 2359 uint mask_byte = 0;
philpem@0 2360 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 2361
philpem@0 2362
philpem@0 2363 if(BIT_B(word2))
philpem@0 2364 offset = MAKE_INT_32(REG_D[offset&7]);
philpem@0 2365 if(BIT_5(word2))
philpem@0 2366 width = REG_D[width&7];
philpem@0 2367
philpem@0 2368 /* Offset is signed so we have to use ugly math =( */
philpem@0 2369 ea += offset / 8;
philpem@0 2370 offset %= 8;
philpem@0 2371 if(offset < 0)
philpem@0 2372 {
philpem@0 2373 offset += 8;
philpem@0 2374 ea--;
philpem@0 2375 }
philpem@0 2376 width = ((width-1) & 31) + 1;
philpem@0 2377
philpem@0 2378 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
philpem@0 2379 mask_long = mask_base >> offset;
philpem@0 2380
philpem@0 2381 data_long = m68ki_read_32(ea);
philpem@0 2382 FLAG_N = NFLAG_32(data_long << offset);
philpem@0 2383 FLAG_Z = data_long & mask_long;
philpem@0 2384 FLAG_V = VFLAG_CLEAR;
philpem@0 2385 FLAG_C = CFLAG_CLEAR;
philpem@0 2386
philpem@0 2387 m68ki_write_32(ea, data_long ^ mask_long);
philpem@0 2388
philpem@0 2389 if((width + offset) > 32)
philpem@0 2390 {
philpem@0 2391 mask_byte = MASK_OUT_ABOVE_8(mask_base);
philpem@0 2392 data_byte = m68ki_read_8(ea+4);
philpem@0 2393 FLAG_Z |= (data_byte & mask_byte);
philpem@0 2394 m68ki_write_8(ea+4, data_byte ^ mask_byte);
philpem@0 2395 }
philpem@0 2396 return;
philpem@0 2397 }
philpem@0 2398 m68ki_exception_illegal();
philpem@0 2399 }
philpem@0 2400
philpem@0 2401
philpem@0 2402 M68KMAKE_OP(bfclr, 32, ., d)
philpem@0 2403 {
philpem@0 2404 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 2405 {
philpem@0 2406 uint word2 = OPER_I_16();
philpem@0 2407 uint offset = (word2>>6)&31;
philpem@0 2408 uint width = word2;
philpem@0 2409 uint* data = &DY;
philpem@0 2410 uint64 mask;
philpem@0 2411
philpem@0 2412
philpem@0 2413 if(BIT_B(word2))
philpem@0 2414 offset = REG_D[offset&7];
philpem@0 2415 if(BIT_5(word2))
philpem@0 2416 width = REG_D[width&7];
philpem@0 2417
philpem@0 2418
philpem@0 2419 offset &= 31;
philpem@0 2420 width = ((width-1) & 31) + 1;
philpem@0 2421
philpem@0 2422
philpem@0 2423 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
philpem@0 2424 mask = ROR_32(mask, offset);
philpem@0 2425
philpem@0 2426 FLAG_N = NFLAG_32(*data<<offset);
philpem@0 2427 FLAG_Z = *data & mask;
philpem@0 2428 FLAG_V = VFLAG_CLEAR;
philpem@0 2429 FLAG_C = CFLAG_CLEAR;
philpem@0 2430
philpem@0 2431 *data &= ~mask;
philpem@0 2432
philpem@0 2433 return;
philpem@0 2434 }
philpem@0 2435 m68ki_exception_illegal();
philpem@0 2436 }
philpem@0 2437
philpem@0 2438
philpem@0 2439 M68KMAKE_OP(bfclr, 32, ., .)
philpem@0 2440 {
philpem@0 2441 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 2442 {
philpem@0 2443 uint word2 = OPER_I_16();
philpem@0 2444 sint offset = (word2>>6)&31;
philpem@0 2445 uint width = word2;
philpem@0 2446 uint mask_base;
philpem@0 2447 uint data_long;
philpem@0 2448 uint mask_long;
philpem@0 2449 uint data_byte = 0;
philpem@0 2450 uint mask_byte = 0;
philpem@0 2451 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 2452
philpem@0 2453
philpem@0 2454 if(BIT_B(word2))
philpem@0 2455 offset = MAKE_INT_32(REG_D[offset&7]);
philpem@0 2456 if(BIT_5(word2))
philpem@0 2457 width = REG_D[width&7];
philpem@0 2458
philpem@0 2459 /* Offset is signed so we have to use ugly math =( */
philpem@0 2460 ea += offset / 8;
philpem@0 2461 offset %= 8;
philpem@0 2462 if(offset < 0)
philpem@0 2463 {
philpem@0 2464 offset += 8;
philpem@0 2465 ea--;
philpem@0 2466 }
philpem@0 2467 width = ((width-1) & 31) + 1;
philpem@0 2468
philpem@0 2469 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
philpem@0 2470 mask_long = mask_base >> offset;
philpem@0 2471
philpem@0 2472 data_long = m68ki_read_32(ea);
philpem@0 2473 FLAG_N = NFLAG_32(data_long << offset);
philpem@0 2474 FLAG_Z = data_long & mask_long;
philpem@0 2475 FLAG_V = VFLAG_CLEAR;
philpem@0 2476 FLAG_C = CFLAG_CLEAR;
philpem@0 2477
philpem@0 2478 m68ki_write_32(ea, data_long & ~mask_long);
philpem@0 2479
philpem@0 2480 if((width + offset) > 32)
philpem@0 2481 {
philpem@0 2482 mask_byte = MASK_OUT_ABOVE_8(mask_base);
philpem@0 2483 data_byte = m68ki_read_8(ea+4);
philpem@0 2484 FLAG_Z |= (data_byte & mask_byte);
philpem@0 2485 m68ki_write_8(ea+4, data_byte & ~mask_byte);
philpem@0 2486 }
philpem@0 2487 return;
philpem@0 2488 }
philpem@0 2489 m68ki_exception_illegal();
philpem@0 2490 }
philpem@0 2491
philpem@0 2492
philpem@0 2493 M68KMAKE_OP(bfexts, 32, ., d)
philpem@0 2494 {
philpem@0 2495 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 2496 {
philpem@0 2497 uint word2 = OPER_I_16();
philpem@0 2498 uint offset = (word2>>6)&31;
philpem@0 2499 uint width = word2;
philpem@0 2500 uint64 data = DY;
philpem@0 2501
philpem@0 2502
philpem@0 2503 if(BIT_B(word2))
philpem@0 2504 offset = REG_D[offset&7];
philpem@0 2505 if(BIT_5(word2))
philpem@0 2506 width = REG_D[width&7];
philpem@0 2507
philpem@0 2508 offset &= 31;
philpem@0 2509 width = ((width-1) & 31) + 1;
philpem@0 2510
philpem@0 2511 data = ROL_32(data, offset);
philpem@0 2512 FLAG_N = NFLAG_32(data);
philpem@0 2513 data = MAKE_INT_32(data) >> (32 - width);
philpem@0 2514
philpem@0 2515 FLAG_Z = data;
philpem@0 2516 FLAG_V = VFLAG_CLEAR;
philpem@0 2517 FLAG_C = CFLAG_CLEAR;
philpem@0 2518
philpem@0 2519 REG_D[(word2>>12)&7] = data;
philpem@0 2520
philpem@0 2521 return;
philpem@0 2522 }
philpem@0 2523 m68ki_exception_illegal();
philpem@0 2524 }
philpem@0 2525
philpem@0 2526
philpem@0 2527 M68KMAKE_OP(bfexts, 32, ., .)
philpem@0 2528 {
philpem@0 2529 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 2530 {
philpem@0 2531 uint word2 = OPER_I_16();
philpem@0 2532 sint offset = (word2>>6)&31;
philpem@0 2533 uint width = word2;
philpem@0 2534 uint data;
philpem@0 2535 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 2536
philpem@0 2537
philpem@0 2538 if(BIT_B(word2))
philpem@0 2539 offset = MAKE_INT_32(REG_D[offset&7]);
philpem@0 2540 if(BIT_5(word2))
philpem@0 2541 width = REG_D[width&7];
philpem@0 2542
philpem@0 2543 /* Offset is signed so we have to use ugly math =( */
philpem@0 2544 ea += offset / 8;
philpem@0 2545 offset %= 8;
philpem@0 2546 if(offset < 0)
philpem@0 2547 {
philpem@0 2548 offset += 8;
philpem@0 2549 ea--;
philpem@0 2550 }
philpem@0 2551 width = ((width-1) & 31) + 1;
philpem@0 2552
philpem@0 2553 data = m68ki_read_32(ea);
philpem@0 2554
philpem@0 2555 data = MASK_OUT_ABOVE_32(data<<offset);
philpem@0 2556
philpem@0 2557 if((offset+width) > 32)
philpem@0 2558 data |= (m68ki_read_8(ea+4) << offset) >> 8;
philpem@0 2559
philpem@0 2560 FLAG_N = NFLAG_32(data);
philpem@0 2561 data = MAKE_INT_32(data) >> (32 - width);
philpem@0 2562
philpem@0 2563 FLAG_Z = data;
philpem@0 2564 FLAG_V = VFLAG_CLEAR;
philpem@0 2565 FLAG_C = CFLAG_CLEAR;
philpem@0 2566
philpem@0 2567 REG_D[(word2 >> 12) & 7] = data;
philpem@0 2568
philpem@0 2569 return;
philpem@0 2570 }
philpem@0 2571 m68ki_exception_illegal();
philpem@0 2572 }
philpem@0 2573
philpem@0 2574
philpem@0 2575 M68KMAKE_OP(bfextu, 32, ., d)
philpem@0 2576 {
philpem@0 2577 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 2578 {
philpem@0 2579 uint word2 = OPER_I_16();
philpem@0 2580 uint offset = (word2>>6)&31;
philpem@0 2581 uint width = word2;
philpem@0 2582 uint64 data = DY;
philpem@0 2583
philpem@0 2584
philpem@0 2585 if(BIT_B(word2))
philpem@0 2586 offset = REG_D[offset&7];
philpem@0 2587 if(BIT_5(word2))
philpem@0 2588 width = REG_D[width&7];
philpem@0 2589
philpem@0 2590 offset &= 31;
philpem@0 2591 width = ((width-1) & 31) + 1;
philpem@0 2592
philpem@0 2593 data = ROL_32(data, offset);
philpem@0 2594 FLAG_N = NFLAG_32(data);
philpem@0 2595 data >>= 32 - width;
philpem@0 2596
philpem@0 2597 FLAG_Z = data;
philpem@0 2598 FLAG_V = VFLAG_CLEAR;
philpem@0 2599 FLAG_C = CFLAG_CLEAR;
philpem@0 2600
philpem@0 2601 REG_D[(word2>>12)&7] = data;
philpem@0 2602
philpem@0 2603 return;
philpem@0 2604 }
philpem@0 2605 m68ki_exception_illegal();
philpem@0 2606 }
philpem@0 2607
philpem@0 2608
philpem@0 2609 M68KMAKE_OP(bfextu, 32, ., .)
philpem@0 2610 {
philpem@0 2611 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 2612 {
philpem@0 2613 uint word2 = OPER_I_16();
philpem@0 2614 sint offset = (word2>>6)&31;
philpem@0 2615 uint width = word2;
philpem@0 2616 uint data;
philpem@0 2617 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 2618
philpem@0 2619
philpem@0 2620 if(BIT_B(word2))
philpem@0 2621 offset = MAKE_INT_32(REG_D[offset&7]);
philpem@0 2622 if(BIT_5(word2))
philpem@0 2623 width = REG_D[width&7];
philpem@0 2624
philpem@0 2625 /* Offset is signed so we have to use ugly math =( */
philpem@0 2626 ea += offset / 8;
philpem@0 2627 offset %= 8;
philpem@0 2628 if(offset < 0)
philpem@0 2629 {
philpem@0 2630 offset += 8;
philpem@0 2631 ea--;
philpem@0 2632 }
philpem@0 2633 width = ((width-1) & 31) + 1;
philpem@0 2634
philpem@0 2635 data = m68ki_read_32(ea);
philpem@0 2636 data = MASK_OUT_ABOVE_32(data<<offset);
philpem@0 2637
philpem@0 2638 if((offset+width) > 32)
philpem@0 2639 data |= (m68ki_read_8(ea+4) << offset) >> 8;
philpem@0 2640
philpem@0 2641 FLAG_N = NFLAG_32(data);
philpem@0 2642 data >>= (32 - width);
philpem@0 2643
philpem@0 2644 FLAG_Z = data;
philpem@0 2645 FLAG_V = VFLAG_CLEAR;
philpem@0 2646 FLAG_C = CFLAG_CLEAR;
philpem@0 2647
philpem@0 2648 REG_D[(word2 >> 12) & 7] = data;
philpem@0 2649
philpem@0 2650 return;
philpem@0 2651 }
philpem@0 2652 m68ki_exception_illegal();
philpem@0 2653 }
philpem@0 2654
philpem@0 2655
philpem@0 2656 M68KMAKE_OP(bfffo, 32, ., d)
philpem@0 2657 {
philpem@0 2658 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 2659 {
philpem@0 2660 uint word2 = OPER_I_16();
philpem@0 2661 uint offset = (word2>>6)&31;
philpem@0 2662 uint width = word2;
philpem@0 2663 uint64 data = DY;
philpem@0 2664 uint bit;
philpem@0 2665
philpem@0 2666
philpem@0 2667 if(BIT_B(word2))
philpem@0 2668 offset = REG_D[offset&7];
philpem@0 2669 if(BIT_5(word2))
philpem@0 2670 width = REG_D[width&7];
philpem@0 2671
philpem@0 2672 offset &= 31;
philpem@0 2673 width = ((width-1) & 31) + 1;
philpem@0 2674
philpem@0 2675 data = ROL_32(data, offset);
philpem@0 2676 FLAG_N = NFLAG_32(data);
philpem@0 2677 data >>= 32 - width;
philpem@0 2678
philpem@0 2679 FLAG_Z = data;
philpem@0 2680 FLAG_V = VFLAG_CLEAR;
philpem@0 2681 FLAG_C = CFLAG_CLEAR;
philpem@0 2682
philpem@0 2683 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
philpem@0 2684 offset++;
philpem@0 2685
philpem@0 2686 REG_D[(word2>>12)&7] = offset;
philpem@0 2687
philpem@0 2688 return;
philpem@0 2689 }
philpem@0 2690 m68ki_exception_illegal();
philpem@0 2691 }
philpem@0 2692
philpem@0 2693
philpem@0 2694 M68KMAKE_OP(bfffo, 32, ., .)
philpem@0 2695 {
philpem@0 2696 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 2697 {
philpem@0 2698 uint word2 = OPER_I_16();
philpem@0 2699 sint offset = (word2>>6)&31;
philpem@0 2700 sint local_offset;
philpem@0 2701 uint width = word2;
philpem@0 2702 uint data;
philpem@0 2703 uint bit;
philpem@0 2704 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 2705
philpem@0 2706
philpem@0 2707 if(BIT_B(word2))
philpem@0 2708 offset = MAKE_INT_32(REG_D[offset&7]);
philpem@0 2709 if(BIT_5(word2))
philpem@0 2710 width = REG_D[width&7];
philpem@0 2711
philpem@0 2712 /* Offset is signed so we have to use ugly math =( */
philpem@0 2713 ea += offset / 8;
philpem@0 2714 local_offset = offset % 8;
philpem@0 2715 if(local_offset < 0)
philpem@0 2716 {
philpem@0 2717 local_offset += 8;
philpem@0 2718 ea--;
philpem@0 2719 }
philpem@0 2720 width = ((width-1) & 31) + 1;
philpem@0 2721
philpem@0 2722 data = m68ki_read_32(ea);
philpem@0 2723 data = MASK_OUT_ABOVE_32(data<<local_offset);
philpem@0 2724
philpem@0 2725 if((local_offset+width) > 32)
philpem@0 2726 data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
philpem@0 2727
philpem@0 2728 FLAG_N = NFLAG_32(data);
philpem@0 2729 data >>= (32 - width);
philpem@0 2730
philpem@0 2731 FLAG_Z = data;
philpem@0 2732 FLAG_V = VFLAG_CLEAR;
philpem@0 2733 FLAG_C = CFLAG_CLEAR;
philpem@0 2734
philpem@0 2735 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
philpem@0 2736 offset++;
philpem@0 2737
philpem@0 2738 REG_D[(word2>>12)&7] = offset;
philpem@0 2739
philpem@0 2740 return;
philpem@0 2741 }
philpem@0 2742 m68ki_exception_illegal();
philpem@0 2743 }
philpem@0 2744
philpem@0 2745
philpem@0 2746 M68KMAKE_OP(bfins, 32, ., d)
philpem@0 2747 {
philpem@0 2748 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 2749 {
philpem@0 2750 uint word2 = OPER_I_16();
philpem@0 2751 uint offset = (word2>>6)&31;
philpem@0 2752 uint width = word2;
philpem@0 2753 uint* data = &DY;
philpem@0 2754 uint64 mask;
philpem@0 2755 uint64 insert = REG_D[(word2>>12)&7];
philpem@0 2756
philpem@0 2757
philpem@0 2758 if(BIT_B(word2))
philpem@0 2759 offset = REG_D[offset&7];
philpem@0 2760 if(BIT_5(word2))
philpem@0 2761 width = REG_D[width&7];
philpem@0 2762
philpem@0 2763
philpem@0 2764 offset &= 31;
philpem@0 2765 width = ((width-1) & 31) + 1;
philpem@0 2766
philpem@0 2767
philpem@0 2768 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
philpem@0 2769 mask = ROR_32(mask, offset);
philpem@0 2770
philpem@0 2771 insert = MASK_OUT_ABOVE_32(insert << (32 - width));
philpem@0 2772 FLAG_N = NFLAG_32(insert);
philpem@0 2773 FLAG_Z = insert;
philpem@0 2774 insert = ROR_32(insert, offset);
philpem@0 2775
philpem@0 2776 FLAG_V = VFLAG_CLEAR;
philpem@0 2777 FLAG_C = CFLAG_CLEAR;
philpem@0 2778
philpem@0 2779 *data &= ~mask;
philpem@0 2780 *data |= insert;
philpem@0 2781
philpem@0 2782 return;
philpem@0 2783 }
philpem@0 2784 m68ki_exception_illegal();
philpem@0 2785 }
philpem@0 2786
philpem@0 2787
philpem@0 2788 M68KMAKE_OP(bfins, 32, ., .)
philpem@0 2789 {
philpem@0 2790 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 2791 {
philpem@0 2792 uint word2 = OPER_I_16();
philpem@0 2793 sint offset = (word2>>6)&31;
philpem@0 2794 uint width = word2;
philpem@0 2795 uint insert_base = REG_D[(word2>>12)&7];
philpem@0 2796 uint insert_long;
philpem@0 2797 uint insert_byte;
philpem@0 2798 uint mask_base;
philpem@0 2799 uint data_long;
philpem@0 2800 uint mask_long;
philpem@0 2801 uint data_byte = 0;
philpem@0 2802 uint mask_byte = 0;
philpem@0 2803 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 2804
philpem@0 2805
philpem@0 2806 if(BIT_B(word2))
philpem@0 2807 offset = MAKE_INT_32(REG_D[offset&7]);
philpem@0 2808 if(BIT_5(word2))
philpem@0 2809 width = REG_D[width&7];
philpem@0 2810
philpem@0 2811 /* Offset is signed so we have to use ugly math =( */
philpem@0 2812 ea += offset / 8;
philpem@0 2813 offset %= 8;
philpem@0 2814 if(offset < 0)
philpem@0 2815 {
philpem@0 2816 offset += 8;
philpem@0 2817 ea--;
philpem@0 2818 }
philpem@0 2819 width = ((width-1) & 31) + 1;
philpem@0 2820
philpem@0 2821 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
philpem@0 2822 mask_long = mask_base >> offset;
philpem@0 2823
philpem@0 2824 insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
philpem@0 2825 FLAG_N = NFLAG_32(insert_base);
philpem@0 2826 FLAG_Z = insert_base;
philpem@0 2827 insert_long = insert_base >> offset;
philpem@0 2828
philpem@0 2829 data_long = m68ki_read_32(ea);
philpem@0 2830 FLAG_V = VFLAG_CLEAR;
philpem@0 2831 FLAG_C = CFLAG_CLEAR;
philpem@0 2832
philpem@0 2833 m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
philpem@0 2834
philpem@0 2835 if((width + offset) > 32)
philpem@0 2836 {
philpem@0 2837 mask_byte = MASK_OUT_ABOVE_8(mask_base);
philpem@0 2838 insert_byte = MASK_OUT_ABOVE_8(insert_base);
philpem@0 2839 data_byte = m68ki_read_8(ea+4);
philpem@0 2840 FLAG_Z |= (data_byte & mask_byte);
philpem@0 2841 m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
philpem@0 2842 }
philpem@0 2843 return;
philpem@0 2844 }
philpem@0 2845 m68ki_exception_illegal();
philpem@0 2846 }
philpem@0 2847
philpem@0 2848
philpem@0 2849 M68KMAKE_OP(bfset, 32, ., d)
philpem@0 2850 {
philpem@0 2851 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 2852 {
philpem@0 2853 uint word2 = OPER_I_16();
philpem@0 2854 uint offset = (word2>>6)&31;
philpem@0 2855 uint width = word2;
philpem@0 2856 uint* data = &DY;
philpem@0 2857 uint64 mask;
philpem@0 2858
philpem@0 2859
philpem@0 2860 if(BIT_B(word2))
philpem@0 2861 offset = REG_D[offset&7];
philpem@0 2862 if(BIT_5(word2))
philpem@0 2863 width = REG_D[width&7];
philpem@0 2864
philpem@0 2865
philpem@0 2866 offset &= 31;
philpem@0 2867 width = ((width-1) & 31) + 1;
philpem@0 2868
philpem@0 2869
philpem@0 2870 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
philpem@0 2871 mask = ROR_32(mask, offset);
philpem@0 2872
philpem@0 2873 FLAG_N = NFLAG_32(*data<<offset);
philpem@0 2874 FLAG_Z = *data & mask;
philpem@0 2875 FLAG_V = VFLAG_CLEAR;
philpem@0 2876 FLAG_C = CFLAG_CLEAR;
philpem@0 2877
philpem@0 2878 *data |= mask;
philpem@0 2879
philpem@0 2880 return;
philpem@0 2881 }
philpem@0 2882 m68ki_exception_illegal();
philpem@0 2883 }
philpem@0 2884
philpem@0 2885
philpem@0 2886 M68KMAKE_OP(bfset, 32, ., .)
philpem@0 2887 {
philpem@0 2888 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 2889 {
philpem@0 2890 uint word2 = OPER_I_16();
philpem@0 2891 sint offset = (word2>>6)&31;
philpem@0 2892 uint width = word2;
philpem@0 2893 uint mask_base;
philpem@0 2894 uint data_long;
philpem@0 2895 uint mask_long;
philpem@0 2896 uint data_byte = 0;
philpem@0 2897 uint mask_byte = 0;
philpem@0 2898 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 2899
philpem@0 2900
philpem@0 2901 if(BIT_B(word2))
philpem@0 2902 offset = MAKE_INT_32(REG_D[offset&7]);
philpem@0 2903 if(BIT_5(word2))
philpem@0 2904 width = REG_D[width&7];
philpem@0 2905
philpem@0 2906 /* Offset is signed so we have to use ugly math =( */
philpem@0 2907 ea += offset / 8;
philpem@0 2908 offset %= 8;
philpem@0 2909 if(offset < 0)
philpem@0 2910 {
philpem@0 2911 offset += 8;
philpem@0 2912 ea--;
philpem@0 2913 }
philpem@0 2914 width = ((width-1) & 31) + 1;
philpem@0 2915
philpem@0 2916
philpem@0 2917 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
philpem@0 2918 mask_long = mask_base >> offset;
philpem@0 2919
philpem@0 2920 data_long = m68ki_read_32(ea);
philpem@0 2921 FLAG_N = NFLAG_32(data_long << offset);
philpem@0 2922 FLAG_Z = data_long & mask_long;
philpem@0 2923 FLAG_V = VFLAG_CLEAR;
philpem@0 2924 FLAG_C = CFLAG_CLEAR;
philpem@0 2925
philpem@0 2926 m68ki_write_32(ea, data_long | mask_long);
philpem@0 2927
philpem@0 2928 if((width + offset) > 32)
philpem@0 2929 {
philpem@0 2930 mask_byte = MASK_OUT_ABOVE_8(mask_base);
philpem@0 2931 data_byte = m68ki_read_8(ea+4);
philpem@0 2932 FLAG_Z |= (data_byte & mask_byte);
philpem@0 2933 m68ki_write_8(ea+4, data_byte | mask_byte);
philpem@0 2934 }
philpem@0 2935 return;
philpem@0 2936 }
philpem@0 2937 m68ki_exception_illegal();
philpem@0 2938 }
philpem@0 2939
philpem@0 2940
philpem@0 2941 M68KMAKE_OP(bftst, 32, ., d)
philpem@0 2942 {
philpem@0 2943 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 2944 {
philpem@0 2945 uint word2 = OPER_I_16();
philpem@0 2946 uint offset = (word2>>6)&31;
philpem@0 2947 uint width = word2;
philpem@0 2948 uint* data = &DY;
philpem@0 2949 uint64 mask;
philpem@0 2950
philpem@0 2951
philpem@0 2952 if(BIT_B(word2))
philpem@0 2953 offset = REG_D[offset&7];
philpem@0 2954 if(BIT_5(word2))
philpem@0 2955 width = REG_D[width&7];
philpem@0 2956
philpem@0 2957
philpem@0 2958 offset &= 31;
philpem@0 2959 width = ((width-1) & 31) + 1;
philpem@0 2960
philpem@0 2961
philpem@0 2962 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
philpem@0 2963 mask = ROR_32(mask, offset);
philpem@0 2964
philpem@0 2965 FLAG_N = NFLAG_32(*data<<offset);
philpem@0 2966 FLAG_Z = *data & mask;
philpem@0 2967 FLAG_V = VFLAG_CLEAR;
philpem@0 2968 FLAG_C = CFLAG_CLEAR;
philpem@0 2969
philpem@0 2970 return;
philpem@0 2971 }
philpem@0 2972 m68ki_exception_illegal();
philpem@0 2973 }
philpem@0 2974
philpem@0 2975
philpem@0 2976 M68KMAKE_OP(bftst, 32, ., .)
philpem@0 2977 {
philpem@0 2978 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 2979 {
philpem@0 2980 uint word2 = OPER_I_16();
philpem@0 2981 sint offset = (word2>>6)&31;
philpem@0 2982 uint width = word2;
philpem@0 2983 uint mask_base;
philpem@0 2984 uint data_long;
philpem@0 2985 uint mask_long;
philpem@0 2986 uint data_byte = 0;
philpem@0 2987 uint mask_byte = 0;
philpem@0 2988 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 2989
philpem@0 2990 if(BIT_B(word2))
philpem@0 2991 offset = MAKE_INT_32(REG_D[offset&7]);
philpem@0 2992 if(BIT_5(word2))
philpem@0 2993 width = REG_D[width&7];
philpem@0 2994
philpem@0 2995 /* Offset is signed so we have to use ugly math =( */
philpem@0 2996 ea += offset / 8;
philpem@0 2997 offset %= 8;
philpem@0 2998 if(offset < 0)
philpem@0 2999 {
philpem@0 3000 offset += 8;
philpem@0 3001 ea--;
philpem@0 3002 }
philpem@0 3003 width = ((width-1) & 31) + 1;
philpem@0 3004
philpem@0 3005
philpem@0 3006 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
philpem@0 3007 mask_long = mask_base >> offset;
philpem@0 3008
philpem@0 3009 data_long = m68ki_read_32(ea);
philpem@0 3010 FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
philpem@0 3011 FLAG_Z = data_long & mask_long;
philpem@0 3012 FLAG_V = VFLAG_CLEAR;
philpem@0 3013 FLAG_C = CFLAG_CLEAR;
philpem@0 3014
philpem@0 3015 if((width + offset) > 32)
philpem@0 3016 {
philpem@0 3017 mask_byte = MASK_OUT_ABOVE_8(mask_base);
philpem@0 3018 data_byte = m68ki_read_8(ea+4);
philpem@0 3019 FLAG_Z |= (data_byte & mask_byte);
philpem@0 3020 }
philpem@0 3021 return;
philpem@0 3022 }
philpem@0 3023 m68ki_exception_illegal();
philpem@0 3024 }
philpem@0 3025
philpem@0 3026
philpem@0 3027 M68KMAKE_OP(bkpt, 0, ., .)
philpem@0 3028 {
philpem@0 3029 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
philpem@0 3030 {
philpem@0 3031 m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */
philpem@0 3032 }
philpem@0 3033 m68ki_exception_illegal();
philpem@0 3034 }
philpem@0 3035
philpem@0 3036
philpem@0 3037 M68KMAKE_OP(bra, 8, ., .)
philpem@0 3038 {
philpem@0 3039 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
philpem@0 3040 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
philpem@0 3041 if(REG_PC == REG_PPC)
philpem@0 3042 USE_ALL_CYCLES();
philpem@0 3043 }
philpem@0 3044
philpem@0 3045
philpem@0 3046 M68KMAKE_OP(bra, 16, ., .)
philpem@0 3047 {
philpem@0 3048 uint offset = OPER_I_16();
philpem@0 3049 REG_PC -= 2;
philpem@0 3050 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
philpem@0 3051 m68ki_branch_16(offset);
philpem@0 3052 if(REG_PC == REG_PPC)
philpem@0 3053 USE_ALL_CYCLES();
philpem@0 3054 }
philpem@0 3055
philpem@0 3056
philpem@0 3057 M68KMAKE_OP(bra, 32, ., .)
philpem@0 3058 {
philpem@0 3059 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 3060 {
philpem@0 3061 uint offset = OPER_I_32();
philpem@0 3062 REG_PC -= 4;
philpem@0 3063 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
philpem@0 3064 m68ki_branch_32(offset);
philpem@0 3065 if(REG_PC == REG_PPC)
philpem@0 3066 USE_ALL_CYCLES();
philpem@0 3067 return;
philpem@0 3068 }
philpem@0 3069 m68ki_exception_illegal();
philpem@0 3070 }
philpem@0 3071
philpem@0 3072
philpem@0 3073 M68KMAKE_OP(bset, 32, r, d)
philpem@0 3074 {
philpem@0 3075 uint* r_dst = &DY;
philpem@0 3076 uint mask = 1 << (DX & 0x1f);
philpem@0 3077
philpem@0 3078 FLAG_Z = *r_dst & mask;
philpem@0 3079 *r_dst |= mask;
philpem@0 3080 }
philpem@0 3081
philpem@0 3082
philpem@0 3083 M68KMAKE_OP(bset, 8, r, .)
philpem@0 3084 {
philpem@0 3085 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 3086 uint src = m68ki_read_8(ea);
philpem@0 3087 uint mask = 1 << (DX & 7);
philpem@0 3088
philpem@0 3089 FLAG_Z = src & mask;
philpem@0 3090 m68ki_write_8(ea, src | mask);
philpem@0 3091 }
philpem@0 3092
philpem@0 3093
philpem@0 3094 M68KMAKE_OP(bset, 32, s, d)
philpem@0 3095 {
philpem@0 3096 uint* r_dst = &DY;
philpem@0 3097 uint mask = 1 << (OPER_I_8() & 0x1f);
philpem@0 3098
philpem@0 3099 FLAG_Z = *r_dst & mask;
philpem@0 3100 *r_dst |= mask;
philpem@0 3101 }
philpem@0 3102
philpem@0 3103
philpem@0 3104 M68KMAKE_OP(bset, 8, s, .)
philpem@0 3105 {
philpem@0 3106 uint mask = 1 << (OPER_I_8() & 7);
philpem@0 3107 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 3108 uint src = m68ki_read_8(ea);
philpem@0 3109
philpem@0 3110 FLAG_Z = src & mask;
philpem@0 3111 m68ki_write_8(ea, src | mask);
philpem@0 3112 }
philpem@0 3113
philpem@0 3114
philpem@0 3115 M68KMAKE_OP(bsr, 8, ., .)
philpem@0 3116 {
philpem@0 3117 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
philpem@0 3118 m68ki_push_32(REG_PC);
philpem@0 3119 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
philpem@0 3120 }
philpem@0 3121
philpem@0 3122
philpem@0 3123 M68KMAKE_OP(bsr, 16, ., .)
philpem@0 3124 {
philpem@0 3125 uint offset = OPER_I_16();
philpem@0 3126 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
philpem@0 3127 m68ki_push_32(REG_PC);
philpem@0 3128 REG_PC -= 2;
philpem@0 3129 m68ki_branch_16(offset);
philpem@0 3130 }
philpem@0 3131
philpem@0 3132
philpem@0 3133 M68KMAKE_OP(bsr, 32, ., .)
philpem@0 3134 {
philpem@0 3135 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 3136 {
philpem@0 3137 uint offset = OPER_I_32();
philpem@0 3138 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
philpem@0 3139 m68ki_push_32(REG_PC);
philpem@0 3140 REG_PC -= 4;
philpem@0 3141 m68ki_branch_32(offset);
philpem@0 3142 return;
philpem@0 3143 }
philpem@0 3144 m68ki_exception_illegal();
philpem@0 3145 }
philpem@0 3146
philpem@0 3147
philpem@0 3148 M68KMAKE_OP(btst, 32, r, d)
philpem@0 3149 {
philpem@0 3150 FLAG_Z = DY & (1 << (DX & 0x1f));
philpem@0 3151 }
philpem@0 3152
philpem@0 3153
philpem@0 3154 M68KMAKE_OP(btst, 8, r, .)
philpem@0 3155 {
philpem@0 3156 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));
philpem@0 3157 }
philpem@0 3158
philpem@0 3159
philpem@0 3160 M68KMAKE_OP(btst, 32, s, d)
philpem@0 3161 {
philpem@0 3162 FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
philpem@0 3163 }
philpem@0 3164
philpem@0 3165
philpem@0 3166 M68KMAKE_OP(btst, 8, s, .)
philpem@0 3167 {
philpem@0 3168 uint bit = OPER_I_8() & 7;
philpem@0 3169
philpem@0 3170 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);
philpem@0 3171 }
philpem@0 3172
philpem@0 3173
philpem@0 3174 M68KMAKE_OP(callm, 32, ., .)
philpem@0 3175 {
philpem@0 3176 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
philpem@0 3177 {
philpem@0 3178 uint ea = M68KMAKE_GET_EA_AY_32;
philpem@0 3179
philpem@0 3180 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
philpem@0 3181 REG_PC += 2;
philpem@0 3182 (void)ea; /* just to avoid an 'unused variable' warning */
philpem@0 3183 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
philpem@0 3184 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
philpem@0 3185 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
philpem@0 3186 return;
philpem@0 3187 }
philpem@0 3188 m68ki_exception_illegal();
philpem@0 3189 }
philpem@0 3190
philpem@0 3191
philpem@0 3192 M68KMAKE_OP(cas, 8, ., .)
philpem@0 3193 {
philpem@0 3194 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 3195 {
philpem@0 3196 uint word2 = OPER_I_16();
philpem@0 3197 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 3198 uint dest = m68ki_read_8(ea);
philpem@0 3199 uint* compare = &REG_D[word2 & 7];
philpem@0 3200 uint res = dest - MASK_OUT_ABOVE_8(*compare);
philpem@0 3201
philpem@0 3202 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
philpem@0 3203 FLAG_N = NFLAG_8(res);
philpem@0 3204 FLAG_Z = MASK_OUT_ABOVE_8(res);
philpem@0 3205 FLAG_V = VFLAG_SUB_8(*compare, dest, res);
philpem@0 3206 FLAG_C = CFLAG_8(res);
philpem@0 3207
philpem@0 3208 if(COND_NE())
philpem@0 3209 *compare = MASK_OUT_BELOW_8(*compare) | dest;
philpem@0 3210 else
philpem@0 3211 {
philpem@0 3212 USE_CYCLES(3);
philpem@0 3213 m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
philpem@0 3214 }
philpem@0 3215 return;
philpem@0 3216 }
philpem@0 3217 m68ki_exception_illegal();
philpem@0 3218 }
philpem@0 3219
philpem@0 3220
philpem@0 3221 M68KMAKE_OP(cas, 16, ., .)
philpem@0 3222 {
philpem@0 3223 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 3224 {
philpem@0 3225 uint word2 = OPER_I_16();
philpem@0 3226 uint ea = M68KMAKE_GET_EA_AY_16;
philpem@0 3227 uint dest = m68ki_read_16(ea);
philpem@0 3228 uint* compare = &REG_D[word2 & 7];
philpem@0 3229 uint res = dest - MASK_OUT_ABOVE_16(*compare);
philpem@0 3230
philpem@0 3231 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
philpem@0 3232 FLAG_N = NFLAG_16(res);
philpem@0 3233 FLAG_Z = MASK_OUT_ABOVE_16(res);
philpem@0 3234 FLAG_V = VFLAG_SUB_16(*compare, dest, res);
philpem@0 3235 FLAG_C = CFLAG_16(res);
philpem@0 3236
philpem@0 3237 if(COND_NE())
philpem@0 3238 *compare = MASK_OUT_BELOW_16(*compare) | dest;
philpem@0 3239 else
philpem@0 3240 {
philpem@0 3241 USE_CYCLES(3);
philpem@0 3242 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
philpem@0 3243 }
philpem@0 3244 return;
philpem@0 3245 }
philpem@0 3246 m68ki_exception_illegal();
philpem@0 3247 }
philpem@0 3248
philpem@0 3249
philpem@0 3250 M68KMAKE_OP(cas, 32, ., .)
philpem@0 3251 {
philpem@0 3252 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 3253 {
philpem@0 3254 uint word2 = OPER_I_16();
philpem@0 3255 uint ea = M68KMAKE_GET_EA_AY_32;
philpem@0 3256 uint dest = m68ki_read_32(ea);
philpem@0 3257 uint* compare = &REG_D[word2 & 7];
philpem@0 3258 uint res = dest - *compare;
philpem@0 3259
philpem@0 3260 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
philpem@0 3261 FLAG_N = NFLAG_32(res);
philpem@0 3262 FLAG_Z = MASK_OUT_ABOVE_32(res);
philpem@0 3263 FLAG_V = VFLAG_SUB_32(*compare, dest, res);
philpem@0 3264 FLAG_C = CFLAG_SUB_32(*compare, dest, res);
philpem@0 3265
philpem@0 3266 if(COND_NE())
philpem@0 3267 *compare = dest;
philpem@0 3268 else
philpem@0 3269 {
philpem@0 3270 USE_CYCLES(3);
philpem@0 3271 m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
philpem@0 3272 }
philpem@0 3273 return;
philpem@0 3274 }
philpem@0 3275 m68ki_exception_illegal();
philpem@0 3276 }
philpem@0 3277
philpem@0 3278
philpem@0 3279 M68KMAKE_OP(cas2, 16, ., .)
philpem@0 3280 {
philpem@0 3281 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 3282 {
philpem@0 3283 uint word2 = OPER_I_32();
philpem@0 3284 uint* compare1 = &REG_D[(word2 >> 16) & 7];
philpem@0 3285 uint ea1 = REG_DA[(word2 >> 28) & 15];
philpem@0 3286 uint dest1 = m68ki_read_16(ea1);
philpem@0 3287 uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);
philpem@0 3288 uint* compare2 = &REG_D[word2 & 7];
philpem@0 3289 uint ea2 = REG_DA[(word2 >> 12) & 15];
philpem@0 3290 uint dest2 = m68ki_read_16(ea2);
philpem@0 3291 uint res2;
philpem@0 3292
philpem@0 3293 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
philpem@0 3294 FLAG_N = NFLAG_16(res1);
philpem@0 3295 FLAG_Z = MASK_OUT_ABOVE_16(res1);
philpem@0 3296 FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);
philpem@0 3297 FLAG_C = CFLAG_16(res1);
philpem@0 3298
philpem@0 3299 if(COND_EQ())
philpem@0 3300 {
philpem@0 3301 res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);
philpem@0 3302
philpem@0 3303 FLAG_N = NFLAG_16(res2);
philpem@0 3304 FLAG_Z = MASK_OUT_ABOVE_16(res2);
philpem@0 3305 FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);
philpem@0 3306 FLAG_C = CFLAG_16(res2);
philpem@0 3307
philpem@0 3308 if(COND_EQ())
philpem@0 3309 {
philpem@0 3310 USE_CYCLES(3);
philpem@0 3311 m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);
philpem@0 3312 m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);
philpem@0 3313 return;
philpem@0 3314 }
philpem@0 3315 }
philpem@0 3316 *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;
philpem@0 3317 *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;
philpem@0 3318 return;
philpem@0 3319 }
philpem@0 3320 m68ki_exception_illegal();
philpem@0 3321 }
philpem@0 3322
philpem@0 3323
philpem@0 3324 M68KMAKE_OP(cas2, 32, ., .)
philpem@0 3325 {
philpem@0 3326 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 3327 {
philpem@0 3328 uint word2 = OPER_I_32();
philpem@0 3329 uint* compare1 = &REG_D[(word2 >> 16) & 7];
philpem@0 3330 uint ea1 = REG_DA[(word2 >> 28) & 15];
philpem@0 3331 uint dest1 = m68ki_read_32(ea1);
philpem@0 3332 uint res1 = dest1 - *compare1;
philpem@0 3333 uint* compare2 = &REG_D[word2 & 7];
philpem@0 3334 uint ea2 = REG_DA[(word2 >> 12) & 15];
philpem@0 3335 uint dest2 = m68ki_read_32(ea2);
philpem@0 3336 uint res2;
philpem@0 3337
philpem@0 3338 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
philpem@0 3339 FLAG_N = NFLAG_32(res1);
philpem@0 3340 FLAG_Z = MASK_OUT_ABOVE_32(res1);
philpem@0 3341 FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);
philpem@0 3342 FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);
philpem@0 3343
philpem@0 3344 if(COND_EQ())
philpem@0 3345 {
philpem@0 3346 res2 = dest2 - *compare2;
philpem@0 3347
philpem@0 3348 FLAG_N = NFLAG_32(res2);
philpem@0 3349 FLAG_Z = MASK_OUT_ABOVE_32(res2);
philpem@0 3350 FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);
philpem@0 3351 FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);
philpem@0 3352
philpem@0 3353 if(COND_EQ())
philpem@0 3354 {
philpem@0 3355 USE_CYCLES(3);
philpem@0 3356 m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);
philpem@0 3357 m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);
philpem@0 3358 return;
philpem@0 3359 }
philpem@0 3360 }
philpem@0 3361 *compare1 = dest1;
philpem@0 3362 *compare2 = dest2;
philpem@0 3363 return;
philpem@0 3364 }
philpem@0 3365 m68ki_exception_illegal();
philpem@0 3366 }
philpem@0 3367
philpem@0 3368
philpem@0 3369 M68KMAKE_OP(chk, 16, ., d)
philpem@0 3370 {
philpem@0 3371 sint src = MAKE_INT_16(DX);
philpem@0 3372 sint bound = MAKE_INT_16(DY);
philpem@0 3373
philpem@0 3374 if(src >= 0 && src <= bound)
philpem@0 3375 {
philpem@0 3376 return;
philpem@0 3377 }
philpem@0 3378 FLAG_N = (src < 0)<<7;
philpem@0 3379 m68ki_exception_trap(EXCEPTION_CHK);
philpem@0 3380 }
philpem@0 3381
philpem@0 3382
philpem@0 3383 M68KMAKE_OP(chk, 16, ., .)
philpem@0 3384 {
philpem@0 3385 sint src = MAKE_INT_16(DX);
philpem@0 3386 sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
philpem@0 3387
philpem@0 3388 if(src >= 0 && src <= bound)
philpem@0 3389 {
philpem@0 3390 return;
philpem@0 3391 }
philpem@0 3392 FLAG_N = (src < 0)<<7;
philpem@0 3393 m68ki_exception_trap(EXCEPTION_CHK);
philpem@0 3394 }
philpem@0 3395
philpem@0 3396
philpem@0 3397 M68KMAKE_OP(chk, 32, ., d)
philpem@0 3398 {
philpem@0 3399 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 3400 {
philpem@0 3401 sint src = MAKE_INT_32(DX);
philpem@0 3402 sint bound = MAKE_INT_32(DY);
philpem@0 3403
philpem@0 3404 if(src >= 0 && src <= bound)
philpem@0 3405 {
philpem@0 3406 return;
philpem@0 3407 }
philpem@0 3408 FLAG_N = (src < 0)<<7;
philpem@0 3409 m68ki_exception_trap(EXCEPTION_CHK);
philpem@0 3410 return;
philpem@0 3411 }
philpem@0 3412 m68ki_exception_illegal();
philpem@0 3413 }
philpem@0 3414
philpem@0 3415
philpem@0 3416 M68KMAKE_OP(chk, 32, ., .)
philpem@0 3417 {
philpem@0 3418 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 3419 {
philpem@0 3420 sint src = MAKE_INT_32(DX);
philpem@0 3421 sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);
philpem@0 3422
philpem@0 3423 if(src >= 0 && src <= bound)
philpem@0 3424 {
philpem@0 3425 return;
philpem@0 3426 }
philpem@0 3427 FLAG_N = (src < 0)<<7;
philpem@0 3428 m68ki_exception_trap(EXCEPTION_CHK);
philpem@0 3429 return;
philpem@0 3430 }
philpem@0 3431 m68ki_exception_illegal();
philpem@0 3432 }
philpem@0 3433
philpem@0 3434
philpem@0 3435 M68KMAKE_OP(chk2cmp2, 8, ., .)
philpem@0 3436 {
philpem@0 3437 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 3438 {
philpem@0 3439 uint word2 = OPER_I_16();
philpem@0 3440 uint compare = REG_DA[(word2 >> 12) & 15];
philpem@0 3441 uint ea = M68KMAKE_GET_EA_AY_8;
philpem@0 3442 uint lower_bound = m68ki_read_8(ea);
philpem@0 3443 uint upper_bound = m68ki_read_8(ea + 1);
philpem@0 3444
philpem@0 3445 if(!BIT_F(word2))
philpem@0 3446 compare = MAKE_INT_8(compare);
philpem@0 3447
philpem@0 3448 FLAG_C = compare - lower_bound;
philpem@0 3449 FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C);
philpem@0 3450 if(COND_CS())
philpem@0 3451 {
philpem@0 3452 if(BIT_B(word2))
philpem@0 3453 m68ki_exception_trap(EXCEPTION_CHK);
philpem@0 3454 return;
philpem@0 3455 }
philpem@0 3456
philpem@0 3457 FLAG_C = upper_bound - compare;
philpem@0 3458 FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C);
philpem@0 3459 if(COND_CS() && BIT_B(word2))
philpem@0 3460 m68ki_exception_trap(EXCEPTION_CHK);
philpem@0 3461
philpem@0 3462 return;
philpem@0 3463 }
philpem@0 3464 m68ki_exception_illegal();
philpem@0 3465 }
philpem@0 3466
philpem@0 3467
philpem@0 3468 M68KMAKE_OP(chk2cmp2, 16, ., .)
philpem@0 3469 {
philpem@0 3470 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 3471 {
philpem@0 3472 uint word2 = OPER_I_16();
philpem@0 3473 uint compare = REG_DA[(word2 >> 12) & 15];
philpem@0 3474 uint ea = M68KMAKE_GET_EA_AY_16;
philpem@0 3475 uint lower_bound = m68ki_read_16(ea);
philpem@0 3476 uint upper_bound = m68ki_read_16(ea + 1);
philpem@0 3477
philpem@0 3478 if(!BIT_F(word2))
philpem@0 3479 compare = MAKE_INT_16(compare);
philpem@0 3480
philpem@0 3481 FLAG_C = compare - lower_bound;
philpem@0 3482 FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C);
philpem@0 3483 FLAG_C = CFLAG_16(FLAG_C);
philpem@0 3484 if(COND_CS())
philpem@0 3485 {
philpem@0 3486 if(BIT_B(word2))
philpem@0 3487 m68ki_exception_trap(EXCEPTION_CHK);
philpem@0 3488 return;
philpem@0 3489 }
philpem@0 3490
philpem@0 3491 FLAG_C = upper_bound - compare;
philpem@0 3492 FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C);
philpem@0 3493 FLAG_C = CFLAG_16(FLAG_C);
philpem@0 3494 if(COND_CS() && BIT_B(word2))
philpem@0 3495 m68ki_exception_trap(EXCEPTION_CHK);
philpem@0 3496
philpem@0 3497 return;
philpem@0 3498 }
philpem@0 3499 m68ki_exception_illegal();
philpem@0 3500 }
philpem@0 3501
philpem@0 3502
philpem@0 3503 M68KMAKE_OP(chk2cmp2, 32, ., .)
philpem@0 3504 {
philpem@0 3505 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
philpem@0 3506 {
philpem@0 3507 uint word2 = OPER_I_16();
philpem@0 3508 uint compare = REG_DA[(word2 >> 12) & 15];
philpem@0 3509 uint ea = M68KMAKE_GET_EA_AY_32;
philpem@0 3510 uint lower_bound = m68ki_read_32(ea);
philpem@0 3511 uint upper_bound = m68ki_read_32(ea + 1);
philpem@0 3512
philpem@0 3513 FLAG_C = compare - lower_bound;
philpem@0 3514 FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C);
philpem@0 3515 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
philpem@0 3516 if(COND_CS())
philpem@0 3517 {
philpem@0 3518 if(BIT_B(word2))
philpem@0 3519 m68ki_exception_trap(EXCEPTION_CHK);
philpem@0 3520 return;
philpem@0 3521 }
philpem@0 3522
philpem@0 3523 FLAG_C = upper_bound - compare;
philpem@0 3524 FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C);
philpem@0 3525 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
philpem@0 3526 if(COND_CS() && BIT_B(word2))
philpem@0 3527 m68ki_exception_trap(EXCEPTION_CHK);
philpem@0 3528
philpem@0 3529 return;
philpem@0 3530 }
philpem@0 3531 m68ki_exception_illegal();
philpem@0 3532 }
philpem@0 3533
philpem@0 3534
philpem@0 3535 M68KMAKE_OP(clr, 8, ., d)
philpem@0 3536 {
philpem@0 3537 DY &= 0xffffff00;
philpem@0 3538
philpem@0 3539 FLAG_N = NFLAG_CLEAR;
philpem@0 3540 FLAG_V = VFLAG_CLEAR;
philpem@0 3541 FLAG_C = CFLAG_CLEAR;
philpem@0 3542 FLAG_Z = ZFLAG_SET;
philpem@0 3543 }
philpem@0 3544
philpem@0 3545
philpem@0 3546 M68KMAKE_OP(clr, 8, ., .)
philpem@0 3547 {
philpem@0 3548 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
philpem@0 3549
philpem@0 3550 FLAG_N = NFLAG_CLEAR;
philpem@0 3551 FLAG_V = VFLAG_CLEAR;
philpem@0 3552 FLAG_C = CFLAG_CLEAR;
philpem@0 3553 FLAG_Z = ZFLAG_SET;
philpem@0 3554 }
philpem@0 3555
philpem@0 3556
philpem@0 3557 M68KMAKE_OP(clr, 16, ., d)
philpem@0 3558 {
philpem@0 3559 DY &= 0xffff0000;
philpem@0 3560
philpem@0 3561 FLAG_N = NFLAG_CLEAR;
philpem@0 3562 FLAG_V = VFLAG_CLEAR;
philpem@0 3563 FLAG_C = CFLAG_CLEAR;
philpem@0 3564 FLAG_Z = ZFLAG_SET;
philpem@0 3565 }
philpem@0 3566
philpem@0 3567
philpem@0 3568 M68KMAKE_OP(clr, 16, ., .)
philpem@0 3569 {
philpem@0 3570 m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0);
philpem@0 3571
philpem@0 3572 FLAG_N = NFLAG_CLEAR;
philpem@0 3573 FLAG_V = VFLAG_CLEAR;
philpem@0 3574 FLAG_C = CFLAG_CLEAR;
philpem@0 3575 FLAG_Z = ZFLAG_SET;
philpem@0 3576 }
philpem@0 3577
philpem@0 3578
philpem@0 3579 M68KMAKE_OP(clr, 32, ., d)
philpem@0 3580 {
philpem@0 3581 DY = 0;
philpem@0 3582
philpem@0 3583 FLAG_N = NFLAG_CLEAR;
philpem@0 3584 FLAG_V = VFLAG_CLEAR;
philpem@0 3585 FLAG_C = CFLAG_CLEAR;
philpem@0 3586 FLAG_Z = ZFLAG_SET;
philpem@0 3587 }
philpem@0 3588
philpem@0 3589
philpem@0 3590 M68KMAKE_OP(clr, 32, ., .)
philpem@0 3591 {
philpem@0 3592 m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0);
philpem@0