src/main.c

Thu, 02 Dec 2010 19:30:46 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Thu, 02 Dec 2010 19:30:46 +0000
changeset 34
e8ebd433270a
parent 32
a44afcf2354c
child 35
391318413bb2
permissions
-rw-r--r--

rewrite memory access routines

philpem@0 1 #include <stdio.h>
philpem@7 2 #include <stdlib.h>
philpem@4 3 #include <stdint.h>
philpem@7 4 #include <stdbool.h>
philpem@7 5 #include <malloc.h>
philpem@7 6 #include <string.h>
philpem@18 7
philpem@20 8 #include "SDL.h"
philpem@20 9
philpem@4 10 #include "musashi/m68k.h"
philpem@7 11 #include "version.h"
philpem@18 12 #include "state.h"
philpem@7 13
philpem@7 14 void FAIL(char *err)
philpem@7 15 {
philpem@7 16 state_done();
philpem@7 17 fprintf(stderr, "ERROR: %s\nExiting...\n", err);
philpem@7 18 exit(EXIT_FAILURE);
philpem@7 19 }
philpem@7 20
philpem@26 21 /***********************************
philpem@26 22 * Array read/write utility macros
philpem@26 23 * "Don't Repeat Yourself" :)
philpem@26 24 ***********************************/
philpem@26 25
philpem@26 26 /// Array read, 32-bit
philpem@26 27 #define RD32(array, address, andmask) \
philpem@26 28 (((uint32_t)array[(address + 0) & (andmask)] << 24) | \
philpem@26 29 ((uint32_t)array[(address + 1) & (andmask)] << 16) | \
philpem@26 30 ((uint32_t)array[(address + 2) & (andmask)] << 8) | \
philpem@26 31 ((uint32_t)array[(address + 3) & (andmask)]))
philpem@26 32
philpem@26 33 /// Array read, 16-bit
philpem@26 34 #define RD16(array, address, andmask) \
philpem@26 35 (((uint32_t)array[(address + 0) & (andmask)] << 8) | \
philpem@26 36 ((uint32_t)array[(address + 1) & (andmask)]))
philpem@26 37
philpem@26 38 /// Array read, 8-bit
philpem@26 39 #define RD8(array, address, andmask) \
philpem@26 40 ((uint32_t)array[(address + 0) & (andmask)])
philpem@26 41
philpem@26 42 /// Array write, 32-bit
philpem@26 43 #define WR32(array, address, andmask, value) { \
philpem@26 44 array[(address + 0) & (andmask)] = (value >> 24) & 0xff; \
philpem@26 45 array[(address + 1) & (andmask)] = (value >> 16) & 0xff; \
philpem@26 46 array[(address + 2) & (andmask)] = (value >> 8) & 0xff; \
philpem@26 47 array[(address + 3) & (andmask)] = value & 0xff; \
philpem@26 48 }
philpem@26 49
philpem@26 50 /// Array write, 16-bit
philpem@26 51 #define WR16(array, address, andmask, value) { \
philpem@26 52 array[(address + 0) & (andmask)] = (value >> 8) & 0xff; \
philpem@26 53 array[(address + 1) & (andmask)] = value & 0xff; \
philpem@26 54 }
philpem@26 55
philpem@26 56 /// Array write, 8-bit
philpem@26 57 #define WR8(array, address, andmask, value) \
philpem@26 58 array[(address + 0) & (andmask)] = value & 0xff;
philpem@26 59
philpem@30 60 /******************
philpem@30 61 * Memory mapping
philpem@30 62 ******************/
philpem@30 63
philpem@30 64 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
philpem@30 65
philpem@30 66 uint32_t mapAddr(uint32_t addr, bool writing)
philpem@30 67 {
philpem@30 68 if (addr < 0x400000) {
philpem@30 69 // RAM access. Check against the Map RAM
philpem@30 70 // Start by getting the original page address
philpem@30 71 uint16_t page = (addr >> 12) & 0x3FF;
philpem@30 72
philpem@30 73 // Look it up in the map RAM and get the physical page address
philpem@30 74 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@30 75
philpem@30 76 // Update the Page Status bits
philpem@30 77 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
philpem@30 78 if (pagebits != 0) {
philpem@30 79 if (writing)
philpem@32 80 state.map[page*2] |= 0x60; // Page written to (dirty)
philpem@30 81 else
philpem@32 82 state.map[page*2] |= 0x40; // Page accessed but not written
philpem@30 83 }
philpem@30 84
philpem@30 85 // Return the address with the new physical page spliced in
philpem@30 86 return (new_page_addr << 12) + (addr & 0xFFF);
philpem@30 87 } else {
philpem@30 88 // I/O, VRAM or MapRAM space; no mapping is performed or required
philpem@30 89 // TODO: assert here?
philpem@30 90 return addr;
philpem@30 91 }
philpem@30 92 }
philpem@30 93
philpem@30 94 typedef enum {
philpem@30 95 MEM_ALLOWED = 0,
philpem@30 96 MEM_PAGEFAULT, // Page fault -- page not present
philpem@30 97 MEM_PAGE_NO_WE, // Page not write enabled
philpem@30 98 MEM_KERNEL, // User attempted to access kernel memory
philpem@30 99 MEM_UIE // User Nonmemory Location Access
philpem@30 100 } MEM_STATUS;
philpem@30 101
philpem@30 102 // check memory access permissions
philpem@30 103 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)
philpem@30 104 {
philpem@30 105 // Are we in Supervisor mode?
philpem@30 106 if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
philpem@30 107 // Yes. We can do anything we like.
philpem@30 108 return MEM_ALLOWED;
philpem@30 109
philpem@30 110 // If we're here, then we must be in User mode.
philpem@30 111 // Check that the user didn't access memory outside of the RAM area
philpem@30 112 if (addr >= 0x400000)
philpem@30 113 return MEM_UIE;
philpem@30 114
philpem@30 115 // This leaves us with Page Fault checking. Get the page bits for this page.
philpem@30 116 uint16_t page = (addr >> 12) & 0x3FF;
philpem@30 117 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
philpem@30 118
philpem@30 119 // Check page is present
philpem@30 120 if ((pagebits & 0x03) == 0)
philpem@30 121 return MEM_PAGEFAULT;
philpem@30 122
philpem@30 123 // User attempt to access the kernel
philpem@30 124 // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
philpem@30 125 if (((addr >> 19) & 0x0F) == 0)
philpem@30 126 return MEM_KERNEL;
philpem@30 127
philpem@30 128 // Check page is write enabled
philpem@30 129 if ((pagebits & 0x04) == 0)
philpem@30 130 return MEM_PAGE_NO_WE;
philpem@30 131
philpem@30 132 // Page access allowed.
philpem@30 133 return MEM_ALLOWED;
philpem@30 134 }
philpem@30 135
philpem@30 136 #undef MAPRAM
philpem@26 137
philpem@26 138 /********************************************************
philpem@26 139 * m68k memory read/write support functions for Musashi
philpem@26 140 ********************************************************/
philpem@26 141
philpem@32 142 /**
philpem@32 143 * @brief Check memory access permissions for a write operation.
philpem@32 144 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
philpem@32 145 * gcc throws warnings when you have a return-with-value in a void
philpem@32 146 * function, even if the return-with-value is completely unreachable.
philpem@32 147 * Similarly it doesn't like it if you have a return without a value
philpem@32 148 * in a non-void function, even if it's impossible to ever reach the
philpem@32 149 * return-with-no-value. UGH!
philpem@32 150 */
philpem@32 151 #define ACCESS_CHECK_WR() do { \
philpem@32 152 /* MEM_STATUS st; */ \
philpem@32 153 switch (checkMemoryAccess(address, true)) { \
philpem@32 154 case MEM_ALLOWED: \
philpem@32 155 /* Access allowed */ \
philpem@32 156 break; \
philpem@32 157 case MEM_PAGEFAULT: \
philpem@32 158 /* Page fault */ \
philpem@32 159 state.genstat = 0x8FFF; \
philpem@32 160 m68k_pulse_bus_error(); \
philpem@32 161 return; \
philpem@32 162 case MEM_UIE: \
philpem@32 163 /* User access to memory above 4MB */ \
philpem@32 164 state.genstat = 0x9EFF; \
philpem@32 165 m68k_pulse_bus_error(); \
philpem@32 166 return; \
philpem@32 167 case MEM_KERNEL: \
philpem@32 168 case MEM_PAGE_NO_WE: \
philpem@32 169 /* kernel access or page not write enabled */ \
philpem@32 170 /* TODO: which regs need setting? */ \
philpem@32 171 m68k_pulse_bus_error(); \
philpem@32 172 return; \
philpem@32 173 } \
philpem@32 174 } while (false)
philpem@32 175
philpem@32 176 /**
philpem@32 177 * @brief Check memory access permissions for a read operation.
philpem@32 178 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
philpem@32 179 * gcc throws warnings when you have a return-with-value in a void
philpem@32 180 * function, even if the return-with-value is completely unreachable.
philpem@32 181 * Similarly it doesn't like it if you have a return without a value
philpem@32 182 * in a non-void function, even if it's impossible to ever reach the
philpem@32 183 * return-with-no-value. UGH!
philpem@32 184 */
philpem@32 185 #define ACCESS_CHECK_RD() do { \
philpem@32 186 /* MEM_STATUS st; */ \
philpem@32 187 switch (checkMemoryAccess(address, false)) { \
philpem@32 188 case MEM_ALLOWED: \
philpem@32 189 /* Access allowed */ \
philpem@32 190 break; \
philpem@32 191 case MEM_PAGEFAULT: \
philpem@32 192 /* Page fault */ \
philpem@32 193 state.genstat = 0xCFFF; \
philpem@32 194 m68k_pulse_bus_error(); \
philpem@32 195 return 0xFFFFFFFF; \
philpem@32 196 case MEM_UIE: \
philpem@32 197 /* User access to memory above 4MB */ \
philpem@32 198 state.genstat = 0xDEFF; \
philpem@32 199 m68k_pulse_bus_error(); \
philpem@32 200 return 0xFFFFFFFF; \
philpem@32 201 case MEM_KERNEL: \
philpem@32 202 case MEM_PAGE_NO_WE: \
philpem@32 203 /* kernel access or page not write enabled */ \
philpem@32 204 /* TODO: which regs need setting? */ \
philpem@32 205 m68k_pulse_bus_error(); \
philpem@32 206 return 0xFFFFFFFF; \
philpem@32 207 } \
philpem@32 208 } while (false)
philpem@32 209
philpem@32 210 /**
philpem@32 211 * @brief Read M68K memory, 32-bit
philpem@32 212 */
philpem@4 213 uint32_t m68k_read_memory_32(uint32_t address)
philpem@4 214 {
philpem@9 215 uint32_t data = 0xFFFFFFFF;
philpem@9 216
philpem@7 217 // If ROMLMAP is set, force system to access ROM
philpem@7 218 if (!state.romlmap)
philpem@7 219 address |= 0x800000;
philpem@7 220
philpem@32 221 // Check access permissions
philpem@32 222 ACCESS_CHECK_RD();
philpem@32 223
philpem@9 224 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@7 225 // ROM access
philpem@26 226 data = RD32(state.rom, address, ROM_SIZE - 1);
philpem@26 227 } else if (address <= (state.ram_size - 1)) {
philpem@32 228 // RAM access
philpem@32 229 data = RD32(state.ram, mapAddr(address, false), state.ram_size - 1);
philpem@34 230 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@34 231 // I/O register space, zone A
philpem@29 232 printf("RD32 0x%08X ==> ??? %s\n", address, m68k_get_reg(NULL, M68K_REG_SR) & 0x2000 ? "[SV]" : "");
philpem@34 233 switch (address & 0x0F0000) {
philpem@34 234 case 0x000000: // Map RAM access
philpem@34 235 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
philpem@34 236 data = RD32(state.map, address, 0x7FF);
philpem@34 237 break;
philpem@34 238 case 0x010000: // General Status Register
philpem@34 239 data = ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
philpem@34 240 break;
philpem@34 241 case 0x020000: // Video RAM
philpem@34 242 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@34 243 data = RD32(state.vram, address, 0x7FFF);
philpem@34 244 break;
philpem@34 245 case 0x030000: // Bus Status Register 0
philpem@34 246 case 0x040000: // Bus Status Register 1
philpem@34 247 case 0x050000: // Phone status
philpem@34 248 case 0x060000: // DMA Count
philpem@34 249 case 0x070000: // Line Printer Status Register
philpem@34 250 case 0x080000: // Real Time Clock
philpem@34 251 case 0x090000: // Phone registers
philpem@34 252 switch (address & 0x0FF000) {
philpem@34 253 case 0x090000: // Handset relay
philpem@34 254 case 0x098000:
philpem@34 255 case 0x091000: // Line select 2
philpem@34 256 case 0x099000:
philpem@34 257 case 0x092000: // Hook relay 1
philpem@34 258 case 0x09A000:
philpem@34 259 case 0x093000: // Hook relay 2
philpem@34 260 case 0x09B000:
philpem@34 261 case 0x094000: // Line 1 hold
philpem@34 262 case 0x09C000:
philpem@34 263 case 0x095000: // Line 2 hold
philpem@34 264 case 0x09D000:
philpem@34 265 case 0x096000: // Line 1 A-lead
philpem@34 266 case 0x09E000:
philpem@34 267 case 0x097000: // Line 2 A-lead
philpem@34 268 case 0x09F000:
philpem@34 269 break;
philpem@34 270 }
philpem@34 271 break;
philpem@34 272 case 0x0A0000: // Miscellaneous Control Register
philpem@34 273 case 0x0B0000: // TM/DIALWR
philpem@34 274 case 0x0C0000: // CSR
philpem@34 275 case 0x0D0000: // DMA Address Register
philpem@34 276 case 0x0E0000: // Disk Control Register
philpem@34 277 case 0x0F0000: // Line Printer Data Register
philpem@34 278 break;
philpem@34 279 }
philpem@34 280 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@34 281 // I/O register space, zone B
philpem@34 282 printf("RD32 0x%08X ==> ??? %s\n", address, m68k_get_reg(NULL, M68K_REG_SR) & 0x2000 ? "[SV]" : "");
philpem@34 283 switch (address & 0xF00000) {
philpem@34 284 case 0xC00000: // Expansion slots
philpem@34 285 case 0xD00000:
philpem@34 286 switch (address & 0xFC0000) {
philpem@34 287 case 0xC00000: // Expansion slot 0
philpem@34 288 case 0xC40000: // Expansion slot 1
philpem@34 289 case 0xC80000: // Expansion slot 2
philpem@34 290 case 0xCC0000: // Expansion slot 3
philpem@34 291 case 0xD00000: // Expansion slot 4
philpem@34 292 case 0xD40000: // Expansion slot 5
philpem@34 293 case 0xD80000: // Expansion slot 6
philpem@34 294 case 0xDC0000: // Expansion slot 7
philpem@34 295 fprintf(stderr, "NOTE: RD32 from expansion card space, addr=0x%08X\n", address);
philpem@34 296 break;
philpem@34 297 }
philpem@34 298 break;
philpem@34 299 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@34 300 case 0xF00000:
philpem@34 301 switch (address & 0x070000) {
philpem@34 302 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@34 303 break;
philpem@34 304 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@34 305 break;
philpem@34 306 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@34 307 break;
philpem@34 308 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@34 309 break;
philpem@34 310 default:
philpem@34 311 fprintf(stderr, "NOTE: RD32 from undefined E/F-block address 0x%08X", address);
philpem@34 312 }
philpem@34 313 }
philpem@7 314 }
philpem@9 315 return data;
philpem@4 316 }
philpem@4 317
philpem@32 318 /**
philpem@32 319 * @brief Read M68K memory, 16-bit
philpem@32 320 */
philpem@4 321 uint32_t m68k_read_memory_16(uint32_t address)
philpem@4 322 {
philpem@9 323 uint16_t data = 0xFFFF;
philpem@9 324
philpem@9 325 // If ROMLMAP is set, force system to access ROM
philpem@9 326 if (!state.romlmap)
philpem@9 327 address |= 0x800000;
philpem@9 328
philpem@32 329 // Check access permissions
philpem@32 330 ACCESS_CHECK_RD();
philpem@32 331
philpem@10 332 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@10 333 // ROM access
philpem@26 334 data = RD16(state.rom, address, ROM_SIZE - 1);
philpem@26 335 } else if (address <= (state.ram_size - 1)) {
philpem@32 336 // RAM access
philpem@32 337 data = RD16(state.ram, mapAddr(address, false), state.ram_size - 1);
philpem@34 338 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@34 339 // I/O register space, zone A
philpem@29 340 printf("RD16 0x%08X ==> ??? %s\n", address, m68k_get_reg(NULL, M68K_REG_SR) & 0x2000 ? "[SV]" : "");
philpem@34 341 switch (address & 0x0F0000) {
philpem@34 342 case 0x000000: // Map RAM access
philpem@34 343 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
philpem@34 344 data = RD16(state.map, address, 0x7FF);
philpem@34 345 break;
philpem@34 346 case 0x010000: // General Status Register
philpem@34 347 data = state.genstat;
philpem@34 348 break;
philpem@34 349 case 0x020000: // Video RAM
philpem@34 350 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@34 351 data = RD16(state.vram, address, 0x7FFF);
philpem@34 352 break;
philpem@34 353 case 0x030000: // Bus Status Register 0
philpem@34 354 case 0x040000: // Bus Status Register 1
philpem@34 355 case 0x050000: // Phone status
philpem@34 356 case 0x060000: // DMA Count
philpem@34 357 case 0x070000: // Line Printer Status Register
philpem@34 358 case 0x080000: // Real Time Clock
philpem@34 359 case 0x090000: // Phone registers
philpem@34 360 switch (address & 0x0FF000) {
philpem@34 361 case 0x090000: // Handset relay
philpem@34 362 case 0x098000:
philpem@34 363 case 0x091000: // Line select 2
philpem@34 364 case 0x099000:
philpem@34 365 case 0x092000: // Hook relay 1
philpem@34 366 case 0x09A000:
philpem@34 367 case 0x093000: // Hook relay 2
philpem@34 368 case 0x09B000:
philpem@34 369 case 0x094000: // Line 1 hold
philpem@34 370 case 0x09C000:
philpem@34 371 case 0x095000: // Line 2 hold
philpem@34 372 case 0x09D000:
philpem@34 373 case 0x096000: // Line 1 A-lead
philpem@34 374 case 0x09E000:
philpem@34 375 case 0x097000: // Line 2 A-lead
philpem@34 376 case 0x09F000:
philpem@34 377 break;
philpem@34 378 }
philpem@34 379 break;
philpem@34 380 case 0x0A0000: // Miscellaneous Control Register
philpem@34 381 case 0x0B0000: // TM/DIALWR
philpem@34 382 case 0x0C0000: // CSR
philpem@34 383 case 0x0D0000: // DMA Address Register
philpem@34 384 case 0x0E0000: // Disk Control Register
philpem@34 385 case 0x0F0000: // Line Printer Data Register
philpem@34 386 break;
philpem@34 387 }
philpem@34 388 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@34 389 // I/O register space, zone B
philpem@34 390 printf("RD16 0x%08X ==> ??? %s\n", address, m68k_get_reg(NULL, M68K_REG_SR) & 0x2000 ? "[SV]" : "");
philpem@34 391 switch (address & 0xF00000) {
philpem@34 392 case 0xC00000: // Expansion slots
philpem@34 393 case 0xD00000:
philpem@34 394 switch (address & 0xFC0000) {
philpem@34 395 case 0xC00000: // Expansion slot 0
philpem@34 396 case 0xC40000: // Expansion slot 1
philpem@34 397 case 0xC80000: // Expansion slot 2
philpem@34 398 case 0xCC0000: // Expansion slot 3
philpem@34 399 case 0xD00000: // Expansion slot 4
philpem@34 400 case 0xD40000: // Expansion slot 5
philpem@34 401 case 0xD80000: // Expansion slot 6
philpem@34 402 case 0xDC0000: // Expansion slot 7
philpem@34 403 fprintf(stderr, "NOTE: RD16 from expansion card space, addr=0x%08X\n", address);
philpem@34 404 break;
philpem@34 405 }
philpem@34 406 break;
philpem@34 407 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@34 408 case 0xF00000:
philpem@34 409 switch (address & 0x070000) {
philpem@34 410 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@34 411 break;
philpem@34 412 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@34 413 break;
philpem@34 414 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@34 415 break;
philpem@34 416 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@34 417 break;
philpem@34 418 default:
philpem@34 419 fprintf(stderr, "NOTE: RD16 to undefined E/F-block address 0x%08X", address);
philpem@34 420 }
philpem@34 421 }
philpem@10 422 }
philpem@9 423 return data;
philpem@4 424 }
philpem@4 425
philpem@32 426 /**
philpem@32 427 * @brief Read M68K memory, 8-bit
philpem@32 428 */
philpem@4 429 uint32_t m68k_read_memory_8(uint32_t address)
philpem@4 430 {
philpem@9 431 uint8_t data = 0xFF;
philpem@9 432
philpem@7 433 // If ROMLMAP is set, force system to access ROM
philpem@7 434 if (!state.romlmap)
philpem@7 435 address |= 0x800000;
philpem@7 436
philpem@32 437 // Check access permissions
philpem@32 438 ACCESS_CHECK_RD();
philpem@32 439
philpem@10 440 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@10 441 // ROM access
philpem@26 442 data = RD8(state.rom, address, ROM_SIZE - 1);
philpem@26 443 } else if (address <= (state.ram_size - 1)) {
philpem@32 444 // RAM access
philpem@32 445 data = RD8(state.ram, mapAddr(address, false), state.ram_size - 1);
philpem@34 446 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@34 447 // I/O register space, zone A
philpem@34 448 printf("RD8 0x%08X ==> ??? %s\n", address, m68k_get_reg(NULL, M68K_REG_SR) & 0x2000 ? "[SV]" : "");
philpem@34 449 switch (address & 0x0F0000) {
philpem@34 450 case 0x000000: // Map RAM access
philpem@34 451 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
philpem@34 452 data = RD8(state.map, address, 0x7FF);
philpem@34 453 break;
philpem@34 454 case 0x010000: // General Status Register
philpem@34 455 if ((address & 1) == 0)
philpem@34 456 data = (state.genstat >> 8) & 0xff;
philpem@34 457 else
philpem@34 458 data = (state.genstat) & 0xff;
philpem@34 459 break;
philpem@34 460 case 0x020000: // Video RAM
philpem@34 461 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@34 462 data = RD8(state.vram, address, 0x7FFF);
philpem@34 463 break;
philpem@34 464 case 0x030000: // Bus Status Register 0
philpem@34 465 case 0x040000: // Bus Status Register 1
philpem@34 466 case 0x050000: // Phone status
philpem@34 467 case 0x060000: // DMA Count
philpem@34 468 case 0x070000: // Line Printer Status Register
philpem@34 469 case 0x080000: // Real Time Clock
philpem@34 470 case 0x090000: // Phone registers
philpem@34 471 switch (address & 0x0FF000) {
philpem@34 472 case 0x090000: // Handset relay
philpem@34 473 case 0x098000:
philpem@34 474 case 0x091000: // Line select 2
philpem@34 475 case 0x099000:
philpem@34 476 case 0x092000: // Hook relay 1
philpem@34 477 case 0x09A000:
philpem@34 478 case 0x093000: // Hook relay 2
philpem@34 479 case 0x09B000:
philpem@34 480 case 0x094000: // Line 1 hold
philpem@34 481 case 0x09C000:
philpem@34 482 case 0x095000: // Line 2 hold
philpem@34 483 case 0x09D000:
philpem@34 484 case 0x096000: // Line 1 A-lead
philpem@34 485 case 0x09E000:
philpem@34 486 case 0x097000: // Line 2 A-lead
philpem@34 487 case 0x09F000:
philpem@34 488 break;
philpem@34 489 }
philpem@34 490 break;
philpem@34 491 case 0x0A0000: // Miscellaneous Control Register
philpem@34 492 case 0x0B0000: // TM/DIALWR
philpem@34 493 case 0x0C0000: // CSR
philpem@34 494 case 0x0D0000: // DMA Address Register
philpem@34 495 case 0x0E0000: // Disk Control Register
philpem@34 496 case 0x0F0000: // Line Printer Data Register
philpem@34 497 break;
philpem@34 498 }
philpem@34 499 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@34 500 // I/O register space, zone B
philpem@34 501 printf("RD32 0x%08X ==> ??? %s\n", address, m68k_get_reg(NULL, M68K_REG_SR) & 0x2000 ? "[SV]" : "");
philpem@34 502 switch (address & 0xF00000) {
philpem@34 503 case 0xC00000: // Expansion slots
philpem@34 504 case 0xD00000:
philpem@34 505 switch (address & 0xFC0000) {
philpem@34 506 case 0xC00000: // Expansion slot 0
philpem@34 507 case 0xC40000: // Expansion slot 1
philpem@34 508 case 0xC80000: // Expansion slot 2
philpem@34 509 case 0xCC0000: // Expansion slot 3
philpem@34 510 case 0xD00000: // Expansion slot 4
philpem@34 511 case 0xD40000: // Expansion slot 5
philpem@34 512 case 0xD80000: // Expansion slot 6
philpem@34 513 case 0xDC0000: // Expansion slot 7
philpem@34 514 fprintf(stderr, "NOTE: RD8 from expansion card address 0x%08X\n", address);
philpem@34 515 break;
philpem@34 516 }
philpem@34 517 break;
philpem@34 518 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@34 519 case 0xF00000:
philpem@34 520 switch (address & 0x070000) {
philpem@34 521 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@34 522 break;
philpem@34 523 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@34 524 break;
philpem@34 525 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@34 526 break;
philpem@34 527 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@34 528 break;
philpem@34 529 default:
philpem@34 530 fprintf(stderr, "NOTE: RD8 from undefined E/F-block address 0x%08X", address);
philpem@34 531 }
philpem@34 532 }
philpem@10 533 }
philpem@9 534 return data;
philpem@4 535 }
philpem@4 536
philpem@32 537 /**
philpem@32 538 * @brief Write M68K memory, 32-bit
philpem@32 539 */
philpem@4 540 void m68k_write_memory_32(uint32_t address, uint32_t value)
philpem@4 541 {
philpem@7 542 // If ROMLMAP is set, force system to access ROM
philpem@7 543 if (!state.romlmap)
philpem@7 544 address |= 0x800000;
philpem@7 545
philpem@32 546 // Check access permissions
philpem@32 547 ACCESS_CHECK_WR();
philpem@32 548
philpem@9 549 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@7 550 // ROM access
philpem@34 551 WR32(state.rom, address, ROM_SIZE - 1, value);
philpem@26 552 } else if (address <= (state.ram_size - 1)) {
philpem@32 553 // RAM access
philpem@34 554 WR32(state.ram, mapAddr(address, false), state.ram_size - 1, value);
philpem@34 555 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@34 556 // I/O register space, zone A
philpem@34 557 printf("WR32 0x%08X ==> ??? %s\n", address, m68k_get_reg(NULL, M68K_REG_SR) & 0x2000 ? "[SV]" : "");
philpem@34 558 switch (address & 0x0F0000) {
philpem@34 559 case 0x000000: // Map RAM access
philpem@34 560 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
philpem@34 561 WR32(state.map, address, 0x7FF, value);
philpem@34 562 break;
philpem@34 563 case 0x010000: // General Status Register
philpem@34 564 state.genstat = (value & 0xffff);
philpem@34 565 break;
philpem@34 566 case 0x020000: // Video RAM
philpem@34 567 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
philpem@34 568 WR32(state.vram, address, 0x7FFF, value);
philpem@34 569 break;
philpem@34 570 case 0x030000: // Bus Status Register 0
philpem@34 571 case 0x040000: // Bus Status Register 1
philpem@34 572 case 0x050000: // Phone status
philpem@34 573 case 0x060000: // DMA Count
philpem@34 574 case 0x070000: // Line Printer Status Register
philpem@34 575 case 0x080000: // Real Time Clock
philpem@34 576 case 0x090000: // Phone registers
philpem@34 577 switch (address & 0x0FF000) {
philpem@34 578 case 0x090000: // Handset relay
philpem@34 579 case 0x098000:
philpem@34 580 case 0x091000: // Line select 2
philpem@34 581 case 0x099000:
philpem@34 582 case 0x092000: // Hook relay 1
philpem@34 583 case 0x09A000:
philpem@34 584 case 0x093000: // Hook relay 2
philpem@34 585 case 0x09B000:
philpem@34 586 case 0x094000: // Line 1 hold
philpem@34 587 case 0x09C000:
philpem@34 588 case 0x095000: // Line 2 hold
philpem@34 589 case 0x09D000:
philpem@34 590 case 0x096000: // Line 1 A-lead
philpem@34 591 case 0x09E000:
philpem@34 592 case 0x097000: // Line 2 A-lead
philpem@34 593 case 0x09F000:
philpem@34 594 break;
philpem@34 595 }
philpem@34 596 break;
philpem@34 597 case 0x0A0000: // Miscellaneous Control Register
philpem@34 598 case 0x0B0000: // TM/DIALWR
philpem@34 599 case 0x0C0000: // CSR
philpem@34 600 case 0x0D0000: // DMA Address Register
philpem@34 601 case 0x0E0000: // Disk Control Register
philpem@34 602 case 0x0F0000: // Line Printer Data Register
philpem@34 603 break;
philpem@34 604 }
philpem@34 605 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@34 606 // I/O register space, zone B
philpem@34 607 printf("WR32 0x%08X ==> 0x%08X %s\n", address, value, m68k_get_reg(NULL, M68K_REG_SR) & 0x2000 ? "[SV]" : "");
philpem@34 608 switch (address & 0xF00000) {
philpem@34 609 case 0xC00000: // Expansion slots
philpem@34 610 case 0xD00000:
philpem@34 611 switch (address & 0xFC0000) {
philpem@34 612 case 0xC00000: // Expansion slot 0
philpem@34 613 case 0xC40000: // Expansion slot 1
philpem@34 614 case 0xC80000: // Expansion slot 2
philpem@34 615 case 0xCC0000: // Expansion slot 3
philpem@34 616 case 0xD00000: // Expansion slot 4
philpem@34 617 case 0xD40000: // Expansion slot 5
philpem@34 618 case 0xD80000: // Expansion slot 6
philpem@34 619 case 0xDC0000: // Expansion slot 7
philpem@34 620 fprintf(stderr, "NOTE: WR32 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
philpem@34 621 break;
philpem@34 622 }
philpem@34 623 break;
philpem@34 624 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@34 625 case 0xF00000:
philpem@34 626 switch (address & 0x070000) {
philpem@34 627 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@34 628 break;
philpem@34 629 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@34 630 break;
philpem@34 631 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@34 632 break;
philpem@34 633 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@34 634 break;
philpem@34 635 default:
philpem@34 636 fprintf(stderr, "NOTE: WR32 to undefined E/F-block space, addr=0x%08X, data=0x%08X\n", address, value);
philpem@34 637 }
philpem@9 638 }
philpem@7 639 }
philpem@4 640 }
philpem@4 641
philpem@32 642 /**
philpem@32 643 * @brief Write M68K memory, 16-bit
philpem@32 644 */
philpem@4 645 void m68k_write_memory_16(uint32_t address, uint32_t value)
philpem@4 646 {
philpem@7 647 // If ROMLMAP is set, force system to access ROM
philpem@7 648 if (!state.romlmap)
philpem@7 649 address |= 0x800000;
philpem@7 650
philpem@32 651 // Check access permissions
philpem@32 652 ACCESS_CHECK_WR();
philpem@32 653
philpem@9 654 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@7 655 // ROM access
philpem@34 656 WR16(state.rom, address, ROM_SIZE - 1, value);
philpem@26 657 } else if (address <= (state.ram_size - 1)) {
philpem@32 658 // RAM access
philpem@34 659 WR16(state.ram, mapAddr(address, false), state.ram_size - 1, value);
philpem@34 660 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@34 661 // I/O register space, zone A
philpem@34 662 printf("WR16 0x%08X ==> ??? %s\n", address, m68k_get_reg(NULL, M68K_REG_SR) & 0x2000 ? "[SV]" : "");
philpem@34 663 switch (address & 0x0F0000) {
philpem@34 664 case 0x000000: // Map RAM access
philpem@34 665 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@34 666 WR16(state.map, address, 0x7FF, value);
philpem@34 667 break;
philpem@34 668 case 0x010000: // General Status Register
philpem@34 669 state.genstat = (value & 0xffff);
philpem@34 670 break;
philpem@34 671 case 0x020000: // Video RAM
philpem@34 672 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@34 673 WR16(state.vram, address, 0x7FFF, value);
philpem@34 674 break;
philpem@34 675 case 0x030000: // Bus Status Register 0
philpem@34 676 case 0x040000: // Bus Status Register 1
philpem@34 677 case 0x050000: // Phone status
philpem@34 678 case 0x060000: // DMA Count
philpem@34 679 case 0x070000: // Line Printer Status Register
philpem@34 680 case 0x080000: // Real Time Clock
philpem@34 681 case 0x090000: // Phone registers
philpem@34 682 switch (address & 0x0FF000) {
philpem@34 683 case 0x090000: // Handset relay
philpem@34 684 case 0x098000:
philpem@34 685 case 0x091000: // Line select 2
philpem@34 686 case 0x099000:
philpem@34 687 case 0x092000: // Hook relay 1
philpem@34 688 case 0x09A000:
philpem@34 689 case 0x093000: // Hook relay 2
philpem@34 690 case 0x09B000:
philpem@34 691 case 0x094000: // Line 1 hold
philpem@34 692 case 0x09C000:
philpem@34 693 case 0x095000: // Line 2 hold
philpem@34 694 case 0x09D000:
philpem@34 695 case 0x096000: // Line 1 A-lead
philpem@34 696 case 0x09E000:
philpem@34 697 case 0x097000: // Line 2 A-lead
philpem@34 698 case 0x09F000:
philpem@34 699 break;
philpem@34 700 }
philpem@34 701 break;
philpem@34 702 case 0x0A0000: // Miscellaneous Control Register
philpem@34 703 case 0x0B0000: // TM/DIALWR
philpem@34 704 case 0x0C0000: // CSR
philpem@34 705 case 0x0D0000: // DMA Address Register
philpem@34 706 case 0x0E0000: // Disk Control Register
philpem@34 707 case 0x0F0000: // Line Printer Data Register
philpem@34 708 break;
philpem@9 709 }
philpem@34 710 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@34 711 // I/O register space, zone B
philpem@34 712 printf("WR16 0x%08X ==> 0x%04X %s\n", address, value, m68k_get_reg(NULL, M68K_REG_SR) & 0x2000 ? "[SV]" : "");
philpem@34 713 switch (address & 0xF00000) {
philpem@34 714 case 0xC00000: // Expansion slots
philpem@34 715 case 0xD00000:
philpem@34 716 switch (address & 0xFC0000) {
philpem@34 717 case 0xC00000: // Expansion slot 0
philpem@34 718 case 0xC40000: // Expansion slot 1
philpem@34 719 case 0xC80000: // Expansion slot 2
philpem@34 720 case 0xCC0000: // Expansion slot 3
philpem@34 721 case 0xD00000: // Expansion slot 4
philpem@34 722 case 0xD40000: // Expansion slot 5
philpem@34 723 case 0xD80000: // Expansion slot 6
philpem@34 724 case 0xDC0000: // Expansion slot 7
philpem@34 725 fprintf(stderr, "NOTE: WR16 to expansion card space, addr=0x%08X, data=0x%04X\n", address, value);
philpem@34 726 break;
philpem@34 727 }
philpem@34 728 break;
philpem@34 729 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@34 730 case 0xF00000:
philpem@34 731 switch (address & 0x070000) {
philpem@34 732 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@34 733 break;
philpem@34 734 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@34 735 break;
philpem@34 736 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@34 737 break;
philpem@34 738 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@34 739 break;
philpem@34 740 default:
philpem@34 741 fprintf(stderr, "NOTE: WR16 to undefined E/F-block space, addr=0x%08X, data=0x%04X\n", address, value);
philpem@34 742 }
philpem@25 743 }
philpem@7 744 }
philpem@4 745 }
philpem@4 746
philpem@32 747 /**
philpem@32 748 * @brief Write M68K memory, 8-bit
philpem@32 749 */
philpem@4 750 void m68k_write_memory_8(uint32_t address, uint32_t value)
philpem@4 751 {
philpem@7 752 // If ROMLMAP is set, force system to access ROM
philpem@7 753 if (!state.romlmap)
philpem@7 754 address |= 0x800000;
philpem@7 755
philpem@32 756 // Check access permissions
philpem@32 757 ACCESS_CHECK_WR();
philpem@32 758
philpem@9 759 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@7 760 // ROM access
philpem@34 761 WR8(state.rom, address, ROM_SIZE - 1, value);
philpem@26 762 } else if (address <= (state.ram_size - 1)) {
philpem@32 763 // RAM access
philpem@34 764 WR8(state.ram, mapAddr(address, false), state.ram_size - 1, value);
philpem@34 765 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@34 766 // I/O register space, zone A
philpem@34 767 printf("WR8 0x%08X ==> ??? %s\n", address, m68k_get_reg(NULL, M68K_REG_SR) & 0x2000 ? "[SV]" : "");
philpem@34 768 switch (address & 0x0F0000) {
philpem@34 769 case 0x000000: // Map RAM access
philpem@34 770 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=%08X, data=%02X\n", address, value);
philpem@34 771 WR8(state.map, address, 0x7FF, value);
philpem@34 772 break;
philpem@34 773 case 0x010000: // General Status Register
philpem@34 774 state.genstat = (value & 0xffff);
philpem@34 775 break;
philpem@34 776 case 0x020000: // Video RAM
philpem@34 777 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=%08X\n, data=0x%02X", address, value);
philpem@34 778 WR8(state.vram, address, 0x7FFF, value);
philpem@34 779 break;
philpem@34 780 case 0x030000: // Bus Status Register 0
philpem@34 781 case 0x040000: // Bus Status Register 1
philpem@34 782 case 0x050000: // Phone status
philpem@34 783 case 0x060000: // DMA Count
philpem@34 784 case 0x070000: // Line Printer Status Register
philpem@34 785 case 0x080000: // Real Time Clock
philpem@34 786 case 0x090000: // Phone registers
philpem@34 787 switch (address & 0x0FF000) {
philpem@34 788 case 0x090000: // Handset relay
philpem@34 789 case 0x098000:
philpem@34 790 case 0x091000: // Line select 2
philpem@34 791 case 0x099000:
philpem@34 792 case 0x092000: // Hook relay 1
philpem@34 793 case 0x09A000:
philpem@34 794 case 0x093000: // Hook relay 2
philpem@34 795 case 0x09B000:
philpem@34 796 case 0x094000: // Line 1 hold
philpem@34 797 case 0x09C000:
philpem@34 798 case 0x095000: // Line 2 hold
philpem@34 799 case 0x09D000:
philpem@34 800 case 0x096000: // Line 1 A-lead
philpem@34 801 case 0x09E000:
philpem@34 802 case 0x097000: // Line 2 A-lead
philpem@34 803 case 0x09F000:
philpem@34 804 break;
philpem@34 805 }
philpem@34 806 break;
philpem@34 807 case 0x0A0000: // Miscellaneous Control Register
philpem@34 808 case 0x0B0000: // TM/DIALWR
philpem@34 809 case 0x0C0000: // CSR
philpem@34 810 case 0x0D0000: // DMA Address Register
philpem@34 811 case 0x0E0000: // Disk Control Register
philpem@34 812 case 0x0F0000: // Line Printer Data Register
philpem@34 813 break;
philpem@34 814 }
philpem@34 815 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@34 816 // I/O register space, zone B
philpem@34 817 printf("WR8 0x%08X ==> 0x%08X %s\n", address, value, m68k_get_reg(NULL, M68K_REG_SR) & 0x2000 ? "[SV]" : "");
philpem@34 818 switch (address & 0xF00000) {
philpem@34 819 case 0xC00000: // Expansion slots
philpem@34 820 case 0xD00000:
philpem@34 821 switch (address & 0xFC0000) {
philpem@34 822 case 0xC00000: // Expansion slot 0
philpem@34 823 case 0xC40000: // Expansion slot 1
philpem@34 824 case 0xC80000: // Expansion slot 2
philpem@34 825 case 0xCC0000: // Expansion slot 3
philpem@34 826 case 0xD00000: // Expansion slot 4
philpem@34 827 case 0xD40000: // Expansion slot 5
philpem@34 828 case 0xD80000: // Expansion slot 6
philpem@34 829 case 0xDC0000: // Expansion slot 7
philpem@34 830 fprintf(stderr, "NOTE: WR8 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
philpem@34 831 break;
philpem@34 832 }
philpem@34 833 break;
philpem@34 834 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@34 835 case 0xF00000:
philpem@34 836 switch (address & 0x070000) {
philpem@34 837 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@34 838 break;
philpem@34 839 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@34 840 break;
philpem@34 841 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@34 842 break;
philpem@34 843 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@34 844 break;
philpem@34 845 default:
philpem@34 846 fprintf(stderr, "NOTE: WR8 to undefined E/F-block space, addr=0x%08X, data=0x%08X\n", address, value);
philpem@34 847 }
philpem@9 848 }
philpem@7 849 }
philpem@4 850 }
philpem@4 851
philpem@34 852
philpem@10 853 // for the disassembler
philpem@9 854 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
philpem@9 855 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
philpem@9 856 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }
philpem@9 857
philpem@27 858
philpem@27 859 /****************************
philpem@27 860 * blessed be thy main()...
philpem@27 861 ****************************/
philpem@27 862
philpem@0 863 int main(void)
philpem@0 864 {
philpem@7 865 // copyright banner
philpem@16 866 printf("FreeBee: A Quick-and-Dirty AT&T 3B1 Emulator. Version %s, %s mode.\n", VER_FULLSTR, VER_BUILD_TYPE);
philpem@17 867 printf("Copyright (C) 2010 P. A. Pemberton. All rights reserved.\nLicensed under the Apache License Version 2.0.\n");
philpem@17 868 printf("Musashi M680x0 emulator engine developed by Karl Stenerud <kstenerud@gmail.com>\n");
philpem@16 869 printf("Built %s by %s@%s.\n", VER_COMPILE_DATETIME, VER_COMPILE_BY, VER_COMPILE_HOST);
philpem@16 870 printf("Compiler: %s\n", VER_COMPILER);
philpem@16 871 printf("CFLAGS: %s\n", VER_CFLAGS);
philpem@17 872 printf("\n");
philpem@7 873
philpem@7 874 // set up system state
philpem@7 875 // 512K of RAM
philpem@18 876 state_init(512*1024);
philpem@7 877
philpem@20 878 // set up musashi and reset the CPU
philpem@7 879 m68k_set_cpu_type(M68K_CPU_TYPE_68010);
philpem@7 880 m68k_pulse_reset();
philpem@9 881
philpem@28 882 // Set up SDL
philpem@20 883 if (SDL_Init(SDL_INIT_VIDEO | SDL_INIT_TIMER) == -1) {
philpem@20 884 printf("Could not initialise SDL: %s.\n", SDL_GetError());
philpem@28 885 exit(EXIT_FAILURE);
philpem@20 886 }
philpem@7 887
philpem@28 888 // Make sure SDL cleans up after itself
philpem@28 889 atexit(SDL_Quit);
philpem@28 890
philpem@28 891 // Set up the video display
philpem@28 892 SDL_Surface *screen = NULL;
philpem@28 893 if ((screen = SDL_SetVideoMode(720, 384, 8, SDL_SWSURFACE | SDL_ANYFORMAT)) == NULL) {
philpem@28 894 printf("Could not find a suitable video mode: %s.\n", SDL_GetError());
philpem@28 895 exit(EXIT_FAILURE);
philpem@28 896 }
philpem@32 897 printf("Set %dx%d at %d bits-per-pixel mode\n\n", screen->w, screen->h, screen->format->BitsPerPixel);
philpem@28 898 SDL_WM_SetCaption("FreeBee 3B1 emulator", "FreeBee");
philpem@28 899
philpem@20 900 /***
philpem@20 901 * The 3B1 CPU runs at 10MHz, with DMA running at 1MHz and video refreshing at
philpem@20 902 * around 60Hz (???), with a 60Hz periodic interrupt.
philpem@20 903 */
philpem@20 904 const uint32_t TIMESLOT_FREQUENCY = 240; // Hz
philpem@20 905 const uint32_t MILLISECS_PER_TIMESLOT = 1e3 / TIMESLOT_FREQUENCY;
philpem@20 906 const uint32_t CLOCKS_PER_60HZ = (10e6 / 60);
philpem@20 907 uint32_t next_timeslot = SDL_GetTicks() + MILLISECS_PER_TIMESLOT;
philpem@20 908 uint32_t clock_cycles = 0;
philpem@16 909 bool exitEmu = false;
philpem@16 910 for (;;) {
philpem@20 911 // Run the CPU for however many cycles we need to. CPU core clock is
philpem@20 912 // 10MHz, and we're running at 240Hz/timeslot. Thus: 10e6/240 or
philpem@20 913 // 41667 cycles per timeslot.
philpem@20 914 clock_cycles += m68k_execute(10e6/TIMESLOT_FREQUENCY);
philpem@20 915
philpem@20 916 // TODO: run DMA here
philpem@16 917
philpem@20 918 // Is it time to run the 60Hz periodic interrupt yet?
philpem@20 919 if (clock_cycles > CLOCKS_PER_60HZ) {
philpem@20 920 // TODO: refresh screen
philpem@20 921 // TODO: trigger periodic interrupt (if enabled)
philpem@20 922 // decrement clock cycle counter, we've handled the intr.
philpem@20 923 clock_cycles -= CLOCKS_PER_60HZ;
philpem@16 924 }
philpem@16 925
philpem@20 926 // make sure frame rate is equal to real time
philpem@20 927 uint32_t now = SDL_GetTicks();
philpem@20 928 if (now < next_timeslot) {
philpem@20 929 // timeslot finished early -- eat up some time
philpem@20 930 SDL_Delay(next_timeslot - now);
philpem@20 931 } else {
philpem@20 932 // timeslot finished late -- skip ahead to gain time
philpem@20 933 // TODO: if this happens a lot, we should let the user know
philpem@20 934 // that their PC might not be fast enough...
philpem@20 935 next_timeslot = now;
philpem@20 936 }
philpem@20 937 // advance to the next timeslot
philpem@20 938 next_timeslot += MILLISECS_PER_TIMESLOT;
philpem@20 939
philpem@20 940 // if we've been asked to exit the emulator, then do so.
philpem@16 941 if (exitEmu) break;
philpem@16 942 }
philpem@7 943
philpem@7 944 // shut down and exit
philpem@20 945 SDL_Quit();
philpem@7 946
philpem@0 947 return 0;
philpem@0 948 }