src/memory.c

Fri, 03 Dec 2010 00:12:53 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Fri, 03 Dec 2010 00:12:53 +0000
changeset 44
f928be115194
parent 43
4d59e4ceef52
child 46
7d14fab5e4aa
permissions
-rw-r--r--

fix state/status transposition, add GENCON.PIE handling

philpem@40 1 #include <stdio.h>
philpem@40 2 #include <stdlib.h>
philpem@40 3 #include <stdint.h>
philpem@40 4 #include <stdbool.h>
philpem@40 5 #include "musashi/m68k.h"
philpem@40 6 #include "state.h"
philpem@40 7 #include "memory.h"
philpem@40 8
philpem@40 9 /******************
philpem@40 10 * Memory mapping
philpem@40 11 ******************/
philpem@40 12
philpem@40 13 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
philpem@40 14
philpem@40 15 uint32_t mapAddr(uint32_t addr, bool writing)
philpem@40 16 {
philpem@40 17 if (addr < 0x400000) {
philpem@40 18 // RAM access. Check against the Map RAM
philpem@40 19 // Start by getting the original page address
philpem@40 20 uint16_t page = (addr >> 12) & 0x3FF;
philpem@40 21
philpem@40 22 // Look it up in the map RAM and get the physical page address
philpem@40 23 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
philpem@40 24
philpem@40 25 // Update the Page Status bits
philpem@40 26 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
philpem@40 27 if (pagebits != 0) {
philpem@40 28 if (writing)
philpem@40 29 state.map[page*2] |= 0x60; // Page written to (dirty)
philpem@40 30 else
philpem@40 31 state.map[page*2] |= 0x40; // Page accessed but not written
philpem@40 32 }
philpem@40 33
philpem@40 34 // Return the address with the new physical page spliced in
philpem@40 35 return (new_page_addr << 12) + (addr & 0xFFF);
philpem@40 36 } else {
philpem@40 37 // I/O, VRAM or MapRAM space; no mapping is performed or required
philpem@40 38 // TODO: assert here?
philpem@40 39 return addr;
philpem@40 40 }
philpem@40 41 }
philpem@40 42
philpem@40 43 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)
philpem@40 44 {
philpem@40 45 // Are we in Supervisor mode?
philpem@40 46 if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
philpem@40 47 // Yes. We can do anything we like.
philpem@40 48 return MEM_ALLOWED;
philpem@40 49
philpem@40 50 // If we're here, then we must be in User mode.
philpem@40 51 // Check that the user didn't access memory outside of the RAM area
philpem@40 52 if (addr >= 0x400000)
philpem@40 53 return MEM_UIE;
philpem@40 54
philpem@40 55 // This leaves us with Page Fault checking. Get the page bits for this page.
philpem@40 56 uint16_t page = (addr >> 12) & 0x3FF;
philpem@40 57 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
philpem@40 58
philpem@40 59 // Check page is present
philpem@40 60 if ((pagebits & 0x03) == 0)
philpem@40 61 return MEM_PAGEFAULT;
philpem@40 62
philpem@40 63 // User attempt to access the kernel
philpem@40 64 // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
philpem@40 65 if (((addr >> 19) & 0x0F) == 0)
philpem@40 66 return MEM_KERNEL;
philpem@40 67
philpem@40 68 // Check page is write enabled
philpem@40 69 if ((pagebits & 0x04) == 0)
philpem@40 70 return MEM_PAGE_NO_WE;
philpem@40 71
philpem@40 72 // Page access allowed.
philpem@40 73 return MEM_ALLOWED;
philpem@40 74 }
philpem@40 75
philpem@40 76 #undef MAPRAM
philpem@40 77
philpem@40 78
philpem@40 79 /********************************************************
philpem@40 80 * m68k memory read/write support functions for Musashi
philpem@40 81 ********************************************************/
philpem@40 82
philpem@40 83 /**
philpem@40 84 * @brief Check memory access permissions for a write operation.
philpem@40 85 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
philpem@40 86 * gcc throws warnings when you have a return-with-value in a void
philpem@40 87 * function, even if the return-with-value is completely unreachable.
philpem@40 88 * Similarly it doesn't like it if you have a return without a value
philpem@40 89 * in a non-void function, even if it's impossible to ever reach the
philpem@40 90 * return-with-no-value. UGH!
philpem@40 91 */
philpem@40 92 #define ACCESS_CHECK_WR(address, bits) do { \
philpem@40 93 bool fault = false; \
philpem@40 94 /* MEM_STATUS st; */ \
philpem@40 95 switch (checkMemoryAccess(address, true)) { \
philpem@40 96 case MEM_ALLOWED: \
philpem@40 97 /* Access allowed */ \
philpem@40 98 break; \
philpem@40 99 case MEM_PAGEFAULT: \
philpem@40 100 /* Page fault */ \
philpem@44 101 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0); \
philpem@40 102 fault = true; \
philpem@40 103 break; \
philpem@40 104 case MEM_UIE: \
philpem@40 105 /* User access to memory above 4MB */ \
philpem@44 106 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0); \
philpem@40 107 fault = true; \
philpem@40 108 break; \
philpem@40 109 case MEM_KERNEL: \
philpem@40 110 case MEM_PAGE_NO_WE: \
philpem@40 111 /* kernel access or page not write enabled */ \
philpem@40 112 /* TODO: which regs need setting? */ \
philpem@40 113 fault = true; \
philpem@40 114 break; \
philpem@40 115 } \
philpem@40 116 \
philpem@40 117 if (fault) { \
philpem@40 118 if (bits >= 16) \
philpem@40 119 state.bsr0 = 0x7F00; \
philpem@40 120 else \
philpem@40 121 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
philpem@40 122 state.bsr0 |= (address >> 16); \
philpem@40 123 state.bsr1 = address & 0xffff; \
philpem@40 124 printf("ERR: BusError WR\n"); \
philpem@40 125 m68k_pulse_bus_error(); \
philpem@40 126 return; \
philpem@40 127 } \
philpem@40 128 } while (false)
philpem@40 129
philpem@40 130 /**
philpem@40 131 * @brief Check memory access permissions for a read operation.
philpem@40 132 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
philpem@40 133 * gcc throws warnings when you have a return-with-value in a void
philpem@40 134 * function, even if the return-with-value is completely unreachable.
philpem@40 135 * Similarly it doesn't like it if you have a return without a value
philpem@40 136 * in a non-void function, even if it's impossible to ever reach the
philpem@40 137 * return-with-no-value. UGH!
philpem@40 138 */
philpem@40 139 #define ACCESS_CHECK_RD(address, bits) do { \
philpem@40 140 bool fault = false; \
philpem@40 141 /* MEM_STATUS st; */ \
philpem@40 142 switch (checkMemoryAccess(address, false)) { \
philpem@40 143 case MEM_ALLOWED: \
philpem@40 144 /* Access allowed */ \
philpem@40 145 break; \
philpem@40 146 case MEM_PAGEFAULT: \
philpem@40 147 /* Page fault */ \
philpem@44 148 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0); \
philpem@40 149 fault = true; \
philpem@40 150 break; \
philpem@40 151 case MEM_UIE: \
philpem@40 152 /* User access to memory above 4MB */ \
philpem@44 153 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0); \
philpem@40 154 fault = true; \
philpem@40 155 break; \
philpem@40 156 case MEM_KERNEL: \
philpem@40 157 case MEM_PAGE_NO_WE: \
philpem@40 158 /* kernel access or page not write enabled */ \
philpem@40 159 /* TODO: which regs need setting? */ \
philpem@40 160 fault = true; \
philpem@40 161 break; \
philpem@40 162 } \
philpem@40 163 \
philpem@40 164 if (fault) { \
philpem@40 165 if (bits >= 16) \
philpem@40 166 state.bsr0 = 0x7F00; \
philpem@40 167 else \
philpem@40 168 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
philpem@40 169 state.bsr0 |= (address >> 16); \
philpem@40 170 state.bsr1 = address & 0xffff; \
philpem@40 171 printf("ERR: BusError RD\n"); \
philpem@40 172 m68k_pulse_bus_error(); \
philpem@40 173 return 0xFFFFFFFF; \
philpem@40 174 } \
philpem@40 175 } while (false)
philpem@40 176
philpem@40 177 // Logging macros
philpem@40 178 #define LOG_NOT_HANDLED_R(bits) \
philpem@40 179 do { \
philpem@40 180 if (!handled) \
philpem@40 181 printf("unhandled read%02d, addr=0x%08X\n", bits, address); \
philpem@40 182 } while (0);
philpem@40 183
philpem@40 184 #define LOG_NOT_HANDLED_W(bits) \
philpem@40 185 do { \
philpem@40 186 if (!handled) \
philpem@40 187 printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, value); \
philpem@40 188 } while (0);
philpem@40 189
philpem@40 190 /**
philpem@40 191 * @brief Read M68K memory, 32-bit
philpem@40 192 */
philpem@40 193 uint32_t m68k_read_memory_32(uint32_t address)
philpem@40 194 {
philpem@40 195 uint32_t data = 0xFFFFFFFF;
philpem@40 196 bool handled = false;
philpem@40 197
philpem@40 198 // If ROMLMAP is set, force system to access ROM
philpem@40 199 if (!state.romlmap)
philpem@40 200 address |= 0x800000;
philpem@40 201
philpem@40 202 // Check access permissions
philpem@40 203 ACCESS_CHECK_RD(address, 32);
philpem@40 204
philpem@40 205 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 206 // ROM access
philpem@40 207 data = RD32(state.rom, address, ROM_SIZE - 1);
philpem@40 208 handled = true;
philpem@40 209 } else if (address <= (state.ram_size - 1)) {
philpem@40 210 // RAM access
philpem@40 211 data = RD32(state.ram, mapAddr(address, false), state.ram_size - 1);
philpem@40 212 handled = true;
philpem@40 213 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 214 // I/O register space, zone A
philpem@40 215 switch (address & 0x0F0000) {
philpem@40 216 case 0x000000: // Map RAM access
philpem@40 217 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 218 data = RD32(state.map, address, 0x7FF);
philpem@40 219 handled = true;
philpem@40 220 break;
philpem@40 221 case 0x010000: // General Status Register
philpem@40 222 data = ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
philpem@40 223 handled = true;
philpem@40 224 break;
philpem@40 225 case 0x020000: // Video RAM
philpem@40 226 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 227 data = RD32(state.vram, address, 0x7FFF);
philpem@40 228 handled = true;
philpem@40 229 break;
philpem@40 230 case 0x030000: // Bus Status Register 0
philpem@40 231 data = ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
philpem@40 232 handled = true;
philpem@40 233 break;
philpem@40 234 case 0x040000: // Bus Status Register 1
philpem@40 235 data = ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
philpem@40 236 handled = true;
philpem@40 237 break;
philpem@40 238 case 0x050000: // Phone status
philpem@40 239 break;
philpem@40 240 case 0x060000: // DMA Count
philpem@40 241 break;
philpem@40 242 case 0x070000: // Line Printer Status Register
philpem@40 243 break;
philpem@40 244 case 0x080000: // Real Time Clock
philpem@40 245 break;
philpem@40 246 case 0x090000: // Phone registers
philpem@40 247 switch (address & 0x0FF000) {
philpem@40 248 case 0x090000: // Handset relay
philpem@40 249 case 0x098000:
philpem@40 250 break;
philpem@40 251 case 0x091000: // Line select 2
philpem@40 252 case 0x099000:
philpem@40 253 break;
philpem@40 254 case 0x092000: // Hook relay 1
philpem@40 255 case 0x09A000:
philpem@40 256 break;
philpem@40 257 case 0x093000: // Hook relay 2
philpem@40 258 case 0x09B000:
philpem@40 259 break;
philpem@40 260 case 0x094000: // Line 1 hold
philpem@40 261 case 0x09C000:
philpem@40 262 break;
philpem@40 263 case 0x095000: // Line 2 hold
philpem@40 264 case 0x09D000:
philpem@40 265 break;
philpem@40 266 case 0x096000: // Line 1 A-lead
philpem@40 267 case 0x09E000:
philpem@40 268 break;
philpem@40 269 case 0x097000: // Line 2 A-lead
philpem@40 270 case 0x09F000:
philpem@40 271 break;
philpem@40 272 }
philpem@40 273 break;
philpem@40 274 case 0x0A0000: // Miscellaneous Control Register
philpem@40 275 break;
philpem@40 276 case 0x0B0000: // TM/DIALWR
philpem@40 277 break;
philpem@43 278 case 0x0C0000: // Clear Status Register
philpem@43 279 handled = true;
philpem@40 280 break;
philpem@40 281 case 0x0D0000: // DMA Address Register
philpem@40 282 break;
philpem@40 283 case 0x0E0000: // Disk Control Register
philpem@40 284 break;
philpem@40 285 case 0x0F0000: // Line Printer Data Register
philpem@40 286 break;
philpem@40 287 }
philpem@40 288 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 289 // I/O register space, zone B
philpem@40 290 switch (address & 0xF00000) {
philpem@40 291 case 0xC00000: // Expansion slots
philpem@40 292 case 0xD00000:
philpem@40 293 switch (address & 0xFC0000) {
philpem@40 294 case 0xC00000: // Expansion slot 0
philpem@40 295 case 0xC40000: // Expansion slot 1
philpem@40 296 case 0xC80000: // Expansion slot 2
philpem@40 297 case 0xCC0000: // Expansion slot 3
philpem@40 298 case 0xD00000: // Expansion slot 4
philpem@40 299 case 0xD40000: // Expansion slot 5
philpem@40 300 case 0xD80000: // Expansion slot 6
philpem@40 301 case 0xDC0000: // Expansion slot 7
philpem@40 302 fprintf(stderr, "NOTE: RD32 from expansion card space, addr=0x%08X\n", address);
philpem@40 303 break;
philpem@40 304 }
philpem@40 305 break;
philpem@40 306 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 307 case 0xF00000:
philpem@40 308 switch (address & 0x070000) {
philpem@40 309 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@40 310 break;
philpem@40 311 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@40 312 break;
philpem@40 313 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 314 break;
philpem@40 315 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 316 break;
philpem@40 317 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 318 switch (address & 0x077000) {
philpem@40 319 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@44 320 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@40 321 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 322 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@44 323 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@44 324 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@44 325 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@44 326 // All write-only registers... TODO: bus error?
philpem@44 327 handled = true;
philpem@40 328 break;
philpem@44 329 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
philpem@40 330 break;
philpem@40 331 }
philpem@40 332 break;
philpem@40 333 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 334 break;
philpem@40 335 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 336 switch (address & 0x07F000) {
philpem@40 337 default:
philpem@40 338 break;
philpem@40 339 }
philpem@40 340 break;
philpem@40 341 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@40 342 break;
philpem@40 343 }
philpem@40 344 }
philpem@40 345 }
philpem@40 346
philpem@40 347 LOG_NOT_HANDLED_R(32);
philpem@40 348 return data;
philpem@40 349 }
philpem@40 350
philpem@40 351 /**
philpem@40 352 * @brief Read M68K memory, 16-bit
philpem@40 353 */
philpem@40 354 uint32_t m68k_read_memory_16(uint32_t address)
philpem@40 355 {
philpem@40 356 uint16_t data = 0xFFFF;
philpem@40 357 bool handled = false;
philpem@40 358
philpem@40 359 // If ROMLMAP is set, force system to access ROM
philpem@40 360 if (!state.romlmap)
philpem@40 361 address |= 0x800000;
philpem@40 362
philpem@40 363 // Check access permissions
philpem@40 364 ACCESS_CHECK_RD(address, 16);
philpem@40 365
philpem@40 366 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 367 // ROM access
philpem@40 368 data = RD16(state.rom, address, ROM_SIZE - 1);
philpem@40 369 handled = true;
philpem@40 370 } else if (address <= (state.ram_size - 1)) {
philpem@40 371 // RAM access
philpem@40 372 data = RD16(state.ram, mapAddr(address, false), state.ram_size - 1);
philpem@40 373 handled = true;
philpem@40 374 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 375 // I/O register space, zone A
philpem@40 376 switch (address & 0x0F0000) {
philpem@40 377 case 0x000000: // Map RAM access
philpem@40 378 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 379 data = RD16(state.map, address, 0x7FF);
philpem@40 380 handled = true;
philpem@40 381 break;
philpem@40 382 case 0x010000: // General Status Register
philpem@40 383 data = state.genstat;
philpem@40 384 handled = true;
philpem@40 385 break;
philpem@40 386 case 0x020000: // Video RAM
philpem@40 387 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 388 data = RD16(state.vram, address, 0x7FFF);
philpem@40 389 handled = true;
philpem@40 390 break;
philpem@40 391 case 0x030000: // Bus Status Register 0
philpem@40 392 data = state.bsr0;
philpem@40 393 handled = true;
philpem@40 394 break;
philpem@40 395 case 0x040000: // Bus Status Register 1
philpem@40 396 data = state.bsr1;
philpem@40 397 handled = true;
philpem@40 398 break;
philpem@40 399 case 0x050000: // Phone status
philpem@40 400 break;
philpem@40 401 case 0x060000: // DMA Count
philpem@40 402 break;
philpem@40 403 case 0x070000: // Line Printer Status Register
philpem@40 404 break;
philpem@40 405 case 0x080000: // Real Time Clock
philpem@40 406 break;
philpem@40 407 case 0x090000: // Phone registers
philpem@40 408 switch (address & 0x0FF000) {
philpem@40 409 case 0x090000: // Handset relay
philpem@40 410 case 0x098000:
philpem@40 411 break;
philpem@40 412 case 0x091000: // Line select 2
philpem@40 413 case 0x099000:
philpem@40 414 break;
philpem@40 415 case 0x092000: // Hook relay 1
philpem@40 416 case 0x09A000:
philpem@40 417 break;
philpem@40 418 case 0x093000: // Hook relay 2
philpem@40 419 case 0x09B000:
philpem@40 420 break;
philpem@40 421 case 0x094000: // Line 1 hold
philpem@40 422 case 0x09C000:
philpem@40 423 break;
philpem@40 424 case 0x095000: // Line 2 hold
philpem@40 425 case 0x09D000:
philpem@40 426 break;
philpem@40 427 case 0x096000: // Line 1 A-lead
philpem@40 428 case 0x09E000:
philpem@40 429 break;
philpem@40 430 case 0x097000: // Line 2 A-lead
philpem@40 431 case 0x09F000:
philpem@40 432 break;
philpem@40 433 }
philpem@40 434 break;
philpem@40 435 case 0x0A0000: // Miscellaneous Control Register
philpem@40 436 break;
philpem@40 437 case 0x0B0000: // TM/DIALWR
philpem@40 438 break;
philpem@43 439 case 0x0C0000: // Clear Status Register
philpem@43 440 handled = true;
philpem@40 441 break;
philpem@40 442 case 0x0D0000: // DMA Address Register
philpem@40 443 break;
philpem@40 444 case 0x0E0000: // Disk Control Register
philpem@40 445 break;
philpem@40 446 case 0x0F0000: // Line Printer Data Register
philpem@40 447 break;
philpem@40 448 }
philpem@40 449 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 450 // I/O register space, zone B
philpem@40 451 switch (address & 0xF00000) {
philpem@40 452 case 0xC00000: // Expansion slots
philpem@40 453 case 0xD00000:
philpem@40 454 switch (address & 0xFC0000) {
philpem@40 455 case 0xC00000: // Expansion slot 0
philpem@40 456 case 0xC40000: // Expansion slot 1
philpem@40 457 case 0xC80000: // Expansion slot 2
philpem@40 458 case 0xCC0000: // Expansion slot 3
philpem@40 459 case 0xD00000: // Expansion slot 4
philpem@40 460 case 0xD40000: // Expansion slot 5
philpem@40 461 case 0xD80000: // Expansion slot 6
philpem@40 462 case 0xDC0000: // Expansion slot 7
philpem@40 463 fprintf(stderr, "NOTE: RD16 from expansion card space, addr=0x%08X\n", address);
philpem@40 464 break;
philpem@40 465 }
philpem@40 466 break;
philpem@40 467 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 468 case 0xF00000:
philpem@40 469 switch (address & 0x070000) {
philpem@40 470 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@40 471 break;
philpem@40 472 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@40 473 break;
philpem@40 474 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 475 break;
philpem@40 476 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 477 break;
philpem@40 478 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 479 switch (address & 0x077000) {
philpem@40 480 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@44 481 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@40 482 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 483 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@40 484 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@40 485 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@40 486 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@44 487 // All write-only registers... TODO: bus error?
philpem@44 488 handled = true;
philpem@40 489 break;
philpem@40 490 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@40 491 break;
philpem@40 492 }
philpem@40 493 break;
philpem@40 494 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 495 break;
philpem@40 496 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 497 switch (address & 0x07F000) {
philpem@40 498 default:
philpem@40 499 break;
philpem@40 500 }
philpem@40 501 break;
philpem@40 502 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@40 503 break;
philpem@40 504 }
philpem@40 505 }
philpem@40 506 }
philpem@40 507
philpem@40 508 LOG_NOT_HANDLED_R(32);
philpem@40 509 return data;
philpem@40 510 }
philpem@40 511
philpem@40 512 /**
philpem@40 513 * @brief Read M68K memory, 8-bit
philpem@40 514 */
philpem@40 515 uint32_t m68k_read_memory_8(uint32_t address)
philpem@40 516 {
philpem@40 517 uint8_t data = 0xFF;
philpem@40 518 bool handled = false;
philpem@40 519
philpem@40 520 // If ROMLMAP is set, force system to access ROM
philpem@40 521 if (!state.romlmap)
philpem@40 522 address |= 0x800000;
philpem@40 523
philpem@40 524 // Check access permissions
philpem@40 525 ACCESS_CHECK_RD(address, 8);
philpem@40 526
philpem@40 527 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 528 // ROM access
philpem@40 529 data = RD8(state.rom, address, ROM_SIZE - 1);
philpem@40 530 handled = true;
philpem@40 531 } else if (address <= (state.ram_size - 1)) {
philpem@40 532 // RAM access
philpem@40 533 data = RD8(state.ram, mapAddr(address, false), state.ram_size - 1);
philpem@40 534 handled = true;
philpem@40 535 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 536 // I/O register space, zone A
philpem@40 537 switch (address & 0x0F0000) {
philpem@40 538 case 0x000000: // Map RAM access
philpem@40 539 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
philpem@40 540 data = RD8(state.map, address, 0x7FF);
philpem@40 541 handled = true;
philpem@40 542 break;
philpem@40 543 case 0x010000: // General Status Register
philpem@40 544 if ((address & 1) == 0)
philpem@40 545 data = (state.genstat >> 8) & 0xff;
philpem@40 546 else
philpem@40 547 data = (state.genstat) & 0xff;
philpem@40 548 handled = true;
philpem@40 549 break;
philpem@40 550 case 0x020000: // Video RAM
philpem@40 551 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
philpem@40 552 data = RD8(state.vram, address, 0x7FFF);
philpem@40 553 handled = true;
philpem@40 554 break;
philpem@40 555 case 0x030000: // Bus Status Register 0
philpem@40 556 if ((address & 1) == 0)
philpem@40 557 data = (state.bsr0 >> 8) & 0xff;
philpem@40 558 else
philpem@40 559 data = (state.bsr0) & 0xff;
philpem@40 560 handled = true;
philpem@40 561 break;
philpem@40 562 case 0x040000: // Bus Status Register 1
philpem@40 563 if ((address & 1) == 0)
philpem@40 564 data = (state.bsr1 >> 8) & 0xff;
philpem@40 565 else
philpem@40 566 data = (state.bsr1) & 0xff;
philpem@40 567 handled = true;
philpem@40 568 break;
philpem@40 569 case 0x050000: // Phone status
philpem@40 570 break;
philpem@40 571 case 0x060000: // DMA Count
philpem@40 572 break;
philpem@40 573 case 0x070000: // Line Printer Status Register
philpem@40 574 break;
philpem@40 575 case 0x080000: // Real Time Clock
philpem@40 576 break;
philpem@40 577 case 0x090000: // Phone registers
philpem@40 578 switch (address & 0x0FF000) {
philpem@40 579 case 0x090000: // Handset relay
philpem@40 580 case 0x098000:
philpem@40 581 break;
philpem@40 582 case 0x091000: // Line select 2
philpem@40 583 case 0x099000:
philpem@40 584 break;
philpem@40 585 case 0x092000: // Hook relay 1
philpem@40 586 case 0x09A000:
philpem@40 587 break;
philpem@40 588 case 0x093000: // Hook relay 2
philpem@40 589 case 0x09B000:
philpem@40 590 break;
philpem@40 591 case 0x094000: // Line 1 hold
philpem@40 592 case 0x09C000:
philpem@40 593 break;
philpem@40 594 case 0x095000: // Line 2 hold
philpem@40 595 case 0x09D000:
philpem@40 596 break;
philpem@40 597 case 0x096000: // Line 1 A-lead
philpem@40 598 case 0x09E000:
philpem@40 599 break;
philpem@40 600 case 0x097000: // Line 2 A-lead
philpem@40 601 case 0x09F000:
philpem@40 602 break;
philpem@40 603 }
philpem@40 604 break;
philpem@40 605 case 0x0A0000: // Miscellaneous Control Register
philpem@40 606 break;
philpem@40 607 case 0x0B0000: // TM/DIALWR
philpem@40 608 break;
philpem@43 609 case 0x0C0000: // Clear Status Register
philpem@43 610 handled = true;
philpem@40 611 break;
philpem@40 612 case 0x0D0000: // DMA Address Register
philpem@40 613 break;
philpem@40 614 case 0x0E0000: // Disk Control Register
philpem@40 615 break;
philpem@40 616 case 0x0F0000: // Line Printer Data Register
philpem@40 617 break;
philpem@40 618 }
philpem@40 619 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 620 // I/O register space, zone B
philpem@40 621 switch (address & 0xF00000) {
philpem@40 622 case 0xC00000: // Expansion slots
philpem@40 623 case 0xD00000:
philpem@40 624 switch (address & 0xFC0000) {
philpem@40 625 case 0xC00000: // Expansion slot 0
philpem@40 626 case 0xC40000: // Expansion slot 1
philpem@40 627 case 0xC80000: // Expansion slot 2
philpem@40 628 case 0xCC0000: // Expansion slot 3
philpem@40 629 case 0xD00000: // Expansion slot 4
philpem@40 630 case 0xD40000: // Expansion slot 5
philpem@40 631 case 0xD80000: // Expansion slot 6
philpem@40 632 case 0xDC0000: // Expansion slot 7
philpem@40 633 fprintf(stderr, "NOTE: RD8 from expansion card space, addr=0x%08X\n", address);
philpem@40 634 break;
philpem@40 635 }
philpem@40 636 break;
philpem@40 637 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 638 case 0xF00000:
philpem@40 639 switch (address & 0x070000) {
philpem@40 640 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@40 641 break;
philpem@40 642 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@40 643 break;
philpem@40 644 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 645 break;
philpem@40 646 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 647 break;
philpem@40 648 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 649 switch (address & 0x077000) {
philpem@40 650 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@44 651 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@40 652 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 653 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@40 654 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@40 655 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@40 656 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@44 657 // All write-only registers... TODO: bus error?
philpem@44 658 handled = true;
philpem@40 659 break;
philpem@40 660 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@40 661 break;
philpem@40 662 }
philpem@40 663 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 664 break;
philpem@40 665 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 666 switch (address & 0x07F000) {
philpem@40 667 default:
philpem@40 668 break;
philpem@40 669 }
philpem@40 670 break;
philpem@40 671 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@40 672 break;
philpem@40 673 }
philpem@40 674 }
philpem@40 675 }
philpem@40 676
philpem@40 677 LOG_NOT_HANDLED_R(8);
philpem@40 678
philpem@40 679 return data;
philpem@40 680 }
philpem@40 681
philpem@40 682 /**
philpem@40 683 * @brief Write M68K memory, 32-bit
philpem@40 684 */
philpem@40 685 void m68k_write_memory_32(uint32_t address, uint32_t value)
philpem@40 686 {
philpem@40 687 bool handled = false;
philpem@40 688
philpem@40 689 // If ROMLMAP is set, force system to access ROM
philpem@40 690 if (!state.romlmap)
philpem@40 691 address |= 0x800000;
philpem@40 692
philpem@40 693 // Check access permissions
philpem@40 694 ACCESS_CHECK_WR(address, 32);
philpem@40 695
philpem@40 696 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 697 // ROM access
philpem@40 698 handled = true;
philpem@40 699 } else if (address <= (state.ram_size - 1)) {
philpem@40 700 // RAM access
philpem@40 701 WR32(state.ram, mapAddr(address, false), state.ram_size - 1, value);
philpem@40 702 handled = true;
philpem@40 703 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 704 // I/O register space, zone A
philpem@40 705 switch (address & 0x0F0000) {
philpem@40 706 case 0x000000: // Map RAM access
philpem@40 707 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
philpem@40 708 WR32(state.map, address, 0x7FF, value);
philpem@40 709 handled = true;
philpem@40 710 break;
philpem@40 711 case 0x010000: // General Status Register
philpem@40 712 state.genstat = (value & 0xffff);
philpem@40 713 handled = true;
philpem@40 714 break;
philpem@40 715 case 0x020000: // Video RAM
philpem@40 716 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
philpem@40 717 WR32(state.vram, address, 0x7FFF, value);
philpem@40 718 handled = true;
philpem@40 719 break;
philpem@40 720 case 0x030000: // Bus Status Register 0
philpem@40 721 break;
philpem@40 722 case 0x040000: // Bus Status Register 1
philpem@40 723 break;
philpem@40 724 case 0x050000: // Phone status
philpem@40 725 break;
philpem@40 726 case 0x060000: // DMA Count
philpem@40 727 break;
philpem@40 728 case 0x070000: // Line Printer Status Register
philpem@40 729 break;
philpem@40 730 case 0x080000: // Real Time Clock
philpem@40 731 break;
philpem@40 732 case 0x090000: // Phone registers
philpem@40 733 switch (address & 0x0FF000) {
philpem@40 734 case 0x090000: // Handset relay
philpem@40 735 case 0x098000:
philpem@40 736 break;
philpem@40 737 case 0x091000: // Line select 2
philpem@40 738 case 0x099000:
philpem@40 739 break;
philpem@40 740 case 0x092000: // Hook relay 1
philpem@40 741 case 0x09A000:
philpem@40 742 break;
philpem@40 743 case 0x093000: // Hook relay 2
philpem@40 744 case 0x09B000:
philpem@40 745 break;
philpem@40 746 case 0x094000: // Line 1 hold
philpem@40 747 case 0x09C000:
philpem@40 748 break;
philpem@40 749 case 0x095000: // Line 2 hold
philpem@40 750 case 0x09D000:
philpem@40 751 break;
philpem@40 752 case 0x096000: // Line 1 A-lead
philpem@40 753 case 0x09E000:
philpem@40 754 break;
philpem@40 755 case 0x097000: // Line 2 A-lead
philpem@40 756 case 0x09F000:
philpem@40 757 break;
philpem@40 758 }
philpem@40 759 break;
philpem@40 760 case 0x0A0000: // Miscellaneous Control Register
philpem@40 761 break;
philpem@40 762 case 0x0B0000: // TM/DIALWR
philpem@40 763 break;
philpem@43 764 case 0x0C0000: // Clear Status Register
philpem@43 765 state.genstat = 0xFFFF;
philpem@43 766 state.bsr0 = 0xFFFF;
philpem@43 767 state.bsr1 = 0xFFFF;
philpem@43 768 handled = true;
philpem@40 769 break;
philpem@40 770 case 0x0D0000: // DMA Address Register
philpem@40 771 break;
philpem@40 772 case 0x0E0000: // Disk Control Register
philpem@40 773 break;
philpem@40 774 case 0x0F0000: // Line Printer Data Register
philpem@40 775 break;
philpem@40 776 }
philpem@40 777 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 778 // I/O register space, zone B
philpem@40 779 switch (address & 0xF00000) {
philpem@40 780 case 0xC00000: // Expansion slots
philpem@40 781 case 0xD00000:
philpem@40 782 switch (address & 0xFC0000) {
philpem@40 783 case 0xC00000: // Expansion slot 0
philpem@40 784 case 0xC40000: // Expansion slot 1
philpem@40 785 case 0xC80000: // Expansion slot 2
philpem@40 786 case 0xCC0000: // Expansion slot 3
philpem@40 787 case 0xD00000: // Expansion slot 4
philpem@40 788 case 0xD40000: // Expansion slot 5
philpem@40 789 case 0xD80000: // Expansion slot 6
philpem@40 790 case 0xDC0000: // Expansion slot 7
philpem@40 791 fprintf(stderr, "NOTE: WR32 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
philpem@40 792 handled = true;
philpem@40 793 break;
philpem@40 794 }
philpem@40 795 break;
philpem@40 796 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 797 case 0xF00000:
philpem@40 798 switch (address & 0x070000) {
philpem@40 799 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@40 800 break;
philpem@40 801 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@40 802 break;
philpem@40 803 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 804 break;
philpem@40 805 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 806 break;
philpem@40 807 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 808 switch (address & 0x077000) {
philpem@40 809 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@40 810 break;
philpem@44 811 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@44 812 state.pie = ((value & 0x8000) == 0x8000);
philpem@44 813 handled = true;
philpem@40 814 break;
philpem@40 815 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 816 break;
philpem@40 817 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@40 818 state.romlmap = ((value & 0x8000) == 0x8000);
philpem@44 819 handled = true;
philpem@40 820 break;
philpem@40 821 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@40 822 break;
philpem@40 823 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@40 824 break;
philpem@40 825 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@40 826 break;
philpem@40 827 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@40 828 break;
philpem@40 829 }
philpem@40 830 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 831 break;
philpem@40 832 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 833 switch (address & 0x07F000) {
philpem@40 834 default:
philpem@40 835 break;
philpem@40 836 }
philpem@40 837 break;
philpem@40 838 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@40 839 break;
philpem@40 840 }
philpem@40 841 }
philpem@40 842 }
philpem@40 843
philpem@40 844 LOG_NOT_HANDLED_W(32);
philpem@40 845 }
philpem@40 846
philpem@40 847 /**
philpem@40 848 * @brief Write M68K memory, 16-bit
philpem@40 849 */
philpem@40 850 void m68k_write_memory_16(uint32_t address, uint32_t value)
philpem@40 851 {
philpem@40 852 bool handled = false;
philpem@40 853
philpem@40 854 // If ROMLMAP is set, force system to access ROM
philpem@40 855 if (!state.romlmap)
philpem@40 856 address |= 0x800000;
philpem@40 857
philpem@40 858 // Check access permissions
philpem@40 859 ACCESS_CHECK_WR(address, 16);
philpem@40 860
philpem@40 861 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 862 // ROM access
philpem@40 863 handled = true;
philpem@40 864 } else if (address <= (state.ram_size - 1)) {
philpem@40 865 // RAM access
philpem@40 866 WR16(state.ram, mapAddr(address, false), state.ram_size - 1, value);
philpem@40 867 handled = true;
philpem@40 868 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 869 // I/O register space, zone A
philpem@40 870 switch (address & 0x0F0000) {
philpem@40 871 case 0x000000: // Map RAM access
philpem@40 872 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 873 WR16(state.map, address, 0x7FF, value);
philpem@40 874 handled = true;
philpem@40 875 break;
philpem@40 876 case 0x010000: // General Status Register (read only)
philpem@40 877 handled = true;
philpem@40 878 break;
philpem@40 879 case 0x020000: // Video RAM
philpem@40 880 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 881 WR16(state.vram, address, 0x7FFF, value);
philpem@40 882 handled = true;
philpem@40 883 break;
philpem@40 884 case 0x030000: // Bus Status Register 0 (read only)
philpem@40 885 handled = true;
philpem@40 886 break;
philpem@40 887 case 0x040000: // Bus Status Register 1 (read only)
philpem@40 888 handled = true;
philpem@40 889 break;
philpem@40 890 case 0x050000: // Phone status
philpem@40 891 break;
philpem@40 892 case 0x060000: // DMA Count
philpem@40 893 break;
philpem@40 894 case 0x070000: // Line Printer Status Register
philpem@40 895 break;
philpem@40 896 case 0x080000: // Real Time Clock
philpem@40 897 break;
philpem@40 898 case 0x090000: // Phone registers
philpem@40 899 switch (address & 0x0FF000) {
philpem@40 900 case 0x090000: // Handset relay
philpem@40 901 case 0x098000:
philpem@40 902 break;
philpem@40 903 case 0x091000: // Line select 2
philpem@40 904 case 0x099000:
philpem@40 905 break;
philpem@40 906 case 0x092000: // Hook relay 1
philpem@40 907 case 0x09A000:
philpem@40 908 break;
philpem@40 909 case 0x093000: // Hook relay 2
philpem@40 910 case 0x09B000:
philpem@40 911 break;
philpem@40 912 case 0x094000: // Line 1 hold
philpem@40 913 case 0x09C000:
philpem@40 914 break;
philpem@40 915 case 0x095000: // Line 2 hold
philpem@40 916 case 0x09D000:
philpem@40 917 break;
philpem@40 918 case 0x096000: // Line 1 A-lead
philpem@40 919 case 0x09E000:
philpem@40 920 break;
philpem@40 921 case 0x097000: // Line 2 A-lead
philpem@40 922 case 0x09F000:
philpem@40 923 break;
philpem@40 924 }
philpem@40 925 break;
philpem@40 926 case 0x0A0000: // Miscellaneous Control Register
philpem@40 927 break;
philpem@40 928 case 0x0B0000: // TM/DIALWR
philpem@40 929 break;
philpem@43 930 case 0x0C0000: // Clear Status Register
philpem@43 931 state.genstat = 0xFFFF;
philpem@43 932 state.bsr0 = 0xFFFF;
philpem@43 933 state.bsr1 = 0xFFFF;
philpem@43 934 handled = true;
philpem@40 935 break;
philpem@40 936 case 0x0D0000: // DMA Address Register
philpem@40 937 break;
philpem@40 938 case 0x0E0000: // Disk Control Register
philpem@40 939 break;
philpem@40 940 case 0x0F0000: // Line Printer Data Register
philpem@40 941 break;
philpem@40 942 }
philpem@40 943 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 944 // I/O register space, zone B
philpem@40 945 switch (address & 0xF00000) {
philpem@40 946 case 0xC00000: // Expansion slots
philpem@40 947 case 0xD00000:
philpem@40 948 switch (address & 0xFC0000) {
philpem@40 949 case 0xC00000: // Expansion slot 0
philpem@40 950 case 0xC40000: // Expansion slot 1
philpem@40 951 case 0xC80000: // Expansion slot 2
philpem@40 952 case 0xCC0000: // Expansion slot 3
philpem@40 953 case 0xD00000: // Expansion slot 4
philpem@40 954 case 0xD40000: // Expansion slot 5
philpem@40 955 case 0xD80000: // Expansion slot 6
philpem@40 956 case 0xDC0000: // Expansion slot 7
philpem@40 957 fprintf(stderr, "NOTE: WR16 to expansion card space, addr=0x%08X, data=0x%04X\n", address, value);
philpem@40 958 break;
philpem@40 959 }
philpem@40 960 break;
philpem@40 961 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 962 case 0xF00000:
philpem@40 963 switch (address & 0x070000) {
philpem@40 964 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@40 965 break;
philpem@40 966 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@40 967 break;
philpem@40 968 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 969 break;
philpem@40 970 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 971 break;
philpem@40 972 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 973 switch (address & 0x077000) {
philpem@40 974 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@40 975 break;
philpem@44 976 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@44 977 state.pie = ((value & 0x8000) == 0x8000);
philpem@44 978 handled = true;
philpem@40 979 break;
philpem@40 980 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 981 break;
philpem@40 982 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@40 983 state.romlmap = ((value & 0x8000) == 0x8000);
philpem@40 984 handled = true;
philpem@40 985 break;
philpem@40 986 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@40 987 break;
philpem@40 988 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@40 989 break;
philpem@40 990 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@40 991 break;
philpem@40 992 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@40 993 break;
philpem@40 994 }
philpem@40 995 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 996 break;
philpem@40 997 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 998 switch (address & 0x07F000) {
philpem@40 999 default:
philpem@40 1000 break;
philpem@40 1001 }
philpem@40 1002 break;
philpem@40 1003 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@40 1004 break;
philpem@40 1005 }
philpem@40 1006 }
philpem@40 1007 }
philpem@40 1008
philpem@40 1009 LOG_NOT_HANDLED_W(16);
philpem@40 1010 }
philpem@40 1011
philpem@40 1012 /**
philpem@40 1013 * @brief Write M68K memory, 8-bit
philpem@40 1014 */
philpem@40 1015 void m68k_write_memory_8(uint32_t address, uint32_t value)
philpem@40 1016 {
philpem@40 1017 bool handled = false;
philpem@40 1018
philpem@40 1019 // If ROMLMAP is set, force system to access ROM
philpem@40 1020 if (!state.romlmap)
philpem@40 1021 address |= 0x800000;
philpem@40 1022
philpem@40 1023 // Check access permissions
philpem@40 1024 ACCESS_CHECK_WR(address, 8);
philpem@40 1025
philpem@40 1026 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
philpem@40 1027 // ROM access (read only!)
philpem@40 1028 handled = true;
philpem@40 1029 } else if (address <= (state.ram_size - 1)) {
philpem@40 1030 // RAM access
philpem@40 1031 WR8(state.ram, mapAddr(address, false), state.ram_size - 1, value);
philpem@40 1032 handled = true;
philpem@40 1033 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
philpem@40 1034 // I/O register space, zone A
philpem@40 1035 switch (address & 0x0F0000) {
philpem@40 1036 case 0x000000: // Map RAM access
philpem@40 1037 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=%08X, data=%02X\n", address, value);
philpem@40 1038 WR8(state.map, address, 0x7FF, value);
philpem@40 1039 handled = true;
philpem@40 1040 break;
philpem@40 1041 case 0x010000: // General Status Register
philpem@40 1042 handled = true;
philpem@40 1043 break;
philpem@40 1044 case 0x020000: // Video RAM
philpem@40 1045 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=%08X\n, data=0x%02X", address, value);
philpem@40 1046 WR8(state.vram, address, 0x7FFF, value);
philpem@40 1047 handled = true;
philpem@40 1048 break;
philpem@40 1049 case 0x030000: // Bus Status Register 0
philpem@40 1050 handled = true;
philpem@40 1051 break;
philpem@40 1052 case 0x040000: // Bus Status Register 1
philpem@40 1053 handled = true;
philpem@40 1054 break;
philpem@40 1055 case 0x050000: // Phone status
philpem@40 1056 break;
philpem@40 1057 case 0x060000: // DMA Count
philpem@40 1058 break;
philpem@40 1059 case 0x070000: // Line Printer Status Register
philpem@40 1060 break;
philpem@40 1061 case 0x080000: // Real Time Clock
philpem@40 1062 break;
philpem@40 1063 case 0x090000: // Phone registers
philpem@40 1064 switch (address & 0x0FF000) {
philpem@40 1065 case 0x090000: // Handset relay
philpem@40 1066 case 0x098000:
philpem@40 1067 break;
philpem@40 1068 case 0x091000: // Line select 2
philpem@40 1069 case 0x099000:
philpem@40 1070 break;
philpem@40 1071 case 0x092000: // Hook relay 1
philpem@40 1072 case 0x09A000:
philpem@40 1073 break;
philpem@40 1074 case 0x093000: // Hook relay 2
philpem@40 1075 case 0x09B000:
philpem@40 1076 break;
philpem@40 1077 case 0x094000: // Line 1 hold
philpem@40 1078 case 0x09C000:
philpem@40 1079 break;
philpem@40 1080 case 0x095000: // Line 2 hold
philpem@40 1081 case 0x09D000:
philpem@40 1082 break;
philpem@40 1083 case 0x096000: // Line 1 A-lead
philpem@40 1084 case 0x09E000:
philpem@40 1085 break;
philpem@40 1086 case 0x097000: // Line 2 A-lead
philpem@40 1087 case 0x09F000:
philpem@40 1088 break;
philpem@40 1089 }
philpem@40 1090 break;
philpem@40 1091 case 0x0A0000: // Miscellaneous Control Register
philpem@40 1092 break;
philpem@40 1093 case 0x0B0000: // TM/DIALWR
philpem@40 1094 break;
philpem@43 1095 case 0x0C0000: // Clear Status Register
philpem@43 1096 state.genstat = 0xFFFF;
philpem@43 1097 state.bsr0 = 0xFFFF;
philpem@43 1098 state.bsr1 = 0xFFFF;
philpem@43 1099 handled = true;
philpem@40 1100 break;
philpem@40 1101 case 0x0D0000: // DMA Address Register
philpem@40 1102 break;
philpem@40 1103 case 0x0E0000: // Disk Control Register
philpem@40 1104 break;
philpem@40 1105 case 0x0F0000: // Line Printer Data Register
philpem@40 1106 break;
philpem@40 1107 }
philpem@40 1108 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
philpem@40 1109 // I/O register space, zone B
philpem@40 1110 switch (address & 0xF00000) {
philpem@40 1111 case 0xC00000: // Expansion slots
philpem@40 1112 case 0xD00000:
philpem@40 1113 switch (address & 0xFC0000) {
philpem@40 1114 case 0xC00000: // Expansion slot 0
philpem@40 1115 case 0xC40000: // Expansion slot 1
philpem@40 1116 case 0xC80000: // Expansion slot 2
philpem@40 1117 case 0xCC0000: // Expansion slot 3
philpem@40 1118 case 0xD00000: // Expansion slot 4
philpem@40 1119 case 0xD40000: // Expansion slot 5
philpem@40 1120 case 0xD80000: // Expansion slot 6
philpem@40 1121 case 0xDC0000: // Expansion slot 7
philpem@40 1122 fprintf(stderr, "NOTE: WR8 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
philpem@40 1123 break;
philpem@40 1124 }
philpem@40 1125 break;
philpem@40 1126 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
philpem@40 1127 case 0xF00000:
philpem@40 1128 switch (address & 0x070000) {
philpem@40 1129 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
philpem@40 1130 break;
philpem@40 1131 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
philpem@40 1132 break;
philpem@40 1133 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
philpem@40 1134 break;
philpem@40 1135 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
philpem@40 1136 break;
philpem@40 1137 case 0x040000: // [ef][4c]xxxx ==> General Control Register
philpem@40 1138 switch (address & 0x077000) {
philpem@40 1139 case 0x040000: // [ef][4c][08]xxx ==> EE
philpem@40 1140 break;
philpem@44 1141 case 0x041000: // [ef][4c][19]xxx ==> PIE
philpem@44 1142 if ((address & 1) == 0)
philpem@44 1143 state.pie = ((value & 0x80) == 0x80);
philpem@44 1144 handled = true;
philpem@40 1145 break;
philpem@40 1146 case 0x042000: // [ef][4c][2A]xxx ==> BP
philpem@40 1147 break;
philpem@40 1148 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
philpem@40 1149 if ((address & 1) == 0)
philpem@40 1150 state.romlmap = ((value & 0x80) == 0x80);
philpem@40 1151 handled = true;
philpem@40 1152 break;
philpem@40 1153 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
philpem@40 1154 break;
philpem@40 1155 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
philpem@40 1156 break;
philpem@40 1157 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
philpem@40 1158 break;
philpem@40 1159 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
philpem@40 1160 break;
philpem@40 1161 }
philpem@40 1162 case 0x050000: // [ef][5d]xxxx ==> 8274
philpem@40 1163 break;
philpem@40 1164 case 0x060000: // [ef][6e]xxxx ==> Control regs
philpem@40 1165 switch (address & 0x07F000) {
philpem@40 1166 default:
philpem@40 1167 break;
philpem@40 1168 }
philpem@40 1169 break;
philpem@40 1170 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
philpem@40 1171 break;
philpem@40 1172 default:
philpem@40 1173 fprintf(stderr, "NOTE: WR8 to undefined E/F-block space, addr=0x%08X, data=0x%08X\n", address, value);
philpem@40 1174 break;
philpem@40 1175 }
philpem@40 1176 }
philpem@40 1177 }
philpem@40 1178
philpem@40 1179 LOG_NOT_HANDLED_W(8);
philpem@40 1180 }
philpem@40 1181
philpem@40 1182
philpem@40 1183 // for the disassembler
philpem@40 1184 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
philpem@40 1185 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
philpem@40 1186 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }
philpem@40 1187
philpem@40 1188