src/memory.c

changeset 116
21521e62007f
parent 114
36367ebd34e0
child 117
73caf968b67b
     1.1 --- a/src/memory.c	Sat Nov 17 22:15:23 2012 +0000
     1.2 +++ b/src/memory.c	Sat Nov 17 22:26:53 2012 +0000
     1.3 @@ -472,7 +472,9 @@
     1.4  						handled = true;
     1.5  						break;
     1.6  					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
     1.7 -						/*TODO: implement P5.1 second hard drive select*/
     1.8 +						// MCR2 - UNIX PC Rev. P5.1 HDD head select b3 and potential HDD#2 select
     1.9 +						wd2010_write_reg(&state.hdc_ctx, UNIXPC_REG_MCR2, data);
    1.10 +						handled = true;
    1.11  						break;
    1.12  					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
    1.13  						break;
    1.14 @@ -546,8 +548,14 @@
    1.15  		// I/O register space, zone A
    1.16  		switch (address & 0x0F0000) {
    1.17  			case 0x010000:				// General Status Register
    1.18 -				ENFORCE_SIZE_R(bits, address, 16, "GENSTAT");
    1.19 -				return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
    1.20 +				/* ENFORCE_SIZE_R(bits, address, 16, "GENSTAT"); */
    1.21 +				if (bits == 32) {
    1.22 +					return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
    1.23 +				} else if (bits == 16) {
    1.24 +					return (uint16_t)state.genstat;
    1.25 +				} else {
    1.26 +					return (uint8_t)(state.genstat & 0xff);
    1.27 +				}
    1.28  				break;
    1.29  			case 0x030000:				// Bus Status Register 0
    1.30  				ENFORCE_SIZE_R(bits, address, 16, "BSR0");