src/memory.c

branch
experimental_memory_mapper_v2
changeset 128
3246b74d96bc
parent 121
15ae2788e848
child 132
8a7dc9b5b1db
     1.1 --- a/src/memory.c	Wed Jan 16 00:41:51 2013 +0000
     1.2 +++ b/src/memory.c	Fri Jan 18 17:03:48 2013 +0000
     1.3 @@ -17,100 +17,10 @@
     1.4   * Memory mapping
     1.5   ******************/
     1.6  
     1.7 -#define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
     1.8 -
     1.9 -uint32_t mapAddr(uint32_t addr, bool writing)/*{{{*/
    1.10 -{
    1.11 -	if (addr < 0x400000) {
    1.12 -		// RAM access. Check against the Map RAM
    1.13 -		// Start by getting the original page address
    1.14 -		uint16_t page = (addr >> 12) & 0x3FF;
    1.15 -
    1.16 -		// Look it up in the map RAM and get the physical page address
    1.17 -		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
    1.18 -
    1.19 -		// Update the Page Status bits
    1.20 -		uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
    1.21 -		// Pagebits --
    1.22 -		//   0 = not present
    1.23 -		//   1 = present but not accessed
    1.24 -		//   2 = present, accessed (read from)
    1.25 -		//   3 = present, dirty (written to)
    1.26 -		switch (pagebits) {
    1.27 -			case 0:
    1.28 -				// Page not present
    1.29 -				// This should cause a page fault
    1.30 -				LOGS("Whoa! Pagebit update, when the page is not present!");
    1.31 -				break;
    1.32 -
    1.33 -			case 1:
    1.34 -				// Page present -- first access
    1.35 -				state.map[page*2] &= 0x9F;	// turn off "present" bit (but not write enable!)
    1.36 -				if (writing)
    1.37 -					state.map[page*2] |= 0x60;		// Page written to (dirty)
    1.38 -				else
    1.39 -					state.map[page*2] |= 0x40;		// Page accessed but not written
    1.40 -				break;
    1.41 -
    1.42 -			case 2:
    1.43 -			case 3:
    1.44 -				// Page present, 2nd or later access
    1.45 -				if (writing)
    1.46 -					state.map[page*2] |= 0x60;		// Page written to (dirty)
    1.47 -				break;
    1.48 -		}
    1.49 -
    1.50 -		// Return the address with the new physical page spliced in
    1.51 -		return (new_page_addr << 12) + (addr & 0xFFF);
    1.52 -	} else {
    1.53 -		// I/O, VRAM or MapRAM space; no mapping is performed or required
    1.54 -		// TODO: assert here?
    1.55 -		return addr;
    1.56 -	}
    1.57 -}/*}}}*/
    1.58 -
    1.59 -MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)/*{{{*/
    1.60 -{
    1.61 -	// Get the page bits for this page.
    1.62 -	uint16_t page = (addr >> 12) & 0x3FF;
    1.63 -	uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
    1.64 -
    1.65 -	// Check page is present (but only for RAM zone)
    1.66 -	if ((addr < 0x400000) && ((pagebits & 0x03) == 0)) {
    1.67 -		LOG("Page not mapped in: addr %08X, page %04X, mapbits %04X", addr, page, MAPRAM(page));
    1.68 -		return MEM_PAGEFAULT;
    1.69 -	}
    1.70 -
    1.71 -	// Are we in Supervisor mode?
    1.72 -	if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
    1.73 -		// Yes. We can do anything we like.
    1.74 -		return MEM_ALLOWED;
    1.75 -
    1.76 -	// If we're here, then we must be in User mode.
    1.77 -	// Check that the user didn't access memory outside of the RAM area
    1.78 -	if (addr >= 0x400000) {
    1.79 -		LOGS("User accessed privileged memory");
    1.80 -		return MEM_UIE;
    1.81 -	}
    1.82 -
    1.83 -	// User attempt to access the kernel
    1.84 -	// A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
    1.85 -	if (((addr >> 19) & 0x0F) == 0) {
    1.86 -		LOGS("Attempt by user code to access kernel space");
    1.87 -		return MEM_KERNEL;
    1.88 -	}
    1.89 -
    1.90 -	// Check page is write enabled
    1.91 -	if (writing && ((pagebits & 0x04) == 0)) {
    1.92 -		LOG("Page not write enabled: inaddr %08X, page %04X, mapram %04X [%02X %02X], pagebits %d",
    1.93 -				addr, page, MAPRAM(page), state.map[page*2], state.map[(page*2)+1], pagebits);
    1.94 -		return MEM_PAGE_NO_WE;
    1.95 -	}
    1.96 -
    1.97 -	// Page access allowed.
    1.98 -	return MEM_ALLOWED;
    1.99 -}/*}}}*/
   1.100 -
   1.101 +/// Set a page bit
   1.102 +#define MAP_SET_PAGEBIT(addr, bit) state.map[(((addr) >> 12) & 0x3FF)*2] |=  (bit << 2)
   1.103 +/// Clear a page bit
   1.104 +#define MAP_CLR_PAGEBIT(addr, bit) state.map[(((addr) >> 12) & 0x3FF)*2] &= ~(bit << 2)
   1.105  
   1.106  
   1.107  /********************************************************
   1.108 @@ -129,40 +39,7 @@
   1.109  /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
   1.110  #define ACCESS_CHECK_WR(address, bits)								\
   1.111  	do {															\
   1.112 -		bool fault = false;											\
   1.113 -		MEM_STATUS st;												\
   1.114 -		switch (st = checkMemoryAccess(address, true)) {			\
   1.115 -			case MEM_ALLOWED:										\
   1.116 -				/* Access allowed */								\
   1.117 -				break;												\
   1.118 -			case MEM_PAGEFAULT:										\
   1.119 -				/* Page fault */									\
   1.120 -				state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0);	\
   1.121 -				fault = true;										\
   1.122 -				break;												\
   1.123 -			case MEM_UIE:											\
   1.124 -				/* User access to memory above 4MB */				\
   1.125 -				state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0);	\
   1.126 -				fault = true;										\
   1.127 -				break;												\
   1.128 -			case MEM_KERNEL:										\
   1.129 -			case MEM_PAGE_NO_WE:									\
   1.130 -				/* kernel access or page not write enabled */		\
   1.131 -				/* XXX: is this the correct value? */				\
   1.132 -				state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0);	\
   1.133 -				fault = true;										\
   1.134 -				break;												\
   1.135 -		}															\
   1.136 -																	\
   1.137 -		if (fault) {												\
   1.138 -			if (bits >= 16)											\
   1.139 -				state.bsr0 = 0x7C00;								\
   1.140 -			else													\
   1.141 -				state.bsr0 = (address & 1) ? 0x7E00 : 0x7D00;		\
   1.142 -			state.bsr0 |= (address >> 16);							\
   1.143 -			state.bsr1 = address & 0xffff;							\
   1.144 -			LOG("Bus Error while writing, addr %08X, statcode %d", address, st);		\
   1.145 -			if (state.ee) m68k_pulse_bus_error();					\
   1.146 +		if (access_check_cpu(address, bits, true)) {				\
   1.147  			return;													\
   1.148  		}															\
   1.149  	} while (0)
   1.150 @@ -180,100 +57,220 @@
   1.151  /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
   1.152  #define ACCESS_CHECK_RD(address, bits)								\
   1.153  	do {															\
   1.154 -		bool fault = false;											\
   1.155 -		MEM_STATUS st;												\
   1.156 -		switch (st = checkMemoryAccess(address, false)) {			\
   1.157 -			case MEM_ALLOWED:										\
   1.158 -				/* Access allowed */								\
   1.159 -				break;												\
   1.160 -			case MEM_PAGEFAULT:										\
   1.161 -				/* Page fault */									\
   1.162 -				state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0);	\
   1.163 -				fault = true;										\
   1.164 -				break;												\
   1.165 -			case MEM_UIE:											\
   1.166 -				/* User access to memory above 4MB */				\
   1.167 -				state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0);	\
   1.168 -				fault = true;										\
   1.169 -				break;												\
   1.170 -			case MEM_KERNEL:										\
   1.171 -			case MEM_PAGE_NO_WE:									\
   1.172 -				/* kernel access or page not write enabled */		\
   1.173 -				/* XXX: is this the correct value? */				\
   1.174 -				state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0);	\
   1.175 -				fault = true;										\
   1.176 -				break;												\
   1.177 -		}															\
   1.178 -																	\
   1.179 -		if (fault) {												\
   1.180 -			if (bits >= 16)											\
   1.181 -				state.bsr0 = 0x7C00;								\
   1.182 +		if (access_check_cpu(address, bits, false)) {				\
   1.183 +			if (bits == 32)											\
   1.184 +				return EMPTY & 0xFFFFFFFF;							\
   1.185  			else													\
   1.186 -				state.bsr0 = (address & 1) ? 0x7E00 : 0x7D00;		\
   1.187 -			state.bsr0 |= (address >> 16);							\
   1.188 -			state.bsr1 = address & 0xffff;							\
   1.189 -			LOG("Bus Error while reading, addr %08X, statcode %d", address, st);		\
   1.190 -			if (state.ee) m68k_pulse_bus_error();					\
   1.191 -			if (bits == 32)											\
   1.192 -				return EMPTY & 0xFFFFFFFF;									\
   1.193 -			else													\
   1.194 -				return EMPTY & ((1UL << bits)-1);								\
   1.195 +				return EMPTY & ((1UL << bits)-1);					\
   1.196  		}															\
   1.197  	} while (0)
   1.198  /*}}}*/
   1.199  
   1.200 -bool access_check_dma(int reading)
   1.201 +
   1.202 +/**
   1.203 + * Update the page bits for a given memory address
   1.204 + *
   1.205 + * @param	addr	Memory address being accessed
   1.206 + * @param	l7intr	Set to <i>true</i> if a level-seven interrupt has been
   1.207 + * 					signalled (even if <b>ENABLE ERROR</b> isn't set).
   1.208 + * @param	write	Set to <i>true</i> if the address is being written to.
   1.209 + */
   1.210 +static void update_page_bits(uint32_t addr, bool l7intr, bool write)
   1.211  {
   1.212 -	// Check memory access permissions
   1.213 -	bool access_ok;
   1.214 -	switch (checkMemoryAccess(state.dma_address, !reading)) {
   1.215 -		case MEM_PAGEFAULT:
   1.216 -			// Page fault
   1.217 -			state.genstat = 0xABFF
   1.218 -				| (reading ? 0x4000 : 0)
   1.219 -				| (state.pie ? 0x0400 : 0);
   1.220 -			access_ok = false;
   1.221 -			break;
   1.222 +	bool ps0_state = false;
   1.223 +
   1.224 +	// Don't try and update pagebits for non-RAM addresses
   1.225 +	if (addr > 0x3FFFFF)
   1.226 +		return;
   1.227 +
   1.228 +	if (l7intr) {
   1.229 +//		if (!(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
   1.230 +			// FIXME FUCKUP The ruddy TRM is wrong AGAIN! If above line is uncommented, Really Bad Things Happen.
   1.231 +		if ((MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
   1.232 +			// Level 7 interrupt, PS0 clear, PS1 don't-care. Set PS0.
   1.233 +			ps0_state = true;
   1.234 +		}
   1.235 +	} else {
   1.236 +		// No L7 interrupt
   1.237 +		if ((write && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS1) &&  (MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) ||
   1.238 +			(write &&  (MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)))
   1.239 +		{
   1.240 +			// No L7 interrupt, PS[1:0] = 0b01, write
   1.241 +			// No L7 interrupt, PS[1:0] = 0b10, write
   1.242 +			ps0_state = true;
   1.243 +		}
   1.244 +	}
   1.245  
   1.246 -		case MEM_UIE:
   1.247 -			// User access to memory above 4MB
   1.248 -			// FIXME? Shouldn't be possible with DMA... assert this?
   1.249 -			state.genstat = 0xBAFF
   1.250 -				| (reading ? 0x4000 : 0)
   1.251 -				| (state.pie ? 0x0400 : 0);
   1.252 -			access_ok = false;
   1.253 -			break;
   1.254 +#ifdef MAPRAM_BIT_TEST
   1.255 +	LOG("Starting Mapram Bit Test");
   1.256 +	state.map[0] = state.map[1] = 0;
   1.257 +	LOG("Start   = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   1.258 +	MAP_SET_PAGEBIT(0, PAGE_BIT_WE);
   1.259 +	LOG("Set WE  = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   1.260 +	MAP_SET_PAGEBIT(0, PAGE_BIT_PS1);
   1.261 +	LOG("Set PS1 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   1.262 +	MAP_SET_PAGEBIT(0, PAGE_BIT_PS0);
   1.263 +	LOG("Set PS0 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   1.264 +	
   1.265 +	MAP_CLR_PAGEBIT(0, PAGE_BIT_WE);
   1.266 +	LOG("Clr WE  = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   1.267 +	MAP_CLR_PAGEBIT(0, PAGE_BIT_PS1);
   1.268 +	LOG("Clr PS1 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   1.269 +	MAP_CLR_PAGEBIT(0, PAGE_BIT_PS0);
   1.270 +	LOG("Clr PS0 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   1.271 +	exit(-1);
   1.272 +#endif
   1.273 +
   1.274 +	uint16_t old_pagebits = MAP_PAGEBITS(addr);
   1.275  
   1.276 -		case MEM_KERNEL:
   1.277 -		case MEM_PAGE_NO_WE:
   1.278 -			// Kernel access or page not write enabled
   1.279 -			/* XXX: is this correct? */
   1.280 -			state.genstat = 0xBBFF
   1.281 -				| (reading ? 0x4000 : 0)
   1.282 -				| (state.pie ? 0x0400 : 0);
   1.283 -			access_ok = false;
   1.284 -			break;
   1.285 +	// PS1 is always set on access
   1.286 +	MAP_SET_PAGEBIT(addr, PAGE_BIT_PS1);
   1.287 +
   1.288 +	uint16_t new_pagebit1 = MAP_PAGEBITS(addr);
   1.289 +
   1.290 +	// Update PS0
   1.291 +	if (ps0_state) {
   1.292 +		MAP_SET_PAGEBIT(addr, PAGE_BIT_PS0);
   1.293 +	} else {
   1.294 +		MAP_CLR_PAGEBIT(addr, PAGE_BIT_PS0);
   1.295 +	}
   1.296  
   1.297 -		case MEM_ALLOWED:
   1.298 -			access_ok = true;
   1.299 +	uint16_t new_pagebit2 = MAP_PAGEBITS(addr);
   1.300 +	switch (addr) {
   1.301 +		case 0x000000:
   1.302 +		case 0x001000:
   1.303 +		case 0x002000:
   1.304 +		case 0x003000:
   1.305 +		case 0x004000:
   1.306 +		case 0x033000:
   1.307 +		case 0x034000:
   1.308 +		case 0x035000:
   1.309 +			LOG("Addr %08X MapNew %04X Pagebit update -- ps0 %d, %02X => %02X => %02X", addr, MAPRAM_ADDR(addr), ps0_state, old_pagebits, new_pagebit1, new_pagebit2);
   1.310 +		default:
   1.311  			break;
   1.312  	}
   1.313 -	if (!access_ok) {
   1.314 +}
   1.315 +
   1.316 +bool access_check_dma(void)
   1.317 +{
   1.318 +	// TODO FIXME BUGBUG Sanity check - Make sure DMAC is only accessing RAM addresses
   1.319 +
   1.320 +	// DMA access check -- make sure the page is mapped in
   1.321 +	if (!(MAP_PAGEBITS(state.dma_address) & PAGE_BIT_PS0) && !(MAP_PAGEBITS(state.dma_address) & PAGE_BIT_PS1)) {
   1.322 +		// DMA access to page which is not mapped in.
   1.323 +		// Level 7 interrupt, page fault, DMA invoked
   1.324 +		state.genstat = 0xABFF
   1.325 +			| (state.dma_reading ? 0x4000 : 0)
   1.326 +			| (state.pie ? 0x0400 : 0);
   1.327 +
   1.328 +		// XXX: Check all this stuff.
   1.329  		state.bsr0 = 0x3C00;
   1.330  		state.bsr0 |= (state.dma_address >> 16);
   1.331  		state.bsr1 = state.dma_address & 0xffff;
   1.332 -		if (state.ee) m68k_set_irq(7);
   1.333 -		printf("BUS ERROR FROM DMA: genstat=%04X, bsr0=%04X, bsr1=%04X\n", state.genstat, state.bsr0, state.bsr1);
   1.334 +
   1.335 +		// Update page bits for this transfer
   1.336 +		update_page_bits(state.dma_address, true, !state.dma_reading);
   1.337 +
   1.338 +		// XXX: is this right?
   1.339 +		// Fire a Level 7 interrupt
   1.340 +		/*if (state.ee)*/ m68k_set_irq(7);
   1.341 +
   1.342 +		LOG("BUS ERROR FROM DMA: genstat=%04X, bsr0=%04X, bsr1=%04X\n", state.genstat, state.bsr0, state.bsr1);
   1.343 +		return false;
   1.344 +	} else {
   1.345 +		// No errors. Just update the page bits.
   1.346 +		update_page_bits(state.dma_address, false, !state.dma_reading);
   1.347 +		return true;
   1.348  	}
   1.349 -	return (access_ok);
   1.350 +}
   1.351 +
   1.352 +/**
   1.353 + * Check memory access permissions for a CPU memory access.
   1.354 + *
   1.355 + * @param	addr	Virtual memory address being accessed (from CPU address bus).
   1.356 + * @param	bits	Word size of this transfer (8, 16 or 32 bits).
   1.357 + * @param	write	<i>true</i> if this is a write operation, <i>false</i> if it is a read operation.
   1.358 + * @return	<i>true</i> if the access was denied and a level-7 interrupt and/or bus error raised.
   1.359 + * 			<i>false</i> if the access was allowed.
   1.360 + */
   1.361 +bool access_check_cpu(uint32_t addr, int bits, bool write)
   1.362 +{
   1.363 +	bool supervisor = (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000);
   1.364 +	bool fault = false;
   1.365 +
   1.366 +	// TODO FIXME BUGBUG? Do we need to check for supervisor access here?
   1.367 +	if ((addr >= 0x000000) && (addr <= 0x3FFFFF) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
   1.368 +		// (A) Page Fault -- user access to page which is not mapped in
   1.369 +		// Level 7 Interrupt, Bus Error, regs=PAGEFAULT
   1.370 +		if (write) {
   1.371 +			state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0);
   1.372 +		} else {
   1.373 +			state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0);
   1.374 +		}
   1.375 +		fault = true;
   1.376 +	} else if (!supervisor && (addr >= 0x000000) && (addr <= 0x07FFFF)) {
   1.377 +		// (B) User attempted to access the kernel
   1.378 +		// Level 7 Interrupt, Bus Error, regs=KERNEL
   1.379 +		if (write) {
   1.380 +			// XXX: BUGBUG? Is this correct?
   1.381 +			state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0);
   1.382 +		} else {
   1.383 +			state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0);
   1.384 +		}
   1.385 +		fault = true;
   1.386 +	} else if (!supervisor && write && (addr >= 0x000000) && (addr <= 0x3FFFFF) && !(MAP_PAGEBITS(addr) & PAGE_BIT_WE)) {
   1.387 +		// (C) User attempted to write to a page which is not write enabled
   1.388 +		// Level 7 Interrupt, Bus Error, regs=WRITE_EN
   1.389 +		if (write) {
   1.390 +			// XXX: BUGBUG? Is this correct?
   1.391 +			state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0);
   1.392 +		} else {
   1.393 +			state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0);
   1.394 +		}
   1.395 +		fault = true;
   1.396 +	} else if (!supervisor && (addr >= 0x400000) && (addr <= 0xFFFFFF)) {
   1.397 +		// (D) UIE - user I/O exception
   1.398 +		// Bus Error only, regs=UIE
   1.399 +		if (write) {
   1.400 +			state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0);
   1.401 +		} else {
   1.402 +			state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0);
   1.403 +		}
   1.404 +		fault = true;
   1.405 +	}
   1.406 +
   1.407 +	// Update the page bits first
   1.408 +	update_page_bits(addr, fault, write);
   1.409 +
   1.410 +	if (fault) {
   1.411 +		if (bits >= 16)
   1.412 +			state.bsr0 = 0x7C00;
   1.413 +		else
   1.414 +			state.bsr0 = (addr & 1) ? 0x7E00 : 0x7D00;
   1.415 +		// FIXME? Physical or virtual address here?
   1.416 +		state.bsr0 |= (addr >> 16);
   1.417 +		state.bsr1 = addr & 0xffff;
   1.418 +
   1.419 +		LOG("CPU Bus Error or L7Intr while %s, vaddr %08X, map %08X, pagebits 0x%02X bsr0=%04X bsr1=%04X genstat=%04X", 
   1.420 +				write ? "writing" : "reading", addr,
   1.421 +				MAPRAM_ADDR(addr & 0x3fffff),
   1.422 +				MAP_PAGEBITS(addr & 0x3fffff),
   1.423 +				state.bsr0, state.bsr1, state.genstat);
   1.424 +
   1.425 +		// FIXME? BUGBUG? Does EE disable one or both of these?
   1.426 +		// /*if (state.ee)*/ m68k_set_irq(7);
   1.427 +		/*if (state.ee)*/ m68k_pulse_bus_error();
   1.428 +	}
   1.429 +
   1.430 +	return fault;
   1.431  }
   1.432  
   1.433  // Logging macros
   1.434  #define LOG_NOT_HANDLED_R(bits)															\
   1.435 -	if (!handled) printf("unhandled read%02d, addr=0x%08X\n", bits, address);
   1.436 +	if (!handled) fprintf(stderr, "unhandled read%02d, addr=0x%08X\n", bits, address);
   1.437  
   1.438  #define LOG_NOT_HANDLED_W(bits)															\
   1.439 -	if (!handled) printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
   1.440 +	if (!handled) fprintf(stderr, "unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
   1.441  
   1.442  /********************************************************
   1.443   * I/O read/write functions
   1.444 @@ -286,7 +283,7 @@
   1.445  {
   1.446  	assert((bits == 8) || (bits == 16) || (bits == 32));
   1.447  	if ((bits & allowed) == 0) {
   1.448 -		printf("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
   1.449 +		LOG("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
   1.450  	}
   1.451  }
   1.452  
   1.453 @@ -349,6 +346,7 @@
   1.454  			case 0x070000:				// Line Printer Status Register
   1.455  				break;
   1.456  			case 0x080000:				// Real Time Clock
   1.457 +				LOGS("REAL TIME CLOCK WRITE");
   1.458  				break;
   1.459  			case 0x090000:				// Phone registers
   1.460  				switch (address & 0x0FF000) {
   1.461 @@ -483,6 +481,7 @@
   1.462  						handled = true;
   1.463  						break;
   1.464  					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   1.465 +						LOGS("REAL TIME CLOCK DATA WRITE");
   1.466  						break;
   1.467  					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   1.468  						switch (address & 0x077000) {
   1.469 @@ -529,11 +528,15 @@
   1.470  						// TODO: figure out which sizes are valid (probably just 8 and 16)
   1.471  						// ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER");
   1.472  						if (bits == 8) {
   1.473 -							printf("KBD WR %02X => %02X\n", (address >> 1) & 3, data);
   1.474 +#ifdef LOG_KEYBOARD_WRITES
   1.475 +							LOG("KBD WR %02X => %02X\n", (address >> 1) & 3, data);
   1.476 +#endif
   1.477  							keyboard_write(&state.kbd, (address >> 1) & 3, data);
   1.478  							handled = true;
   1.479  						} else if (bits == 16) {
   1.480 -							printf("KBD WR %02X => %04X\n", (address >> 1) & 3, data);
   1.481 +#ifdef LOG_KEYBOARD_WRITES
   1.482 +							LOG("KBD WR %02X => %04X\n", (address >> 1) & 3, data);
   1.483 +#endif
   1.484  							keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8);
   1.485  							handled = true;
   1.486  						}
   1.487 @@ -587,7 +590,7 @@
   1.488  				return data;
   1.489  				break;
   1.490  			case 0x080000:				// Real Time Clock
   1.491 -				printf("READ NOTIMP: Realtime Clock\n");
   1.492 +				LOGS("REAL TIME CLOCK READ");
   1.493  				break;
   1.494  			case 0x090000:				// Phone registers
   1.495  				switch (address & 0x0FF000) {
   1.496 @@ -665,6 +668,7 @@
   1.497  					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   1.498  						break;
   1.499  					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   1.500 +						LOGS("REAL TIME CLOCK DATA READ");
   1.501  						break;
   1.502  					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   1.503  						switch (address & 0x077000) {
   1.504 @@ -735,7 +739,8 @@
   1.505  		return RD32(state.rom, address, ROM_SIZE - 1);
   1.506  	} else if (address <= 0x3fffff) {
   1.507  		// RAM access
   1.508 -		uint32_t newAddr = mapAddr(address, false);
   1.509 +		uint32_t newAddr = MAP_ADDR(address);
   1.510 +
   1.511  		if (newAddr <= 0x1fffff) {
   1.512  			if (newAddr >= state.base_ram_size)
   1.513  				return EMPTY & 0xffffffff;
   1.514 @@ -787,7 +792,8 @@
   1.515  		data = RD16(state.rom, address, ROM_SIZE - 1);
   1.516  	} else if (address <= 0x3fffff) {
   1.517  		// RAM access
   1.518 -		uint32_t newAddr = mapAddr(address, false);
   1.519 +		uint32_t newAddr = MAP_ADDR(address);
   1.520 +
   1.521  		if (newAddr <= 0x1fffff) {
   1.522  			if (newAddr >= state.base_ram_size)
   1.523  				return EMPTY & 0xffff;
   1.524 @@ -839,7 +845,8 @@
   1.525  		data = RD8(state.rom, address, ROM_SIZE - 1);
   1.526  	} else if (address <= 0x3fffff) {
   1.527  		// RAM access
   1.528 -		uint32_t newAddr = mapAddr(address, false);
   1.529 +		uint32_t newAddr = MAP_ADDR(address);
   1.530 +
   1.531  		if (newAddr <= 0x1fffff) {
   1.532  			if (newAddr >= state.base_ram_size)
   1.533  				return EMPTY & 0xff;
   1.534 @@ -888,7 +895,8 @@
   1.535  		// ROM access
   1.536  	} else if (address <= 0x3FFFFF) {
   1.537  		// RAM access
   1.538 -		uint32_t newAddr = mapAddr(address, true);
   1.539 +		uint32_t newAddr = MAP_ADDR(address);
   1.540 +
   1.541  		if (newAddr <= 0x1fffff) {
   1.542  			if (newAddr < state.base_ram_size) {
   1.543  				WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
   1.544 @@ -933,7 +941,7 @@
   1.545  		// ROM access
   1.546  	} else if (address <= 0x3FFFFF) {
   1.547  		// RAM access
   1.548 -		uint32_t newAddr = mapAddr(address, true);
   1.549 +		uint32_t newAddr = MAP_ADDR(address);
   1.550  
   1.551  		if (newAddr <= 0x1fffff) {
   1.552  			if (newAddr < state.base_ram_size) {
   1.553 @@ -979,7 +987,8 @@
   1.554  		// ROM access (read only!)
   1.555  	} else if (address <= 0x3FFFFF) {
   1.556  		// RAM access
   1.557 -		uint32_t newAddr = mapAddr(address, true);
   1.558 +		uint32_t newAddr = MAP_ADDR(address);
   1.559 +
   1.560  		if (newAddr <= 0x1fffff) {
   1.561  			if (newAddr < state.base_ram_size) {
   1.562  				WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
   1.563 @@ -1013,6 +1022,7 @@
   1.564  uint32_t m68k_read_disassembler_32(uint32_t addr)
   1.565  {
   1.566  	if (addr < 0x400000) {
   1.567 +		// XXX FIXME BUGBUG update this to use the new mapper macros!
   1.568  		uint16_t page = (addr >> 12) & 0x3FF;
   1.569  		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
   1.570  		uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
   1.571 @@ -1028,7 +1038,7 @@
   1.572  				return EMPTY;
   1.573  		}
   1.574  	} else {
   1.575 -		printf(">>> WARNING Disassembler RD32 out of range 0x%08X\n", addr);
   1.576 +		LOG("WARNING: Disassembler RD32 out of range 0x%08X\n", addr);
   1.577  		return EMPTY;
   1.578  	}
   1.579  }
   1.580 @@ -1051,7 +1061,7 @@
   1.581  				return EMPTY & 0xffff;
   1.582  		}
   1.583  	} else {
   1.584 -		printf(">>> WARNING Disassembler RD16 out of range 0x%08X\n", addr);
   1.585 +		LOG("WARNING: Disassembler RD16 out of range 0x%08X\n", addr);
   1.586  		return EMPTY & 0xffff;
   1.587  	}
   1.588  }
   1.589 @@ -1074,7 +1084,7 @@
   1.590  				return EMPTY & 0xff;
   1.591  		}
   1.592  	} else {
   1.593 -		printf(">>> WARNING Disassembler RD8 out of range 0x%08X\n", addr);
   1.594 +		LOG("WARNING: Disassembler RD8 out of range 0x%08X\n", addr);
   1.595  		return EMPTY & 0xff;
   1.596  	}
   1.597  }