src/memory.c

branch
experimental_memory_mapper_v2
changeset 144
609707511166
parent 141
8460d432606f
     1.1 --- a/src/memory.c	Fri Apr 12 12:37:34 2013 +0100
     1.2 +++ b/src/memory.c	Fri Apr 12 16:26:25 2013 +0100
     1.3 @@ -88,7 +88,7 @@
     1.4  //		if (!(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
     1.5  			// FIXME FUCKUP The ruddy TRM is wrong AGAIN! If above line is uncommented, Really Bad Things Happen.
     1.6  		if ((MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
     1.7 -			// Level 7 interrupt, PS0 clear, PS1 don't-care. Set PS0.
     1.8 +			// Level 7 interrupt, PS0 set, PS1 don't-care. Set PS0.
     1.9  			ps0_state = true;
    1.10  		}
    1.11  	} else {
    1.12 @@ -123,22 +123,16 @@
    1.13  	exit(-1);
    1.14  #endif
    1.15  
    1.16 -#ifdef MAPRAM_DEBUG_MESSAGES
    1.17 -	uint16_t old_pagebits = MAP_PAGEBITS(addr);
    1.18 -#endif
    1.19 -
    1.20 -	// PS1 is always set on access
    1.21 -	MAP_SET_PAGEBIT(addr, PAGE_BIT_PS1);
    1.22 +	if (!l7intr) {
    1.23 +		// PS1 is always set on access if no fault
    1.24 +		MAP_SET_PAGEBIT(addr, PAGE_BIT_PS1);
    1.25  
    1.26 -#ifdef MAPRAM_DEBUG_MESSAGES
    1.27 -	uint16_t new_pagebit1 = MAP_PAGEBITS(addr);
    1.28 -#endif
    1.29 -
    1.30 -	// Update PS0
    1.31 -	if (ps0_state) {
    1.32 -		MAP_SET_PAGEBIT(addr, PAGE_BIT_PS0);
    1.33 -	} else {
    1.34 -		MAP_CLR_PAGEBIT(addr, PAGE_BIT_PS0);
    1.35 +		// Update PS0
    1.36 +		if (ps0_state) {
    1.37 +			MAP_SET_PAGEBIT(addr, PAGE_BIT_PS0);
    1.38 +		} else {
    1.39 +			MAP_CLR_PAGEBIT(addr, PAGE_BIT_PS0);
    1.40 +		}
    1.41  	}
    1.42  
    1.43  #ifdef MAPRAM_DEBUG_MESSAGES
    1.44 @@ -259,6 +253,8 @@
    1.45  		fault = true;
    1.46  	}
    1.47  
    1.48 +	unsigned char pagebits_preup = MAP_PAGEBITS(addr & 0x3fffff);
    1.49 +
    1.50  	// Update the page bits first
    1.51  	update_page_bits(addr, fault, write);
    1.52  
    1.53 @@ -271,9 +267,10 @@
    1.54  		state.bsr0 |= (addr >> 16);
    1.55  		state.bsr1 = addr & 0xffff;
    1.56  
    1.57 -		LOG("CPU Bus Error or L7Intr while %s, vaddr %08X, map %08X, pagebits 0x%02X bsr0=%04X bsr1=%04X genstat=%04X", 
    1.58 +		LOG("CPU Bus Error or L7Intr while %s, vaddr %08X, map %08X, pagebits 0x%02X=>0x%02X bsr0=%04X bsr1=%04X genstat=%04X", 
    1.59  				write ? "writing" : "reading", addr,
    1.60  				MAPRAM_ADDR(addr & 0x3fffff),
    1.61 +				pagebits_preup,
    1.62  				MAP_PAGEBITS(addr & 0x3fffff),
    1.63  				state.bsr0, state.bsr1, state.genstat);
    1.64