1.1 --- a/src/wd279x.c Wed Dec 29 01:38:54 2010 +0000 1.2 +++ b/src/wd279x.c Wed Dec 29 09:04:43 2010 +0000 1.3 @@ -37,19 +37,20 @@ 1.4 ctx->track = ctx->head = ctx->sector = 0; 1.5 1.6 // no IRQ pending 1.7 - ctx->irql = ctx->irqe = false; 1.8 + ctx->irq = false; 1.9 1.10 // no data available 1.11 ctx->data_pos = ctx->data_len = 0; 1.12 ctx->data = NULL; 1.13 1.14 - // Status register clear, not busy 1.15 + // Status register clear, not busy; type1 command 1.16 ctx->status = 0; 1.17 + ctx->cmd_has_drq = false; 1.18 1.19 // Clear data register 1.20 ctx->data_reg = 0; 1.21 1.22 - // Last step direction 1.23 + // Last step direction = "towards zero" 1.24 ctx->last_step_dir = -1; 1.25 1.26 // No disc image loaded 1.27 @@ -64,7 +65,7 @@ 1.28 ctx->track = ctx->head = ctx->sector = 0; 1.29 1.30 // no IRQ pending 1.31 - ctx->irql = ctx->irqe = false; 1.32 + ctx->irq = false; 1.33 1.34 // no data available 1.35 ctx->data_pos = ctx->data_len = 0; 1.36 @@ -95,13 +96,7 @@ 1.37 1.38 bool wd2797_get_irq(WD2797_CTX *ctx) 1.39 { 1.40 - // If an IRQ is pending, clear it and return true, otherwise return false 1.41 - if (ctx->irqe) { 1.42 - ctx->irqe = false; 1.43 - return true; 1.44 - } else { 1.45 - return false; 1.46 - } 1.47 + return ctx->irq; 1.48 } 1.49 1.50 1.51 @@ -169,8 +164,7 @@ 1.52 switch (addr & 0x03) { 1.53 case WD2797_REG_STATUS: // Status register 1.54 // Read from status register clears IRQ 1.55 - ctx->irql = false; 1.56 - ctx->irqe = false; 1.57 + ctx->irq = false; 1.58 1.59 // Get current status flags (set by last command) 1.60 // DRQ bit 1.61 @@ -197,9 +191,8 @@ 1.62 if (ctx->data_pos < ctx->data_len) { 1.63 // set IRQ if this is the last data byte 1.64 if (ctx->data_pos == (ctx->data_len-1)) { 1.65 - // Set IRQ only if IRQL has been cleared (no pending IRQs) 1.66 - ctx->irqe = ctx->irql ? ctx->irqe : true; 1.67 - ctx->irql = true; 1.68 + // Set IRQ 1.69 + ctx->irq = true; 1.70 } 1.71 // return data byte and increment pointer 1.72 return ctx->data[ctx->data_pos++]; 1.73 @@ -228,7 +221,7 @@ 1.74 switch (addr) { 1.75 case WD2797_REG_COMMAND: // Command register 1.76 // write to command register clears interrupt request 1.77 - ctx->irql = false; 1.78 + ctx->irq = false; 1.79 1.80 // Is the drive ready? 1.81 if (ctx->disc_image == NULL) { 1.82 @@ -319,9 +312,8 @@ 1.83 // S0 = Busy. We just exec'd the command, thus we're not busy. 1.84 // TODO: Set a timer for seeks, and ONLY clear BUSY when that timer expires. Need periodics for that. 1.85 1.86 - // Set IRQ only if IRQL has been cleared (no pending IRQs) 1.87 - ctx->irqe = ctx->irql ? ctx->irqe : true; 1.88 - ctx->irql = true; 1.89 + // Set IRQ 1.90 + ctx->irq = true; 1.91 return; 1.92 } 1.93 1.94 @@ -344,9 +336,8 @@ 1.95 // Set Write Protect bit and bail. 1.96 ctx->status = 0x40; 1.97 1.98 - // Set IRQ only if IRQL has been cleared (no pending IRQs) 1.99 - ctx->irqe = ctx->irql ? ctx->irqe : true; 1.100 - ctx->irql = true; 1.101 + // Set IRQ 1.102 + ctx->irq = true; 1.103 1.104 return; 1.105 } 1.106 @@ -398,9 +389,8 @@ 1.107 // CHS parameters exceed limits 1.108 ctx->status = 0x10; // Record Not Found 1.109 break; 1.110 - // Set IRQ only if IRQL has been cleared (no pending IRQs) 1.111 - ctx->irqe = ctx->irql ? ctx->irqe : true; 1.112 - ctx->irql = true; 1.113 + // Set IRQ 1.114 + ctx->irq = true; 1.115 } 1.116 1.117 // reset data pointers 1.118 @@ -485,9 +475,8 @@ 1.119 // TODO! 1.120 ctx->status = 0; 1.121 ctx->data_pos = ctx->data_len = 0; 1.122 - // Set IRQ only if IRQL has been cleared (no pending IRQs) 1.123 - ctx->irqe = ctx->irql ? ctx->irqe : true; 1.124 - ctx->irql = true; 1.125 + // Set IRQ 1.126 + ctx->irq = true; 1.127 break; 1.128 } 1.129 break; 1.130 @@ -509,9 +498,8 @@ 1.131 if (ctx->data_pos < ctx->data_len) { 1.132 // set IRQ if this is the last data byte 1.133 if (ctx->data_pos == (ctx->data_len-1)) { 1.134 - // Set IRQ only if IRQL has been cleared (no pending IRQs) 1.135 - ctx->irqe = ctx->irql ? ctx->irqe : true; 1.136 - ctx->irql = true; 1.137 + // Set IRQ 1.138 + ctx->irq = true; 1.139 } 1.140 1.141 // store data byte and increment pointer