Thu, 10 Feb 2011 01:08:32 +0000
properly handle 8 and 16 bit KBC writes
1 #include <stdio.h>
2 #include <stdlib.h>
3 #include <stdint.h>
4 #include <stdbool.h>
5 #include <assert.h>
6 #include "musashi/m68k.h"
7 #include "state.h"
8 #include "memory.h"
10 /******************
11 * Memory mapping
12 ******************/
14 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
16 uint32_t mapAddr(uint32_t addr, bool writing)/*{{{*/
17 {
18 if (addr < 0x400000) {
19 // RAM access. Check against the Map RAM
20 // Start by getting the original page address
21 uint16_t page = (addr >> 12) & 0x3FF;
23 // Look it up in the map RAM and get the physical page address
24 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
26 // Update the Page Status bits
27 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
28 if (pagebits != 0) {
29 if (writing)
30 state.map[page*2] |= 0x60; // Page written to (dirty)
31 else
32 state.map[page*2] |= 0x40; // Page accessed but not written
33 }
35 // Return the address with the new physical page spliced in
36 return (new_page_addr << 12) + (addr & 0xFFF);
37 } else {
38 // I/O, VRAM or MapRAM space; no mapping is performed or required
39 // TODO: assert here?
40 return addr;
41 }
42 }/*}}}*/
44 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)/*{{{*/
45 {
46 // Are we in Supervisor mode?
47 if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
48 // Yes. We can do anything we like.
49 return MEM_ALLOWED;
51 // If we're here, then we must be in User mode.
52 // Check that the user didn't access memory outside of the RAM area
53 if (addr >= 0x400000)
54 return MEM_UIE;
56 // This leaves us with Page Fault checking. Get the page bits for this page.
57 uint16_t page = (addr >> 12) & 0x3FF;
58 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
60 // Check page is present
61 if ((pagebits & 0x03) == 0)
62 return MEM_PAGEFAULT;
64 // User attempt to access the kernel
65 // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
66 if (((addr >> 19) & 0x0F) == 0)
67 return MEM_KERNEL;
69 // Check page is write enabled
70 if (writing && ((pagebits & 0x04) == 0))
71 return MEM_PAGE_NO_WE;
73 // Page access allowed.
74 return MEM_ALLOWED;
75 }/*}}}*/
77 #undef MAPRAM
80 /********************************************************
81 * m68k memory read/write support functions for Musashi
82 ********************************************************/
84 /**
85 * @brief Check memory access permissions for a write operation.
86 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
87 * gcc throws warnings when you have a return-with-value in a void
88 * function, even if the return-with-value is completely unreachable.
89 * Similarly it doesn't like it if you have a return without a value
90 * in a non-void function, even if it's impossible to ever reach the
91 * return-with-no-value. UGH!
92 */
93 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
94 #define ACCESS_CHECK_WR(address, bits) \
95 do { \
96 bool fault = false; \
97 /* MEM_STATUS st; */ \
98 switch (checkMemoryAccess(address, true)) { \
99 case MEM_ALLOWED: \
100 /* Access allowed */ \
101 break; \
102 case MEM_PAGEFAULT: \
103 /* Page fault */ \
104 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0); \
105 fault = true; \
106 break; \
107 case MEM_UIE: \
108 /* User access to memory above 4MB */ \
109 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0); \
110 fault = true; \
111 break; \
112 case MEM_KERNEL: \
113 case MEM_PAGE_NO_WE: \
114 /* kernel access or page not write enabled */ \
115 /* FIXME: which regs need setting? */ \
116 fault = true; \
117 break; \
118 } \
119 \
120 if (fault) { \
121 if (bits >= 16) \
122 state.bsr0 = 0x7C00; \
123 else \
124 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
125 state.bsr0 |= (address >> 16); \
126 state.bsr1 = address & 0xffff; \
127 printf("ERR: BusError WR\n"); \
128 m68k_pulse_bus_error(); \
129 return; \
130 } \
131 } while (0)
132 /*}}}*/
134 /**
135 * @brief Check memory access permissions for a read operation.
136 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
137 * gcc throws warnings when you have a return-with-value in a void
138 * function, even if the return-with-value is completely unreachable.
139 * Similarly it doesn't like it if you have a return without a value
140 * in a non-void function, even if it's impossible to ever reach the
141 * return-with-no-value. UGH!
142 */
143 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
144 #define ACCESS_CHECK_RD(address, bits) \
145 do { \
146 bool fault = false; \
147 /* MEM_STATUS st; */ \
148 switch (checkMemoryAccess(address, false)) { \
149 case MEM_ALLOWED: \
150 /* Access allowed */ \
151 break; \
152 case MEM_PAGEFAULT: \
153 /* Page fault */ \
154 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0); \
155 fault = true; \
156 break; \
157 case MEM_UIE: \
158 /* User access to memory above 4MB */ \
159 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0); \
160 fault = true; \
161 break; \
162 case MEM_KERNEL: \
163 case MEM_PAGE_NO_WE: \
164 /* kernel access or page not write enabled */ \
165 /* FIXME: which regs need setting? */ \
166 fault = true; \
167 break; \
168 } \
169 \
170 if (fault) { \
171 if (bits >= 16) \
172 state.bsr0 = 0x7C00; \
173 else \
174 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
175 state.bsr0 |= (address >> 16); \
176 state.bsr1 = address & 0xffff; \
177 printf("ERR: BusError RD\n"); \
178 m68k_pulse_bus_error(); \
179 return 0xFFFFFFFF; \
180 } \
181 } while (0)
182 /*}}}*/
184 // Logging macros
185 #define LOG_NOT_HANDLED_R(bits) \
186 if (!handled) printf("unhandled read%02d, addr=0x%08X\n", bits, address);
188 #define LOG_NOT_HANDLED_W(bits) \
189 if (!handled) printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
191 /********************************************************
192 * I/O read/write functions
193 ********************************************************/
195 /**
196 * Issue a warning if a read operation is made with an invalid size
197 */
198 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
199 {
200 assert((bits == 8) || (bits == 16) || (bits == 32));
201 if ((bits & allowed) == 0) {
202 printf("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
203 }
204 }
206 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
207 {
208 ENFORCE_SIZE(bits, address, true, allowed, regname);
209 }
211 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
212 {
213 ENFORCE_SIZE(bits, address, false, allowed, regname);
214 }
216 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
217 {
218 bool handled = false;
220 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
221 // I/O register space, zone A
222 switch (address & 0x0F0000) {
223 case 0x010000: // General Status Register
224 if (bits == 16)
225 state.genstat = (data & 0xffff);
226 else if (bits == 8) {
227 if (address & 0)
228 state.genstat = data;
229 else
230 state.genstat = data << 8;
231 }
232 handled = true;
233 break;
234 case 0x030000: // Bus Status Register 0
235 break;
236 case 0x040000: // Bus Status Register 1
237 break;
238 case 0x050000: // Phone status
239 break;
240 case 0x060000: // DMA Count
241 ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
242 state.dma_count = (data & 0x3FFF);
243 state.idmarw = ((data & 0x4000) == 0x4000);
244 state.dmaen = ((data & 0x8000) == 0x8000);
245 // This handles the "dummy DMA transfer" mentioned in the docs
246 // TODO: access check, peripheral access
247 if (!state.idmarw)
248 WR32(state.base_ram, mapAddr(address, true), state.base_ram_size - 1, 0xDEAD);
249 state.dma_count++;
250 handled = true;
251 break;
252 case 0x070000: // Line Printer Status Register
253 break;
254 case 0x080000: // Real Time Clock
255 break;
256 case 0x090000: // Phone registers
257 switch (address & 0x0FF000) {
258 case 0x090000: // Handset relay
259 case 0x098000:
260 break;
261 case 0x091000: // Line select 2
262 case 0x099000:
263 break;
264 case 0x092000: // Hook relay 1
265 case 0x09A000:
266 break;
267 case 0x093000: // Hook relay 2
268 case 0x09B000:
269 break;
270 case 0x094000: // Line 1 hold
271 case 0x09C000:
272 break;
273 case 0x095000: // Line 2 hold
274 case 0x09D000:
275 break;
276 case 0x096000: // Line 1 A-lead
277 case 0x09E000:
278 break;
279 case 0x097000: // Line 2 A-lead
280 case 0x09F000:
281 break;
282 }
283 break;
284 case 0x0A0000: // Miscellaneous Control Register
285 ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
286 // TODO: handle the ctrl bits properly
287 // TODO: &0x8000 --> dismiss 60hz intr
288 state.dma_reading = (data & 0x4000);
289 if (state.leds != ((~data & 0xF00) >> 8)) {
290 state.leds = (~data & 0xF00) >> 8;
291 printf("LEDs: %s %s %s %s\n",
292 (state.leds & 8) ? "R" : "-",
293 (state.leds & 4) ? "G" : "-",
294 (state.leds & 2) ? "Y" : "-",
295 (state.leds & 1) ? "R" : "-");
296 }
297 handled = true;
298 break;
299 case 0x0B0000: // TM/DIALWR
300 break;
301 case 0x0C0000: // Clear Status Register
302 state.genstat = 0xFFFF;
303 state.bsr0 = 0xFFFF;
304 state.bsr1 = 0xFFFF;
305 handled = true;
306 break;
307 case 0x0D0000: // DMA Address Register
308 if (address & 0x004000) {
309 // A14 high -- set most significant bits
310 state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
311 } else {
312 // A14 low -- set least significant bits
313 state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
314 }
315 handled = true;
316 break;
317 case 0x0E0000: // Disk Control Register
318 ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
319 // B7 = FDD controller reset
320 if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
321 // B6 = drive 0 select -- TODO
322 // B5 = motor enable -- TODO
323 // B4 = HDD controller reset -- TODO
324 // B3 = HDD0 select -- TODO
325 // B2,1,0 = HDD0 head select
326 handled = true;
327 break;
328 case 0x0F0000: // Line Printer Data Register
329 break;
330 }
331 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
332 // I/O register space, zone B
333 switch (address & 0xF00000) {
334 case 0xC00000: // Expansion slots
335 case 0xD00000:
336 switch (address & 0xFC0000) {
337 case 0xC00000: // Expansion slot 0
338 case 0xC40000: // Expansion slot 1
339 case 0xC80000: // Expansion slot 2
340 case 0xCC0000: // Expansion slot 3
341 case 0xD00000: // Expansion slot 4
342 case 0xD40000: // Expansion slot 5
343 case 0xD80000: // Expansion slot 6
344 case 0xDC0000: // Expansion slot 7
345 fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
346 handled = true;
347 break;
348 }
349 break;
350 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
351 case 0xF00000:
352 switch (address & 0x070000) {
353 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
354 break;
355 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
356 ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");
357 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
358 handled = true;
359 break;
360 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
361 break;
362 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
363 break;
364 case 0x040000: // [ef][4c]xxxx ==> General Control Register
365 switch (address & 0x077000) {
366 case 0x040000: // [ef][4c][08]xxx ==> EE
367 break;
368 case 0x041000: // [ef][4c][19]xxx ==> PIE
369 ENFORCE_SIZE_W(bits, address, 16, "PIE");
370 state.pie = ((data & 0x8000) == 0x8000);
371 handled = true;
372 break;
373 case 0x042000: // [ef][4c][2A]xxx ==> BP
374 break;
375 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
376 ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
377 state.romlmap = ((data & 0x8000) == 0x8000);
378 handled = true;
379 break;
380 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
381 ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
382 break;
383 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
384 ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
385 break;
386 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
387 ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
388 break;
389 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
390 ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
391 break;
392 }
393 case 0x050000: // [ef][5d]xxxx ==> 8274
394 break;
395 case 0x060000: // [ef][6e]xxxx ==> Control regs
396 switch (address & 0x07F000) {
397 default:
398 break;
399 }
400 break;
401 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
402 // TODO: figure out which sizes are valid (probably just 8 and 16)
403 // ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER");
404 if (bits == 8) {
405 printf("KBD WR %02X => %02X\n", (address >> 1) & 3, data);
406 keyboard_write(&state.kbd, (address >> 1) & 3, data);
407 handled = true;
408 } else if (bits == 16) {
409 printf("KBD WR %02X => %04X\n", (address >> 1) & 3, data);
410 keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8);
411 handled = true;
412 }
413 break;
414 }
415 }
416 }
418 LOG_NOT_HANDLED_W(bits);
419 }/*}}}*/
421 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
422 {
423 bool handled = false;
424 uint32_t data = 0xFFFFFFFF;
426 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
427 // I/O register space, zone A
428 switch (address & 0x0F0000) {
429 case 0x010000: // General Status Register
430 ENFORCE_SIZE_R(bits, address, 16, "GENSTAT");
431 return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
432 break;
433 case 0x030000: // Bus Status Register 0
434 ENFORCE_SIZE_R(bits, address, 16, "BSR0");
435 return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
436 break;
437 case 0x040000: // Bus Status Register 1
438 ENFORCE_SIZE_R(bits, address, 16, "BSR1");
439 return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
440 break;
441 case 0x050000: // Phone status
442 ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
443 break;
444 case 0x060000: // DMA Count
445 // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
446 // Bit 14 is always unused, so leave it set
447 ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
448 return (state.dma_count & 0x3fff) | 0xC000;
449 break;
450 case 0x070000: // Line Printer Status Register
451 data = 0x00120012; // no parity error, no line printer error, no irqs from FDD or HDD
452 data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0;
453 return data;
454 break;
455 case 0x080000: // Real Time Clock
456 printf("READ NOTIMP: Realtime Clock\n");
457 break;
458 case 0x090000: // Phone registers
459 switch (address & 0x0FF000) {
460 case 0x090000: // Handset relay
461 case 0x098000:
462 break;
463 case 0x091000: // Line select 2
464 case 0x099000:
465 break;
466 case 0x092000: // Hook relay 1
467 case 0x09A000:
468 break;
469 case 0x093000: // Hook relay 2
470 case 0x09B000:
471 break;
472 case 0x094000: // Line 1 hold
473 case 0x09C000:
474 break;
475 case 0x095000: // Line 2 hold
476 case 0x09D000:
477 break;
478 case 0x096000: // Line 1 A-lead
479 case 0x09E000:
480 break;
481 case 0x097000: // Line 2 A-lead
482 case 0x09F000:
483 break;
484 }
485 break;
486 case 0x0A0000: // Miscellaneous Control Register -- write only!
487 handled = true;
488 break;
489 case 0x0B0000: // TM/DIALWR
490 break;
491 case 0x0C0000: // Clear Status Register -- write only!
492 handled = true;
493 break;
494 case 0x0D0000: // DMA Address Register
495 break;
496 case 0x0E0000: // Disk Control Register
497 break;
498 case 0x0F0000: // Line Printer Data Register
499 break;
500 }
501 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
502 // I/O register space, zone B
503 switch (address & 0xF00000) {
504 case 0xC00000: // Expansion slots
505 case 0xD00000:
506 switch (address & 0xFC0000) {
507 case 0xC00000: // Expansion slot 0
508 case 0xC40000: // Expansion slot 1
509 case 0xC80000: // Expansion slot 2
510 case 0xCC0000: // Expansion slot 3
511 case 0xD00000: // Expansion slot 4
512 case 0xD40000: // Expansion slot 5
513 case 0xD80000: // Expansion slot 6
514 case 0xDC0000: // Expansion slot 7
515 fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
516 handled = true;
517 break;
518 }
519 break;
520 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
521 case 0xF00000:
522 switch (address & 0x070000) {
523 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
524 break;
525 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
526 ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");
527 return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
528 break;
529 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
530 break;
531 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
532 break;
533 case 0x040000: // [ef][4c]xxxx ==> General Control Register
534 switch (address & 0x077000) {
535 case 0x040000: // [ef][4c][08]xxx ==> EE
536 case 0x041000: // [ef][4c][19]xxx ==> PIE
537 case 0x042000: // [ef][4c][2A]xxx ==> BP
538 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
539 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
540 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
541 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
542 // All write-only registers... TODO: bus error?
543 handled = true;
544 break;
545 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
546 break;
547 }
548 break;
549 case 0x050000: // [ef][5d]xxxx ==> 8274
550 break;
551 case 0x060000: // [ef][6e]xxxx ==> Control regs
552 switch (address & 0x07F000) {
553 default:
554 break;
555 }
556 break;
557 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
558 // TODO: figure out which sizes are valid (probably just 8 and 16)
559 //ENFORCE_SIZE_R(bits, address, 16, "KEYBOARD CONTROLLER");
560 {
561 if (bits == 8) {
562 return keyboard_read(&state.kbd, (address >> 1) & 3);
563 } else {
564 return keyboard_read(&state.kbd, (address >> 1) & 3) << 8;
565 }
566 return data;
567 }
568 break;
569 }
570 }
571 }
573 LOG_NOT_HANDLED_R(bits);
575 return data;
576 }/*}}}*/
579 /********************************************************
580 * m68k memory read/write support functions for Musashi
581 ********************************************************/
583 /**
584 * @brief Read M68K memory, 32-bit
585 */
586 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
587 {
588 uint32_t data = 0xFFFFFFFF;
590 // If ROMLMAP is set, force system to access ROM
591 if (!state.romlmap)
592 address |= 0x800000;
594 // Check access permissions
595 ACCESS_CHECK_RD(address, 32);
597 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
598 // ROM access
599 return RD32(state.rom, address, ROM_SIZE - 1);
600 } else if (address <= 0x3fffff) {
601 // RAM access
602 uint32_t newAddr = mapAddr(address, false);
603 if (newAddr <= 0x1fffff) {
604 return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
605 } else {
606 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
607 return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
608 else
609 return 0xffffffff;
610 }
611 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
612 // I/O register space, zone A
613 switch (address & 0x0F0000) {
614 case 0x000000: // Map RAM access
615 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
616 return RD32(state.map, address, 0x7FF);
617 break;
618 case 0x020000: // Video RAM
619 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
620 return RD32(state.vram, address, 0x7FFF);
621 break;
622 default:
623 return IoRead(address, 32);
624 }
625 } else {
626 return IoRead(address, 32);
627 }
629 return data;
630 }/*}}}*/
632 /**
633 * @brief Read M68K memory, 16-bit
634 */
635 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
636 {
637 uint16_t data = 0xFFFF;
639 // If ROMLMAP is set, force system to access ROM
640 if (!state.romlmap)
641 address |= 0x800000;
643 // Check access permissions
644 ACCESS_CHECK_RD(address, 16);
646 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
647 // ROM access
648 data = RD16(state.rom, address, ROM_SIZE - 1);
649 } else if (address <= 0x3fffff) {
650 // RAM access
651 uint32_t newAddr = mapAddr(address, false);
652 if (newAddr <= 0x1fffff) {
653 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
654 } else {
655 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
656 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
657 else
658 return 0xffff;
659 }
660 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
661 // I/O register space, zone A
662 switch (address & 0x0F0000) {
663 case 0x000000: // Map RAM access
664 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
665 data = RD16(state.map, address, 0x7FF);
666 break;
667 case 0x020000: // Video RAM
668 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
669 data = RD16(state.vram, address, 0x7FFF);
670 break;
671 default:
672 data = IoRead(address, 16);
673 }
674 } else {
675 data = IoRead(address, 16);
676 }
678 return data;
679 }/*}}}*/
681 /**
682 * @brief Read M68K memory, 8-bit
683 */
684 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
685 {
686 uint8_t data = 0xFF;
688 // If ROMLMAP is set, force system to access ROM
689 if (!state.romlmap)
690 address |= 0x800000;
692 // Check access permissions
693 ACCESS_CHECK_RD(address, 8);
695 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
696 // ROM access
697 data = RD8(state.rom, address, ROM_SIZE - 1);
698 } else if (address <= 0x3fffff) {
699 // RAM access
700 uint32_t newAddr = mapAddr(address, false);
701 if (newAddr <= 0x1fffff) {
702 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
703 } else {
704 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
705 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
706 else
707 return 0xff;
708 }
709 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
710 // I/O register space, zone A
711 switch (address & 0x0F0000) {
712 case 0x000000: // Map RAM access
713 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
714 data = RD8(state.map, address, 0x7FF);
715 break;
716 case 0x020000: // Video RAM
717 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
718 data = RD8(state.vram, address, 0x7FFF);
719 break;
720 default:
721 data = IoRead(address, 8);
722 }
723 } else {
724 data = IoRead(address, 8);
725 }
727 return data;
728 }/*}}}*/
730 /**
731 * @brief Write M68K memory, 32-bit
732 */
733 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
734 {
735 // If ROMLMAP is set, force system to access ROM
736 if (!state.romlmap)
737 address |= 0x800000;
739 // Check access permissions
740 ACCESS_CHECK_WR(address, 32);
742 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
743 // ROM access
744 } else if (address <= 0x3FFFFF) {
745 // RAM access
746 uint32_t newAddr = mapAddr(address, true);
747 if (newAddr <= 0x1fffff)
748 WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
749 else
750 WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
751 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
752 // I/O register space, zone A
753 switch (address & 0x0F0000) {
754 case 0x000000: // Map RAM access
755 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
756 WR32(state.map, address, 0x7FF, value);
757 break;
758 case 0x020000: // Video RAM
759 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
760 WR32(state.vram, address, 0x7FFF, value);
761 break;
762 default:
763 IoWrite(address, value, 32);
764 }
765 } else {
766 IoWrite(address, value, 32);
767 }
768 }/*}}}*/
770 /**
771 * @brief Write M68K memory, 16-bit
772 */
773 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
774 {
775 // If ROMLMAP is set, force system to access ROM
776 if (!state.romlmap)
777 address |= 0x800000;
779 // Check access permissions
780 ACCESS_CHECK_WR(address, 16);
782 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
783 // ROM access
784 } else if (address <= 0x3FFFFF) {
785 // RAM access
786 uint32_t newAddr = mapAddr(address, true);
787 if (newAddr <= 0x1fffff)
788 WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
789 else
790 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
791 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
792 // I/O register space, zone A
793 switch (address & 0x0F0000) {
794 case 0x000000: // Map RAM access
795 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
796 WR16(state.map, address, 0x7FF, value);
797 break;
798 case 0x020000: // Video RAM
799 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
800 WR16(state.vram, address, 0x7FFF, value);
801 break;
802 default:
803 IoWrite(address, value, 16);
804 }
805 } else {
806 IoWrite(address, value, 16);
807 }
808 }/*}}}*/
810 /**
811 * @brief Write M68K memory, 8-bit
812 */
813 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
814 {
815 // If ROMLMAP is set, force system to access ROM
816 if (!state.romlmap)
817 address |= 0x800000;
819 // Check access permissions
820 ACCESS_CHECK_WR(address, 8);
822 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
823 // ROM access (read only!)
824 } else if (address <= 0x3FFFFF) {
825 // RAM access
826 uint32_t newAddr = mapAddr(address, true);
827 if (newAddr <= 0x1fffff)
828 WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
829 else
830 WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
831 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
832 // I/O register space, zone A
833 switch (address & 0x0F0000) {
834 case 0x000000: // Map RAM access
835 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
836 WR8(state.map, address, 0x7FF, value);
837 break;
838 case 0x020000: // Video RAM
839 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
840 WR8(state.vram, address, 0x7FFF, value);
841 break;
842 default:
843 IoWrite(address, value, 8);
844 }
845 } else {
846 IoWrite(address, value, 8);
847 }
848 }/*}}}*/
851 // for the disassembler
852 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
853 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
854 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }