src/memory.c

Fri, 12 Apr 2013 12:34:32 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Fri, 12 Apr 2013 12:34:32 +0100
branch
experimental_memory_mapper_v2
changeset 140
1e4c45b144c4
parent 133
84ed5ec1d1e0
child 141
8460d432606f
permissions
-rw-r--r--

Fix read-after-write logic

In some cases (notably reading from a page after having written to it), the
mapper may change the pagestate from "accessed and written" ("dirty"; PS0,PS1)
to "accessed but not written" (clean; PS1,!PS0). This should never, ever, EVER
happen. Once a page is dirty, it remains so until the 68k clears the DIRTY
bit.

Once again, this wonderful bit of logic was missing from the TRM.

     1 #include <stdio.h>
     2 #include <stdlib.h>
     3 #include <stdint.h>
     4 #include <stdbool.h>
     5 #include <assert.h>
     6 #include "musashi/m68k.h"
     7 #include "state.h"
     8 #include "utils.h"
     9 #include "memory.h"
    11 // The value which will be returned if the CPU attempts to read from empty memory
    12 // TODO (FIXME?) - need to figure out if R/W ops wrap around. This seems to appease the UNIX kernel and P4TEST.
    13 #define EMPTY 0xFFFFFFFFUL
    14 //#define EMPTY 0x55555555UL
    15 //#define EMPTY 0x00000000UL
    17 /******************
    18  * Memory mapping
    19  ******************/
    21 /// Set a page bit
    22 #define MAP_SET_PAGEBIT(addr, bit) state.map[(MAP_ADDR_TO_PAGE(addr))*2] |=  ((uint8_t)bit << 2)
    23 /// Clear a page bit
    24 #define MAP_CLR_PAGEBIT(addr, bit) state.map[(MAP_ADDR_TO_PAGE(addr))*2] &= ~((uint8_t)bit << 2)
    27 /********************************************************
    28  * m68k memory read/write support functions for Musashi
    29  ********************************************************/
    31 /**
    32  * @brief	Check memory access permissions for a write operation.
    33  * @note	This used to be a single macro (merged with ACCESS_CHECK_RD), but
    34  * 			gcc throws warnings when you have a return-with-value in a void
    35  * 			function, even if the return-with-value is completely unreachable.
    36  * 			Similarly it doesn't like it if you have a return without a value
    37  * 			in a non-void function, even if it's impossible to ever reach the
    38  * 			return-with-no-value. UGH!
    39  */
    40 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
    41 #define ACCESS_CHECK_WR(address, bits)								\
    42 	do {															\
    43 		if (access_check_cpu(address, bits, true)) {				\
    44 			return;													\
    45 		}															\
    46 	} while (0)
    47 /*}}}*/
    49 /**
    50  * @brief Check memory access permissions for a read operation.
    51  * @note	This used to be a single macro (merged with ACCESS_CHECK_WR), but
    52  * 			gcc throws warnings when you have a return-with-value in a void
    53  * 			function, even if the return-with-value is completely unreachable.
    54  * 			Similarly it doesn't like it if you have a return without a value
    55  * 			in a non-void function, even if it's impossible to ever reach the
    56  * 			return-with-no-value. UGH!
    57  */
    58 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
    59 #define ACCESS_CHECK_RD(address, bits)								\
    60 	do {															\
    61 		if (access_check_cpu(address, bits, false)) {				\
    62 			if (bits == 32)											\
    63 				return EMPTY & 0xFFFFFFFF;							\
    64 			else													\
    65 				return EMPTY & ((1UL << bits)-1);					\
    66 		}															\
    67 	} while (0)
    68 /*}}}*/
    71 /**
    72  * Update the page bits for a given memory address
    73  *
    74  * @param	addr	Memory address being accessed
    75  * @param	l7intr	Set to <i>true</i> if a level-seven interrupt has been
    76  * 					signalled (even if <b>ENABLE ERROR</b> isn't set).
    77  * @param	write	Set to <i>true</i> if the address is being written to.
    78  */
    79 static void update_page_bits(uint32_t addr, bool l7intr, bool write)
    80 {
    81 	bool ps0_state = false;
    83 	// Don't try and update pagebits for non-RAM addresses
    84 	if (addr > 0x3FFFFF)
    85 		return;
    87 	if (l7intr) {
    88 //		if (!(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
    89 			// FIXME FUCKUP The ruddy TRM is wrong AGAIN! If above line is uncommented, Really Bad Things Happen.
    90 		if ((MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
    91 			// Level 7 interrupt, PS0 clear, PS1 don't-care. Set PS0.
    92 			ps0_state = true;
    93 		}
    94 	} else {
    95 		// No L7 interrupt
    96 		if ((write && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS1) &&  (MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) ||
    97 			(write &&  (MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) ||
    98 			(          (MAP_PAGEBITS(addr) & PAGE_BIT_PS1) &&  (MAP_PAGEBITS(addr) & PAGE_BIT_PS0)))  /* NOTE -- Once again, this case was missing from the PAL equations in the TRM... */
    99 		{
   100 			// No L7 interrupt, PS[1:0] = 0b01, write
   101 			// No L7 interrupt, PS[1:0] = 0b10, write
   102 			ps0_state = true;
   103 		}
   104 	}
   106 #ifdef MAPRAM_BIT_TEST
   107 	LOG("Starting Mapram Bit Test");
   108 	state.map[0] = state.map[1] = 0;
   109 	LOG("Start   = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   110 	MAP_SET_PAGEBIT(0, PAGE_BIT_WE);
   111 	LOG("Set WE  = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   112 	MAP_SET_PAGEBIT(0, PAGE_BIT_PS1);
   113 	LOG("Set PS1 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   114 	MAP_SET_PAGEBIT(0, PAGE_BIT_PS0);
   115 	LOG("Set PS0 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   117 	MAP_CLR_PAGEBIT(0, PAGE_BIT_WE);
   118 	LOG("Clr WE  = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   119 	MAP_CLR_PAGEBIT(0, PAGE_BIT_PS1);
   120 	LOG("Clr PS1 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   121 	MAP_CLR_PAGEBIT(0, PAGE_BIT_PS0);
   122 	LOG("Clr PS0 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   123 	exit(-1);
   124 #endif
   126 	uint16_t old_pagebits = MAP_PAGEBITS(addr);
   128 	// PS1 is always set on access
   129 	MAP_SET_PAGEBIT(addr, PAGE_BIT_PS1);
   131 	uint16_t new_pagebit1 = MAP_PAGEBITS(addr);
   133 	// Update PS0
   134 	if (ps0_state) {
   135 		MAP_SET_PAGEBIT(addr, PAGE_BIT_PS0);
   136 	} else {
   137 		MAP_CLR_PAGEBIT(addr, PAGE_BIT_PS0);
   138 	}
   140 	uint16_t new_pagebit2 = MAP_PAGEBITS(addr);
   141 	switch (addr) {
   142 		case 0x000000:
   143 		case 0x001000:
   144 		case 0x002000:
   145 		case 0x003000:
   146 		case 0x004000:
   147 		case 0x033000:
   148 		case 0x034000:
   149 		case 0x035000:
   150 			LOG("Addr %08X MapNew %04X Pagebit update -- ps0 %d, %02X => %02X => %02X", addr, MAPRAM_ADDR(addr), ps0_state, old_pagebits, new_pagebit1, new_pagebit2);
   151 		default:
   152 			break;
   153 	}
   154 }
   156 bool access_check_dma(void)
   157 {
   158 	// TODO FIXME BUGBUG Sanity check - Make sure DMAC is only accessing RAM addresses
   160 	// DMA access check -- make sure the page is mapped in
   161 	if (!(MAP_PAGEBITS(state.dma_address) & PAGE_BIT_PS0) && !(MAP_PAGEBITS(state.dma_address) & PAGE_BIT_PS1)) {
   162 		// DMA access to page which is not mapped in.
   163 		// Level 7 interrupt, page fault, DMA invoked
   164 		state.genstat = 0xABFF
   165 			| (state.dma_reading ? 0x4000 : 0)
   166 			| (state.pie ? 0x0400 : 0);
   168 		// XXX: Check all this stuff.
   169 		state.bsr0 = 0x3C00;
   170 		state.bsr0 |= (state.dma_address >> 16);
   171 		state.bsr1 = state.dma_address & 0xffff;
   173 		// Update page bits for this transfer
   174 		update_page_bits(state.dma_address, true, !state.dma_reading);
   176 		// XXX: is this right?
   177 		// Fire a Level 7 interrupt
   178 		/*if (state.ee)*/ m68k_set_irq(7);
   180 		LOG("BUS ERROR FROM DMA: genstat=%04X, bsr0=%04X, bsr1=%04X\n", state.genstat, state.bsr0, state.bsr1);
   181 		return false;
   182 	} else {
   183 		// No errors. Just update the page bits.
   184 		update_page_bits(state.dma_address, false, !state.dma_reading);
   185 		return true;
   186 	}
   187 }
   189 /**
   190  * Check memory access permissions for a CPU memory access.
   191  *
   192  * @param	addr	Virtual memory address being accessed (from CPU address bus).
   193  * @param	bits	Word size of this transfer (8, 16 or 32 bits).
   194  * @param	write	<i>true</i> if this is a write operation, <i>false</i> if it is a read operation.
   195  * @return	<i>true</i> if the access was denied and a level-7 interrupt and/or bus error raised.
   196  * 			<i>false</i> if the access was allowed.
   197  */
   198 bool access_check_cpu(uint32_t addr, int bits, bool write)
   199 {
   200 	bool supervisor = (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000);
   201 	bool fault = false;
   203 	// TODO FIXME BUGBUG? Do we need to check for supervisor access here?
   204 	if ((addr >= 0x000000) && (addr <= 0x3FFFFF) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
   205 		// (A) Page Fault -- user access to page which is not mapped in
   206 		// Level 7 Interrupt, Bus Error, regs=PAGEFAULT
   207 		if (write) {
   208 			state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0);
   209 		} else {
   210 			state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0);
   211 		}
   212 		fault = true;
   213 	} else if (!supervisor && (addr >= 0x000000) && (addr <= 0x07FFFF)) {
   214 		// (B) User attempted to access the kernel
   215 		// Level 7 Interrupt, Bus Error, regs=KERNEL
   216 		if (write) {
   217 			// XXX: BUGBUG? Is this correct?
   218 			state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0);
   219 		} else {
   220 			state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0);
   221 		}
   222 		fault = true;
   223 	} else if (!supervisor && write && (addr >= 0x000000) && (addr <= 0x3FFFFF) && !(MAP_PAGEBITS(addr) & PAGE_BIT_WE)) {
   224 		// (C) User attempted to write to a page which is not write enabled
   225 		// Level 7 Interrupt, Bus Error, regs=WRITE_EN
   226 		if (write) {
   227 			// XXX: BUGBUG? Is this correct?
   228 			state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0);
   229 		} else {
   230 			state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0);
   231 		}
   232 		fault = true;
   233 	} else if (!supervisor && (addr >= 0x400000) && (addr <= 0xFFFFFF)) {
   234 		// (D) UIE - user I/O exception
   235 		// Bus Error only, regs=UIE
   236 		if (write) {
   237 			state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0);
   238 		} else {
   239 			state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0);
   240 		}
   241 		fault = true;
   242 	}
   244 	// Update the page bits first
   245 	update_page_bits(addr, fault, write);
   247 	if (fault) {
   248 		if (bits >= 16)
   249 			state.bsr0 = 0x7C00;
   250 		else
   251 			state.bsr0 = (addr & 1) ? 0x7E00 : 0x7D00;
   252 		// FIXME? Physical or virtual address here?
   253 		state.bsr0 |= (addr >> 16);
   254 		state.bsr1 = addr & 0xffff;
   256 		LOG("CPU Bus Error or L7Intr while %s, vaddr %08X, map %08X, pagebits 0x%02X bsr0=%04X bsr1=%04X genstat=%04X", 
   257 				write ? "writing" : "reading", addr,
   258 				MAPRAM_ADDR(addr & 0x3fffff),
   259 				MAP_PAGEBITS(addr & 0x3fffff),
   260 				state.bsr0, state.bsr1, state.genstat);
   262 		// FIXME? BUGBUG? Does EE disable one or both of these?
   263 		// /*if (state.ee)*/ m68k_set_irq(7);
   264 		/*if (state.ee)*/ m68k_pulse_bus_error();
   265 	}
   267 	return fault;
   268 }
   270 // Logging macros
   271 #define LOG_NOT_HANDLED_R(bits)															\
   272 	if (!handled) fprintf(stderr, "unhandled read%02d, addr=0x%08X\n", bits, address);
   274 #define LOG_NOT_HANDLED_W(bits)															\
   275 	if (!handled) fprintf(stderr, "unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
   277 /********************************************************
   278  * I/O read/write functions
   279  ********************************************************/
   281 /**
   282  * Issue a warning if a read operation is made with an invalid size
   283  */
   284 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
   285 {
   286 	assert((bits == 8) || (bits == 16) || (bits == 32));
   287 	if ((bits & allowed) == 0) {
   288 		LOG("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
   289 	}
   290 }
   292 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
   293 {
   294 	ENFORCE_SIZE(bits, address, true, allowed, regname);
   295 }
   297 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
   298 {
   299 	ENFORCE_SIZE(bits, address, false, allowed, regname);
   300 }
   302 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
   303 {
   304 	bool handled = false;
   306 	if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   307 		// I/O register space, zone A
   308 		switch (address & 0x0F0000) {
   309 			case 0x010000:				// General Status Register
   310 				if (bits == 16)
   311 					state.genstat = (data & 0xffff);
   312 				else if (bits == 8) {
   313 					if (address & 0)
   314 						state.genstat = data;
   315 					else
   316 						state.genstat = data << 8;
   317 				}
   318 				handled = true;
   319 				break;
   320 			case 0x030000:				// Bus Status Register 0
   321 				break;
   322 			case 0x040000:				// Bus Status Register 1
   323 				break;
   324 			case 0x050000:				// Phone status
   325 				break;
   326 			case 0x060000:				// DMA Count
   327 				ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
   328 				state.dma_count = (data & 0x3FFF);
   329 				state.idmarw = ((data & 0x4000) == 0x4000);
   330 				state.dmaen = ((data & 0x8000) == 0x8000);
   331 				// This handles the "dummy DMA transfer" mentioned in the docs
   332 				// disabled because it causes the floppy test to fail
   333 #if 0
   334 				if (!state.idmarw){
   335 					if (access_check_dma(true)){
   336 						uint32_t newAddr = mapAddr(state.dma_address, true);
   337 						// RAM access
   338 						if (newAddr <= 0x1fffff)
   339 							WR16(state.base_ram, newAddr, state.base_ram_size - 1, 0xFF);
   340 						else if (address <= 0x3FFFFF)
   341 							WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, 0xFF);
   342 					}
   343 				}
   344 #endif
   345 				state.dma_count++;
   346 				handled = true;
   347 				break;
   348 			case 0x070000:				// Line Printer Status Register
   349 				break;
   350 			case 0x080000:				// Real Time Clock
   351 				LOGS("REAL TIME CLOCK WRITE");
   352 				break;
   353 			case 0x090000:				// Phone registers
   354 				switch (address & 0x0FF000) {
   355 					case 0x090000:		// Handset relay
   356 					case 0x098000:
   357 						break;
   358 					case 0x091000:		// Line select 2
   359 					case 0x099000:
   360 						break;
   361 					case 0x092000:		// Hook relay 1
   362 					case 0x09A000:
   363 						break;
   364 					case 0x093000:		// Hook relay 2
   365 					case 0x09B000:
   366 						break;
   367 					case 0x094000:		// Line 1 hold
   368 					case 0x09C000:
   369 						break;
   370 					case 0x095000:		// Line 2 hold
   371 					case 0x09D000:
   372 						break;
   373 					case 0x096000:		// Line 1 A-lead
   374 					case 0x09E000:
   375 						break;
   376 					case 0x097000:		// Line 2 A-lead
   377 					case 0x09F000:
   378 						break;
   379 				}
   380 				break;
   381 			case 0x0A0000:				// Miscellaneous Control Register
   382 				ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
   383 				// TODO: handle the ctrl bits properly
   384 				if (data & 0x8000){
   385 					state.timer_enabled = 1;
   386 				}else{
   387 					state.timer_enabled = 0;
   388 					state.timer_asserted = 0;
   389 				}
   390 				state.dma_reading = (data & 0x4000);
   391 				if (state.leds != ((~data & 0xF00) >> 8)) {
   392 					state.leds = (~data & 0xF00) >> 8;
   393 #ifdef SHOW_LEDS
   394 					printf("LEDs: %s %s %s %s\n",
   395 							(state.leds & 8) ? "R" : "-",
   396 							(state.leds & 4) ? "G" : "-",
   397 							(state.leds & 2) ? "Y" : "-",
   398 							(state.leds & 1) ? "R" : "-");
   399 #endif
   400 				}
   401 				handled = true;
   402 				break;
   403 			case 0x0B0000:				// TM/DIALWR
   404 				break;
   405 			case 0x0C0000:				// Clear Status Register
   406 				state.genstat = 0xFFFF;
   407 				state.bsr0 = 0xFFFF;
   408 				state.bsr1 = 0xFFFF;
   409 				handled = true;
   410 				break;
   411 			case 0x0D0000:				// DMA Address Register
   412 				if (address & 0x004000) {
   413 					// A14 high -- set most significant bits
   414 					state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
   415 				} else {
   416 					// A14 low -- set least significant bits
   417 					state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
   418 				}
   419 				handled = true;
   420 				break;
   421 			case 0x0E0000:				// Disk Control Register
   422 				{
   423 					bool fd_selected;
   424 					bool hd_selected;
   425 					ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
   426 					// B7 = FDD controller reset
   427 					if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
   428 					// B6 = drive 0 select
   429 					fd_selected = (data & 0x40) != 0;
   430 					// B5 = motor enable -- TODO
   431 					// B4 = HDD controller reset
   432 					if ((data & 0x10) == 0) wd2010_reset(&state.hdc_ctx);
   433 					// B3 = HDD0 select
   434 					hd_selected = (data & 0x08) != 0;
   435 					// B2,1,0 = HDD0 head select -- TODO?
   436 					if (hd_selected && !state.hd_selected){
   437 						state.fd_selected = false;
   438 						state.hd_selected = true;
   439 					}else if (fd_selected && !state.fd_selected){
   440 						state.hd_selected = false;
   441 						state.fd_selected = true;
   442 					}
   443 					handled = true;
   444 					break;
   445 				}
   446 			case 0x0F0000:				// Line Printer Data Register
   447 				break;
   448 		}
   449 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   450 		// I/O register space, zone B
   451 		switch (address & 0xF00000) {
   452 			case 0xC00000:				// Expansion slots
   453 			case 0xD00000:
   454 				switch (address & 0xFC0000) {
   455 					case 0xC00000:		// Expansion slot 0
   456 					case 0xC40000:		// Expansion slot 1
   457 					case 0xC80000:		// Expansion slot 2
   458 					case 0xCC0000:		// Expansion slot 3
   459 					case 0xD00000:		// Expansion slot 4
   460 					case 0xD40000:		// Expansion slot 5
   461 					case 0xD80000:		// Expansion slot 6
   462 					case 0xDC0000:		// Expansion slot 7
   463 						fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
   464 						handled = true;
   465 						break;
   466 				}
   467 				break;
   468 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   469 			case 0xF00000:
   470 				switch (address & 0x070000) {
   471 					case 0x000000:		// [ef][08]xxxx ==> WD2010 hard disc controller
   472 						wd2010_write_reg(&state.hdc_ctx, (address >> 1) & 7, data);
   473 						handled = true;
   474 						break;
   475 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   476 						/*ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");*/
   477 						wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
   478 						handled = true;
   479 						break;
   480 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   481 						// MCR2 - UNIX PC Rev. P5.1 HDD head select b3 and potential HDD#2 select
   482 						wd2010_write_reg(&state.hdc_ctx, UNIXPC_REG_MCR2, data);
   483 						handled = true;
   484 						break;
   485 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   486 						LOGS("REAL TIME CLOCK DATA WRITE");
   487 						break;
   488 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   489 						switch (address & 0x077000) {
   490 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   491 								// Error Enable. If =0, Level7 intrs and bus errors are masked.
   492 								ENFORCE_SIZE_W(bits, address, 16, "EE");
   493 								state.ee = ((data & 0x8000) == 0x8000);
   494 								handled = true;
   495 								break;
   496 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   497 								ENFORCE_SIZE_W(bits, address, 16, "PIE");
   498 								state.pie = ((data & 0x8000) == 0x8000);
   499 								handled = true;
   500 								break;
   501 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   502 								break;
   503 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   504 								ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
   505 								state.romlmap = ((data & 0x8000) == 0x8000);
   506 								handled = true;
   507 								break;
   508 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   509 								ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
   510 								break;
   511 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   512 								ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
   513 								break;
   514 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   515 								ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
   516 								break;
   517 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   518 								ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
   519 								break;
   520 						}
   521 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   522 						break;
   523 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   524 						switch (address & 0x07F000) {
   525 							default:
   526 								break;
   527 						}
   528 						break;
   529 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   530 						// TODO: figure out which sizes are valid (probably just 8 and 16)
   531 						// ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER");
   532 						if (bits == 8) {
   533 #ifdef LOG_KEYBOARD_WRITES
   534 							LOG("KBD WR %02X => %02X\n", (address >> 1) & 3, data);
   535 #endif
   536 							keyboard_write(&state.kbd, (address >> 1) & 3, data);
   537 							handled = true;
   538 						} else if (bits == 16) {
   539 #ifdef LOG_KEYBOARD_WRITES
   540 							LOG("KBD WR %02X => %04X\n", (address >> 1) & 3, data);
   541 #endif
   542 							keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8);
   543 							handled = true;
   544 						}
   545 						break;
   546 				}
   547 		}
   548 	}
   550 	LOG_NOT_HANDLED_W(bits);
   551 }/*}}}*/
   553 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
   554 {
   555 	bool handled = false;
   556 	uint32_t data = EMPTY & 0xFFFFFFFF;
   558 	if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   559 		// I/O register space, zone A
   560 		switch (address & 0x0F0000) {
   561 			case 0x010000:				// General Status Register
   562 				/* ENFORCE_SIZE_R(bits, address, 16, "GENSTAT"); */
   563 				if (bits == 32) {
   564 					return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
   565 				} else if (bits == 16) {
   566 					return (uint16_t)state.genstat;
   567 				} else {
   568 					return (uint8_t)(state.genstat & 0xff);
   569 				}
   570 				break;
   571 			case 0x030000:				// Bus Status Register 0
   572 				ENFORCE_SIZE_R(bits, address, 16, "BSR0");
   573 				return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
   574 				break;
   575 			case 0x040000:				// Bus Status Register 1
   576 				ENFORCE_SIZE_R(bits, address, 16, "BSR1");
   577 				return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
   578 				break;
   579 			case 0x050000:				// Phone status
   580 				ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
   581 				break;
   582 			case 0x060000:				// DMA Count
   583 				// TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
   584 				// Bit 14 is always unused, so leave it set
   585 				ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
   586 				return (state.dma_count & 0x3fff) | 0xC000;
   587 				break;
   588 			case 0x070000:				// Line Printer Status Register
   589 				data = 0x00120012;	// no parity error, no line printer error, no irqs from FDD or HDD
   590 				data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0;
   591 				data |= wd2010_get_irq(&state.hdc_ctx) ? 0x00040004 : 0;
   592 				return data;
   593 				break;
   594 			case 0x080000:				// Real Time Clock
   595 				LOGS("REAL TIME CLOCK READ");
   596 				break;
   597 			case 0x090000:				// Phone registers
   598 				switch (address & 0x0FF000) {
   599 					case 0x090000:		// Handset relay
   600 					case 0x098000:
   601 						break;
   602 					case 0x091000:		// Line select 2
   603 					case 0x099000:
   604 						break;
   605 					case 0x092000:		// Hook relay 1
   606 					case 0x09A000:
   607 						break;
   608 					case 0x093000:		// Hook relay 2
   609 					case 0x09B000:
   610 						break;
   611 					case 0x094000:		// Line 1 hold
   612 					case 0x09C000:
   613 						break;
   614 					case 0x095000:		// Line 2 hold
   615 					case 0x09D000:
   616 						break;
   617 					case 0x096000:		// Line 1 A-lead
   618 					case 0x09E000:
   619 						break;
   620 					case 0x097000:		// Line 2 A-lead
   621 					case 0x09F000:
   622 						break;
   623 				}
   624 				break;
   625 			case 0x0A0000:				// Miscellaneous Control Register -- write only!
   626 				handled = true;
   627 				break;
   628 			case 0x0B0000:				// TM/DIALWR
   629 				break;
   630 			case 0x0C0000:				// Clear Status Register -- write only!
   631 				handled = true;
   632 				break;
   633 			case 0x0D0000:				// DMA Address Register
   634 				break;
   635 			case 0x0E0000:				// Disk Control Register
   636 				break;
   637 			case 0x0F0000:				// Line Printer Data Register
   638 				break;
   639 		}
   640 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   641 		// I/O register space, zone B
   642 		switch (address & 0xF00000) {
   643 			case 0xC00000:				// Expansion slots
   644 			case 0xD00000:
   645 				switch (address & 0xFC0000) {
   646 					case 0xC00000:		// Expansion slot 0
   647 					case 0xC40000:		// Expansion slot 1
   648 					case 0xC80000:		// Expansion slot 2
   649 					case 0xCC0000:		// Expansion slot 3
   650 					case 0xD00000:		// Expansion slot 4
   651 					case 0xD40000:		// Expansion slot 5
   652 					case 0xD80000:		// Expansion slot 6
   653 					case 0xDC0000:		// Expansion slot 7
   654 						fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
   655 						handled = true;
   656 						break;
   657 				}
   658 				break;
   659 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   660 			case 0xF00000:
   661 				switch (address & 0x070000) {
   662 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   663 						return (wd2010_read_reg(&state.hdc_ctx, (address >> 1) & 7));
   665 						break;
   666 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   667 						/*ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");*/
   668 						return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
   669 						break;
   670 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   671 						break;
   672 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   673 						LOGS("REAL TIME CLOCK DATA READ");
   674 						break;
   675 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   676 						switch (address & 0x077000) {
   677 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   678 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   679 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   680 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   681 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   682 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   683 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   684 								// All write-only registers... TODO: bus error?
   685 								handled = true;
   686 								break;
   687 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
   688 								break;
   689 						}
   690 						break;
   691 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   692 						break;
   693 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   694 						switch (address & 0x07F000) {
   695 							default:
   696 								break;
   697 						}
   698 						break;
   699 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   700 						// TODO: figure out which sizes are valid (probably just 8 and 16)
   701 						//ENFORCE_SIZE_R(bits, address, 16, "KEYBOARD CONTROLLER");
   702 						{
   703 							if (bits == 8) {
   704 								return keyboard_read(&state.kbd, (address >> 1) & 3);
   705 							} else {
   706 								return keyboard_read(&state.kbd, (address >> 1) & 3) << 8;
   707 							}
   708 							return data;
   709 						}
   710 						break;
   711 				}
   712 		}
   713 	}
   715 	LOG_NOT_HANDLED_R(bits);
   717 	return data;
   718 }/*}}}*/
   721 /********************************************************
   722  * m68k memory read/write support functions for Musashi
   723  ********************************************************/
   725 /**
   726  * @brief Read M68K memory, 32-bit
   727  */
   728 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
   729 {
   730 	uint32_t data = EMPTY & 0xFFFFFFFF;
   732 	// If ROMLMAP is set, force system to access ROM
   733 	if (!state.romlmap)
   734 		address |= 0x800000;
   736 	// Check access permissions
   737 	ACCESS_CHECK_RD(address, 32);
   739 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   740 		// ROM access
   741 		return RD32(state.rom, address, ROM_SIZE - 1);
   742 	} else if (address <= 0x3fffff) {
   743 		// RAM access
   744 		uint32_t newAddr = MAP_ADDR(address);
   746 		if (newAddr <= 0x1fffff) {
   747 			// Base memory wraps around
   748 			return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
   749 		} else {
   750 			if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
   751 				return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   752 			else
   753 				return EMPTY & 0xffffffff;
   754 		}
   755 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   756 		// I/O register space, zone A
   757 		switch (address & 0x0F0000) {
   758 			case 0x000000:				// Map RAM access
   759 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
   760 				return RD32(state.map, address, 0x7FF);
   761 				break;
   762 			case 0x020000:				// Video RAM
   763 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
   764 				return RD32(state.vram, address, 0x7FFF);
   765 				break;
   766 			default:
   767 				return IoRead(address, 32);
   768 		}
   769 	} else {
   770 		return IoRead(address, 32);
   771 	}
   773 	return data;
   774 }/*}}}*/
   776 /**
   777  * @brief Read M68K memory, 16-bit
   778  */
   779 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
   780 {
   781 	uint16_t data = EMPTY & 0xFFFF;
   783 	// If ROMLMAP is set, force system to access ROM
   784 	if (!state.romlmap)
   785 		address |= 0x800000;
   787 	// Check access permissions
   788 	ACCESS_CHECK_RD(address, 16);
   790 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   791 		// ROM access
   792 		data = RD16(state.rom, address, ROM_SIZE - 1);
   793 	} else if (address <= 0x3fffff) {
   794 		// RAM access
   795 		uint32_t newAddr = MAP_ADDR(address);
   797 		if (newAddr <= 0x1fffff) {
   798 			// Base memory wraps around
   799 			return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
   800 		} else {
   801 			if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
   802 				return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   803 			else
   804 				return EMPTY & 0xffff;
   805 		}
   806 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   807 		// I/O register space, zone A
   808 		switch (address & 0x0F0000) {
   809 			case 0x000000:				// Map RAM access
   810 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
   811 				data = RD16(state.map, address, 0x7FF);
   812 				break;
   813 			case 0x020000:				// Video RAM
   814 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
   815 				data = RD16(state.vram, address, 0x7FFF);
   816 				break;
   817 			default:
   818 				data = IoRead(address, 16);
   819 		}
   820 	} else {
   821 		data = IoRead(address, 16);
   822 	}
   824 	return data;
   825 }/*}}}*/
   827 /**
   828  * @brief Read M68K memory, 8-bit
   829  */
   830 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
   831 {
   832 	uint8_t data = EMPTY & 0xFF;
   834 	// If ROMLMAP is set, force system to access ROM
   835 	if (!state.romlmap)
   836 		address |= 0x800000;
   838 	// Check access permissions
   839 	ACCESS_CHECK_RD(address, 8);
   841 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   842 		// ROM access
   843 		data = RD8(state.rom, address, ROM_SIZE - 1);
   844 	} else if (address <= 0x3fffff) {
   845 		// RAM access
   846 		uint32_t newAddr = MAP_ADDR(address);
   848 		if (newAddr <= 0x1fffff) {
   849 			// Base memory wraps around
   850 			return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
   851 		} else {
   852 			if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
   853 				return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   854 			else
   855 				return EMPTY & 0xff;
   856 		}
   857 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   858 		// I/O register space, zone A
   859 		switch (address & 0x0F0000) {
   860 			case 0x000000:				// Map RAM access
   861 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
   862 				data = RD8(state.map, address, 0x7FF);
   863 				break;
   864 			case 0x020000:				// Video RAM
   865 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
   866 				data = RD8(state.vram, address, 0x7FFF);
   867 				break;
   868 			default:
   869 				data = IoRead(address, 8);
   870 		}
   871 	} else {
   872 		data = IoRead(address, 8);
   873 	}
   875 	return data;
   876 }/*}}}*/
   878 /**
   879  * @brief Write M68K memory, 32-bit
   880  */
   881 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
   882 {
   883 	// If ROMLMAP is set, force system to access ROM
   884 	if (!state.romlmap)
   885 		address |= 0x800000;
   887 	// Check access permissions
   888 	ACCESS_CHECK_WR(address, 32);
   890 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   891 		// ROM access
   892 	} else if (address <= 0x3FFFFF) {
   893 		// RAM access
   894 		uint32_t newAddr = MAP_ADDR(address);
   896 		if (newAddr <= 0x1fffff) {
   897 			if (newAddr < state.base_ram_size) {
   898 				WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
   899 			}
   900 		} else {
   901 			if ((newAddr - 0x200000) < state.exp_ram_size) {
   902 				WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   903 			}
   904 		}
   905 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   906 		// I/O register space, zone A
   907 		switch (address & 0x0F0000) {
   908 			case 0x000000:				// Map RAM access
   909 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X\n", address);
   910 				WR32(state.map, address, 0x7FF, value);
   911 				break;
   912 			case 0x020000:				// Video RAM
   913 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X\n", address);
   914 				WR32(state.vram, address, 0x7FFF, value);
   915 				break;
   916 			default:
   917 				IoWrite(address, value, 32);
   918 		}
   919 	} else {
   920 		IoWrite(address, value, 32);
   921 	}
   922 }/*}}}*/
   924 /**
   925  * @brief Write M68K memory, 16-bit
   926  */
   927 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
   928 {
   929 	// If ROMLMAP is set, force system to access ROM
   930 	if (!state.romlmap)
   931 		address |= 0x800000;
   933 	// Check access permissions
   934 	ACCESS_CHECK_WR(address, 16);
   936 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   937 		// ROM access
   938 	} else if (address <= 0x3FFFFF) {
   939 		// RAM access
   940 		uint32_t newAddr = MAP_ADDR(address);
   942 		if (newAddr <= 0x1fffff) {
   943 			if (newAddr < state.base_ram_size) {
   944 				WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
   945 			}
   946 		} else {
   947 			if ((newAddr - 0x200000) < state.exp_ram_size) {
   948 				WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   949 			}
   950 		}
   951 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   952 		// I/O register space, zone A
   953 		switch (address & 0x0F0000) {
   954 			case 0x000000:				// Map RAM access
   955 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   956 				WR16(state.map, address, 0x7FF, value);
   957 				break;
   958 			case 0x020000:				// Video RAM
   959 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   960 				WR16(state.vram, address, 0x7FFF, value);
   961 				break;
   962 			default:
   963 				IoWrite(address, value, 16);
   964 		}
   965 	} else {
   966 		IoWrite(address, value, 16);
   967 	}
   968 }/*}}}*/
   970 /**
   971  * @brief Write M68K memory, 8-bit
   972  */
   973 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
   974 {
   975 	// If ROMLMAP is set, force system to access ROM
   976 	if (!state.romlmap)
   977 		address |= 0x800000;
   979 	// Check access permissions
   980 	ACCESS_CHECK_WR(address, 8);
   982 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   983 		// ROM access (read only!)
   984 	} else if (address <= 0x3FFFFF) {
   985 		// RAM access
   986 		uint32_t newAddr = MAP_ADDR(address);
   988 		if (newAddr <= 0x1fffff) {
   989 			if (newAddr < state.base_ram_size) {
   990 				WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
   991 			}
   992 		} else {
   993 			if ((newAddr - 0x200000) < state.exp_ram_size) {
   994 				WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   995 			}
   996 		}
   997 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   998 		// I/O register space, zone A
   999 		switch (address & 0x0F0000) {
  1000 			case 0x000000:				// Map RAM access
  1001 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
  1002 				WR8(state.map, address, 0x7FF, value);
  1003 				break;
  1004 			case 0x020000:				// Video RAM
  1005 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
  1006 				WR8(state.vram, address, 0x7FFF, value);
  1007 				break;
  1008 			default:
  1009 				IoWrite(address, value, 8);
  1011 	} else {
  1012 		IoWrite(address, value, 8);
  1014 }/*}}}*/
  1017 // for the disassembler
  1018 uint32_t m68k_read_disassembler_32(uint32_t addr)
  1020 	if (addr < 0x400000) {
  1021 		// XXX FIXME BUGBUG update this to use the new mapper macros!
  1022 		uint16_t page = (addr >> 12) & 0x3FF;
  1023 		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
  1024 		uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
  1025 		if (newAddr <= 0x1fffff) {
  1026 			if (newAddr >= state.base_ram_size)
  1027 				return EMPTY;
  1028 			else
  1029 				return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
  1030 		} else {
  1031 			if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
  1032 				return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
  1033 			else
  1034 				return EMPTY;
  1036 	} else {
  1037 		LOG("WARNING: Disassembler RD32 out of range 0x%08X\n", addr);
  1038 		return EMPTY;
  1042 uint32_t m68k_read_disassembler_16(uint32_t addr)
  1044 	if (addr < 0x400000) {
  1045 		uint16_t page = (addr >> 12) & 0x3FF;
  1046 		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
  1047 		uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
  1048 		if (newAddr <= 0x1fffff) {
  1049 			if (newAddr >= state.base_ram_size)
  1050 				return EMPTY & 0xffff;
  1051 			else
  1052 				return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
  1053 		} else {
  1054 			if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
  1055 				return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
  1056 			else
  1057 				return EMPTY & 0xffff;
  1059 	} else {
  1060 		LOG("WARNING: Disassembler RD16 out of range 0x%08X\n", addr);
  1061 		return EMPTY & 0xffff;
  1065 uint32_t m68k_read_disassembler_8 (uint32_t addr)
  1067 	if (addr < 0x400000) {
  1068 		uint16_t page = (addr >> 12) & 0x3FF;
  1069 		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
  1070 		uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
  1071 		if (newAddr <= 0x1fffff) {
  1072 			if (newAddr >= state.base_ram_size)
  1073 				return EMPTY & 0xff;
  1074 			else
  1075 				return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
  1076 		} else {
  1077 			if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
  1078 				return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
  1079 			else
  1080 				return EMPTY & 0xff;
  1082 	} else {
  1083 		LOG("WARNING: Disassembler RD8 out of range 0x%08X\n", addr);
  1084 		return EMPTY & 0xff;