src/memory.c

Thu, 02 Dec 2010 23:03:13 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Thu, 02 Dec 2010 23:03:13 +0000
changeset 40
239bc48590ba
child 43
4d59e4ceef52
permissions
-rw-r--r--

move memory access and mapping functions into memory.[ch]

This is to tidy up main.c...

     1 #include <stdio.h>
     2 #include <stdlib.h>
     3 #include <stdint.h>
     4 #include <stdbool.h>
     5 #include "musashi/m68k.h"
     6 #include "state.h"
     7 #include "memory.h"
     9 /******************
    10  * Memory mapping
    11  ******************/
    13 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
    15 uint32_t mapAddr(uint32_t addr, bool writing)
    16 {
    17 	if (addr < 0x400000) {
    18 		// RAM access. Check against the Map RAM
    19 		// Start by getting the original page address
    20 		uint16_t page = (addr >> 12) & 0x3FF;
    22 		// Look it up in the map RAM and get the physical page address
    23 		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
    25 		// Update the Page Status bits
    26 		uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
    27 		if (pagebits != 0) {
    28 			if (writing)
    29 				state.map[page*2] |= 0x60;		// Page written to (dirty)
    30 			else
    31 				state.map[page*2] |= 0x40;		// Page accessed but not written
    32 		}
    34 		// Return the address with the new physical page spliced in
    35 		return (new_page_addr << 12) + (addr & 0xFFF);
    36 	} else {
    37 		// I/O, VRAM or MapRAM space; no mapping is performed or required
    38 		// TODO: assert here?
    39 		return addr;
    40 	}
    41 }
    43 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)
    44 {
    45 	// Are we in Supervisor mode?
    46 	if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
    47 		// Yes. We can do anything we like.
    48 		return MEM_ALLOWED;
    50 	// If we're here, then we must be in User mode.
    51 	// Check that the user didn't access memory outside of the RAM area
    52 	if (addr >= 0x400000)
    53 		return MEM_UIE;
    55 	// This leaves us with Page Fault checking. Get the page bits for this page.
    56 	uint16_t page = (addr >> 12) & 0x3FF;
    57 	uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
    59 	// Check page is present
    60 	if ((pagebits & 0x03) == 0)
    61 		return MEM_PAGEFAULT;
    63 	// User attempt to access the kernel
    64 	// A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
    65 	if (((addr >> 19) & 0x0F) == 0)
    66 		return MEM_KERNEL;
    68 	// Check page is write enabled
    69 	if ((pagebits & 0x04) == 0)
    70 		return MEM_PAGE_NO_WE;
    72 	// Page access allowed.
    73 	return MEM_ALLOWED;
    74 }
    76 #undef MAPRAM
    79 /********************************************************
    80  * m68k memory read/write support functions for Musashi
    81  ********************************************************/
    83 /**
    84  * @brief	Check memory access permissions for a write operation.
    85  * @note	This used to be a single macro (merged with ACCESS_CHECK_RD), but
    86  * 			gcc throws warnings when you have a return-with-value in a void
    87  * 			function, even if the return-with-value is completely unreachable.
    88  * 			Similarly it doesn't like it if you have a return without a value
    89  * 			in a non-void function, even if it's impossible to ever reach the
    90  * 			return-with-no-value. UGH!
    91  */
    92 #define ACCESS_CHECK_WR(address, bits) do {							\
    93 		bool fault = false;											\
    94 		/* MEM_STATUS st; */										\
    95 		switch (checkMemoryAccess(address, true)) {					\
    96 			case MEM_ALLOWED:										\
    97 				/* Access allowed */								\
    98 				break;												\
    99 			case MEM_PAGEFAULT:										\
   100 				/* Page fault */									\
   101 				state.genstat = 0x8FFF;								\
   102 				fault = true;										\
   103 				break;												\
   104 			case MEM_UIE:											\
   105 				/* User access to memory above 4MB */				\
   106 				state.genstat = 0x9EFF;								\
   107 				fault = true;										\
   108 				break;												\
   109 			case MEM_KERNEL:										\
   110 			case MEM_PAGE_NO_WE:									\
   111 				/* kernel access or page not write enabled */		\
   112 				/* TODO: which regs need setting? */				\
   113 				fault = true;										\
   114 				break;												\
   115 		}															\
   116 																	\
   117 		if (fault) {												\
   118 			if (bits >= 16)											\
   119 				state.bsr0 = 0x7F00;								\
   120 			else													\
   121 				state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00;		\
   122 			state.bsr0 |= (address >> 16);							\
   123 			state.bsr1 = address & 0xffff;							\
   124 			printf("ERR: BusError WR\n");							\
   125 			m68k_pulse_bus_error();									\
   126 			return;													\
   127 		}															\
   128 	} while (false)
   130 /**
   131  * @brief Check memory access permissions for a read operation.
   132  * @note	This used to be a single macro (merged with ACCESS_CHECK_WR), but
   133  * 			gcc throws warnings when you have a return-with-value in a void
   134  * 			function, even if the return-with-value is completely unreachable.
   135  * 			Similarly it doesn't like it if you have a return without a value
   136  * 			in a non-void function, even if it's impossible to ever reach the
   137  * 			return-with-no-value. UGH!
   138  */
   139 #define ACCESS_CHECK_RD(address, bits) do {							\
   140 		bool fault = false;											\
   141 		/* MEM_STATUS st; */										\
   142 		switch (checkMemoryAccess(address, false)) {				\
   143 			case MEM_ALLOWED:										\
   144 				/* Access allowed */								\
   145 				break;												\
   146 			case MEM_PAGEFAULT:										\
   147 				/* Page fault */									\
   148 				state.genstat = 0x8FFF;								\
   149 				fault = true;										\
   150 				break;												\
   151 			case MEM_UIE:											\
   152 				/* User access to memory above 4MB */				\
   153 				state.genstat = 0x9EFF;								\
   154 				fault = true;										\
   155 				break;												\
   156 			case MEM_KERNEL:										\
   157 			case MEM_PAGE_NO_WE:									\
   158 				/* kernel access or page not write enabled */		\
   159 				/* TODO: which regs need setting? */				\
   160 				fault = true;										\
   161 				break;												\
   162 		}															\
   163 																	\
   164 		if (fault) {												\
   165 			if (bits >= 16)											\
   166 				state.bsr0 = 0x7F00;								\
   167 			else													\
   168 				state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00;		\
   169 			state.bsr0 |= (address >> 16);							\
   170 			state.bsr1 = address & 0xffff;							\
   171 			printf("ERR: BusError RD\n");							\
   172 			m68k_pulse_bus_error();									\
   173 			return 0xFFFFFFFF;										\
   174 		}															\
   175 	} while (false)
   177 // Logging macros
   178 #define LOG_NOT_HANDLED_R(bits)																	\
   179 	do {																						\
   180 		if (!handled)																			\
   181 			printf("unhandled read%02d, addr=0x%08X\n", bits, address);							\
   182 	} while (0);
   184 #define LOG_NOT_HANDLED_W(bits)																	\
   185 	do {																						\
   186 		if (!handled)																			\
   187 			printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, value);	\
   188 	} while (0);
   190 /**
   191  * @brief Read M68K memory, 32-bit
   192  */
   193 uint32_t m68k_read_memory_32(uint32_t address)
   194 {
   195 	uint32_t data = 0xFFFFFFFF;
   196 	bool handled = false;
   198 	// If ROMLMAP is set, force system to access ROM
   199 	if (!state.romlmap)
   200 		address |= 0x800000;
   202 	// Check access permissions
   203 	ACCESS_CHECK_RD(address, 32);
   205 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   206 		// ROM access
   207 		data = RD32(state.rom, address, ROM_SIZE - 1);
   208 		handled = true;
   209 	} else if (address <= (state.ram_size - 1)) {
   210 		// RAM access
   211 		data = RD32(state.ram, mapAddr(address, false), state.ram_size - 1);
   212 		handled = true;
   213 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   214 		// I/O register space, zone A
   215 		switch (address & 0x0F0000) {
   216 			case 0x000000:				// Map RAM access
   217 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
   218 				data = RD32(state.map, address, 0x7FF);
   219 				handled = true;
   220 				break;
   221 			case 0x010000:				// General Status Register
   222 				data = ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
   223 				handled = true;
   224 				break;
   225 			case 0x020000:				// Video RAM
   226 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
   227 				data = RD32(state.vram, address, 0x7FFF);
   228 				handled = true;
   229 				break;
   230 			case 0x030000:				// Bus Status Register 0
   231 				data = ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
   232 				handled = true;
   233 				break;
   234 			case 0x040000:				// Bus Status Register 1
   235 				data = ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
   236 				handled = true;
   237 				break;
   238 			case 0x050000:				// Phone status
   239 				break;
   240 			case 0x060000:				// DMA Count
   241 				break;
   242 			case 0x070000:				// Line Printer Status Register
   243 				break;
   244 			case 0x080000:				// Real Time Clock
   245 				break;
   246 			case 0x090000:				// Phone registers
   247 				switch (address & 0x0FF000) {
   248 					case 0x090000:		// Handset relay
   249 					case 0x098000:
   250 						break;
   251 					case 0x091000:		// Line select 2
   252 					case 0x099000:
   253 						break;
   254 					case 0x092000:		// Hook relay 1
   255 					case 0x09A000:
   256 						break;
   257 					case 0x093000:		// Hook relay 2
   258 					case 0x09B000:
   259 						break;
   260 					case 0x094000:		// Line 1 hold
   261 					case 0x09C000:
   262 						break;
   263 					case 0x095000:		// Line 2 hold
   264 					case 0x09D000:
   265 						break;
   266 					case 0x096000:		// Line 1 A-lead
   267 					case 0x09E000:
   268 						break;
   269 					case 0x097000:		// Line 2 A-lead
   270 					case 0x09F000:
   271 						break;
   272 				}
   273 				break;
   274 			case 0x0A0000:				// Miscellaneous Control Register
   275 				break;
   276 			case 0x0B0000:				// TM/DIALWR
   277 				break;
   278 			case 0x0C0000:				// CSR
   279 				break;
   280 			case 0x0D0000:				// DMA Address Register
   281 				break;
   282 			case 0x0E0000:				// Disk Control Register
   283 				break;
   284 			case 0x0F0000:				// Line Printer Data Register
   285 				break;
   286 		}
   287 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   288 		// I/O register space, zone B
   289 		switch (address & 0xF00000) {
   290 			case 0xC00000:				// Expansion slots
   291 			case 0xD00000:
   292 				switch (address & 0xFC0000) {
   293 					case 0xC00000:		// Expansion slot 0
   294 					case 0xC40000:		// Expansion slot 1
   295 					case 0xC80000:		// Expansion slot 2
   296 					case 0xCC0000:		// Expansion slot 3
   297 					case 0xD00000:		// Expansion slot 4
   298 					case 0xD40000:		// Expansion slot 5
   299 					case 0xD80000:		// Expansion slot 6
   300 					case 0xDC0000:		// Expansion slot 7
   301 						fprintf(stderr, "NOTE: RD32 from expansion card space, addr=0x%08X\n", address);
   302 						break;
   303 				}
   304 				break;
   305 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   306 			case 0xF00000:
   307 				switch (address & 0x070000) {
   308 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   309 						break;
   310 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   311 						break;
   312 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   313 						break;
   314 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   315 						break;
   316 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   317 						switch (address & 0x077000) {
   318 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   319 								break;
   320 							case 0x041000:		// [ef][4c][19]xxx ==> P1E
   321 								break;
   322 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   323 								break;
   324 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   325 								break;
   326 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   327 								break;
   328 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   329 								break;
   330 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   331 								break;
   332 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   333 								break;
   334 						}
   335 						break;
   336 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   337 						break;
   338 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   339 						switch (address & 0x07F000) {
   340 							default:
   341 								break;
   342 						}
   343 						break;
   344 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   345 						break;
   346 				}
   347 		}
   348 	}
   350 	LOG_NOT_HANDLED_R(32);
   351 	return data;
   352 }
   354 /**
   355  * @brief Read M68K memory, 16-bit
   356  */
   357 uint32_t m68k_read_memory_16(uint32_t address)
   358 {
   359 	uint16_t data = 0xFFFF;
   360 	bool handled = false;
   362 	// If ROMLMAP is set, force system to access ROM
   363 	if (!state.romlmap)
   364 		address |= 0x800000;
   366 	// Check access permissions
   367 	ACCESS_CHECK_RD(address, 16);
   369 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   370 		// ROM access
   371 		data = RD16(state.rom, address, ROM_SIZE - 1);
   372 		handled = true;
   373 	} else if (address <= (state.ram_size - 1)) {
   374 		// RAM access
   375 		data = RD16(state.ram, mapAddr(address, false), state.ram_size - 1);
   376 		handled = true;
   377 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   378 		// I/O register space, zone A
   379 		switch (address & 0x0F0000) {
   380 			case 0x000000:				// Map RAM access
   381 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
   382 				data = RD16(state.map, address, 0x7FF);
   383 				handled = true;
   384 				break;
   385 			case 0x010000:				// General Status Register
   386 				data = state.genstat;
   387 				handled = true;
   388 				break;
   389 			case 0x020000:				// Video RAM
   390 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
   391 				data = RD16(state.vram, address, 0x7FFF);
   392 				handled = true;
   393 				break;
   394 			case 0x030000:				// Bus Status Register 0
   395 				data = state.bsr0;
   396 				handled = true;
   397 				break;
   398 			case 0x040000:				// Bus Status Register 1
   399 				data = state.bsr1;
   400 				handled = true;
   401 				break;
   402 			case 0x050000:				// Phone status
   403 				break;
   404 			case 0x060000:				// DMA Count
   405 				break;
   406 			case 0x070000:				// Line Printer Status Register
   407 				break;
   408 			case 0x080000:				// Real Time Clock
   409 				break;
   410 			case 0x090000:				// Phone registers
   411 				switch (address & 0x0FF000) {
   412 					case 0x090000:		// Handset relay
   413 					case 0x098000:
   414 						break;
   415 					case 0x091000:		// Line select 2
   416 					case 0x099000:
   417 						break;
   418 					case 0x092000:		// Hook relay 1
   419 					case 0x09A000:
   420 						break;
   421 					case 0x093000:		// Hook relay 2
   422 					case 0x09B000:
   423 						break;
   424 					case 0x094000:		// Line 1 hold
   425 					case 0x09C000:
   426 						break;
   427 					case 0x095000:		// Line 2 hold
   428 					case 0x09D000:
   429 						break;
   430 					case 0x096000:		// Line 1 A-lead
   431 					case 0x09E000:
   432 						break;
   433 					case 0x097000:		// Line 2 A-lead
   434 					case 0x09F000:
   435 						break;
   436 				}
   437 				break;
   438 			case 0x0A0000:				// Miscellaneous Control Register
   439 				break;
   440 			case 0x0B0000:				// TM/DIALWR
   441 				break;
   442 			case 0x0C0000:				// CSR
   443 				break;
   444 			case 0x0D0000:				// DMA Address Register
   445 				break;
   446 			case 0x0E0000:				// Disk Control Register
   447 				break;
   448 			case 0x0F0000:				// Line Printer Data Register
   449 				break;
   450 		}
   451 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   452 		// I/O register space, zone B
   453 		switch (address & 0xF00000) {
   454 			case 0xC00000:				// Expansion slots
   455 			case 0xD00000:
   456 				switch (address & 0xFC0000) {
   457 					case 0xC00000:		// Expansion slot 0
   458 					case 0xC40000:		// Expansion slot 1
   459 					case 0xC80000:		// Expansion slot 2
   460 					case 0xCC0000:		// Expansion slot 3
   461 					case 0xD00000:		// Expansion slot 4
   462 					case 0xD40000:		// Expansion slot 5
   463 					case 0xD80000:		// Expansion slot 6
   464 					case 0xDC0000:		// Expansion slot 7
   465 						fprintf(stderr, "NOTE: RD16 from expansion card space, addr=0x%08X\n", address);
   466 						break;
   467 				}
   468 				break;
   469 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   470 			case 0xF00000:
   471 				switch (address & 0x070000) {
   472 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   473 						break;
   474 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   475 						break;
   476 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   477 						break;
   478 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   479 						break;
   480 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   481 						switch (address & 0x077000) {
   482 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   483 								break;
   484 							case 0x041000:		// [ef][4c][19]xxx ==> P1E
   485 								break;
   486 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   487 								break;
   488 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   489 								break;
   490 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   491 								break;
   492 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   493 								break;
   494 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   495 								break;
   496 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   497 								break;
   498 						}
   499 						break;
   500 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   501 						break;
   502 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   503 						switch (address & 0x07F000) {
   504 							default:
   505 								break;
   506 						}
   507 						break;
   508 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   509 						break;
   510 				}
   511 		}
   512 	}
   514 	LOG_NOT_HANDLED_R(32);
   515 	return data;
   516 }
   518 /**
   519  * @brief Read M68K memory, 8-bit
   520  */
   521 uint32_t m68k_read_memory_8(uint32_t address)
   522 {
   523 	uint8_t data = 0xFF;
   524 	bool handled = false;
   526 	// If ROMLMAP is set, force system to access ROM
   527 	if (!state.romlmap)
   528 		address |= 0x800000;
   530 	// Check access permissions
   531 	ACCESS_CHECK_RD(address, 8);
   533 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   534 		// ROM access
   535 		data = RD8(state.rom, address, ROM_SIZE - 1);
   536 		handled = true;
   537 	} else if (address <= (state.ram_size - 1)) {
   538 		// RAM access
   539 		data = RD8(state.ram, mapAddr(address, false), state.ram_size - 1);
   540 		handled = true;
   541 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   542 		// I/O register space, zone A
   543 		switch (address & 0x0F0000) {
   544 			case 0x000000:				// Map RAM access
   545 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
   546 				data = RD8(state.map, address, 0x7FF);
   547 				handled = true;
   548 				break;
   549 			case 0x010000:				// General Status Register
   550 				if ((address & 1) == 0)
   551 					data = (state.genstat >> 8) & 0xff;
   552 				else
   553 					data = (state.genstat)      & 0xff;
   554 				handled = true;
   555 				break;
   556 			case 0x020000:				// Video RAM
   557 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
   558 				data = RD8(state.vram, address, 0x7FFF);
   559 				handled = true;
   560 				break;
   561 			case 0x030000:				// Bus Status Register 0
   562 				if ((address & 1) == 0)
   563 					data = (state.bsr0 >> 8) & 0xff;
   564 				else
   565 					data = (state.bsr0)      & 0xff;
   566 				handled = true;
   567 				break;
   568 			case 0x040000:				// Bus Status Register 1
   569 				if ((address & 1) == 0)
   570 					data = (state.bsr1 >> 8) & 0xff;
   571 				else
   572 					data = (state.bsr1)      & 0xff;
   573 				handled = true;
   574 				break;
   575 			case 0x050000:				// Phone status
   576 				break;
   577 			case 0x060000:				// DMA Count
   578 				break;
   579 			case 0x070000:				// Line Printer Status Register
   580 				break;
   581 			case 0x080000:				// Real Time Clock
   582 				break;
   583 			case 0x090000:				// Phone registers
   584 				switch (address & 0x0FF000) {
   585 					case 0x090000:		// Handset relay
   586 					case 0x098000:
   587 						break;
   588 					case 0x091000:		// Line select 2
   589 					case 0x099000:
   590 						break;
   591 					case 0x092000:		// Hook relay 1
   592 					case 0x09A000:
   593 						break;
   594 					case 0x093000:		// Hook relay 2
   595 					case 0x09B000:
   596 						break;
   597 					case 0x094000:		// Line 1 hold
   598 					case 0x09C000:
   599 						break;
   600 					case 0x095000:		// Line 2 hold
   601 					case 0x09D000:
   602 						break;
   603 					case 0x096000:		// Line 1 A-lead
   604 					case 0x09E000:
   605 						break;
   606 					case 0x097000:		// Line 2 A-lead
   607 					case 0x09F000:
   608 						break;
   609 				}
   610 				break;
   611 			case 0x0A0000:				// Miscellaneous Control Register
   612 				break;
   613 			case 0x0B0000:				// TM/DIALWR
   614 				break;
   615 			case 0x0C0000:				// CSR
   616 				break;
   617 			case 0x0D0000:				// DMA Address Register
   618 				break;
   619 			case 0x0E0000:				// Disk Control Register
   620 				break;
   621 			case 0x0F0000:				// Line Printer Data Register
   622 				break;
   623 		}
   624 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   625 		// I/O register space, zone B
   626 		switch (address & 0xF00000) {
   627 			case 0xC00000:				// Expansion slots
   628 			case 0xD00000:
   629 				switch (address & 0xFC0000) {
   630 					case 0xC00000:		// Expansion slot 0
   631 					case 0xC40000:		// Expansion slot 1
   632 					case 0xC80000:		// Expansion slot 2
   633 					case 0xCC0000:		// Expansion slot 3
   634 					case 0xD00000:		// Expansion slot 4
   635 					case 0xD40000:		// Expansion slot 5
   636 					case 0xD80000:		// Expansion slot 6
   637 					case 0xDC0000:		// Expansion slot 7
   638 						fprintf(stderr, "NOTE: RD8 from expansion card space, addr=0x%08X\n", address);
   639 						break;
   640 				}
   641 				break;
   642 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   643 			case 0xF00000:
   644 				switch (address & 0x070000) {
   645 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   646 						break;
   647 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   648 						break;
   649 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   650 						break;
   651 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   652 						break;
   653 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   654 						switch (address & 0x077000) {
   655 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   656 								break;
   657 							case 0x041000:		// [ef][4c][19]xxx ==> P1E
   658 								break;
   659 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   660 								break;
   661 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   662 								break;
   663 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   664 								break;
   665 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   666 								break;
   667 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   668 								break;
   669 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   670 								break;
   671 						}
   672 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   673 						break;
   674 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   675 						switch (address & 0x07F000) {
   676 							default:
   677 								break;
   678 						}
   679 						break;
   680 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   681 						break;
   682 				}
   683 		}
   684 	}
   686 	LOG_NOT_HANDLED_R(8);
   688 	return data;
   689 }
   691 /**
   692  * @brief Write M68K memory, 32-bit
   693  */
   694 void m68k_write_memory_32(uint32_t address, uint32_t value)
   695 {
   696 	bool handled = false;
   698 	// If ROMLMAP is set, force system to access ROM
   699 	if (!state.romlmap)
   700 		address |= 0x800000;
   702 	// Check access permissions
   703 	ACCESS_CHECK_WR(address, 32);
   705 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   706 		// ROM access
   707 		handled = true;
   708 	} else if (address <= (state.ram_size - 1)) {
   709 		// RAM access
   710 		WR32(state.ram, mapAddr(address, false), state.ram_size - 1, value);
   711 		handled = true;
   712 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   713 		// I/O register space, zone A
   714 		switch (address & 0x0F0000) {
   715 			case 0x000000:				// Map RAM access
   716 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
   717 				WR32(state.map, address, 0x7FF, value);
   718 				handled = true;
   719 				break;
   720 			case 0x010000:				// General Status Register
   721 				state.genstat = (value & 0xffff);
   722 				handled = true;
   723 				break;
   724 			case 0x020000:				// Video RAM
   725 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
   726 				WR32(state.vram, address, 0x7FFF, value);
   727 				handled = true;
   728 				break;
   729 			case 0x030000:				// Bus Status Register 0
   730 				break;
   731 			case 0x040000:				// Bus Status Register 1
   732 				break;
   733 			case 0x050000:				// Phone status
   734 				break;
   735 			case 0x060000:				// DMA Count
   736 				break;
   737 			case 0x070000:				// Line Printer Status Register
   738 				break;
   739 			case 0x080000:				// Real Time Clock
   740 				break;
   741 			case 0x090000:				// Phone registers
   742 				switch (address & 0x0FF000) {
   743 					case 0x090000:		// Handset relay
   744 					case 0x098000:
   745 						break;
   746 					case 0x091000:		// Line select 2
   747 					case 0x099000:
   748 						break;
   749 					case 0x092000:		// Hook relay 1
   750 					case 0x09A000:
   751 						break;
   752 					case 0x093000:		// Hook relay 2
   753 					case 0x09B000:
   754 						break;
   755 					case 0x094000:		// Line 1 hold
   756 					case 0x09C000:
   757 						break;
   758 					case 0x095000:		// Line 2 hold
   759 					case 0x09D000:
   760 						break;
   761 					case 0x096000:		// Line 1 A-lead
   762 					case 0x09E000:
   763 						break;
   764 					case 0x097000:		// Line 2 A-lead
   765 					case 0x09F000:
   766 						break;
   767 				}
   768 				break;
   769 			case 0x0A0000:				// Miscellaneous Control Register
   770 				break;
   771 			case 0x0B0000:				// TM/DIALWR
   772 				break;
   773 			case 0x0C0000:				// CSR
   774 				break;
   775 			case 0x0D0000:				// DMA Address Register
   776 				break;
   777 			case 0x0E0000:				// Disk Control Register
   778 				break;
   779 			case 0x0F0000:				// Line Printer Data Register
   780 				break;
   781 		}
   782 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   783 		// I/O register space, zone B
   784 		switch (address & 0xF00000) {
   785 			case 0xC00000:				// Expansion slots
   786 			case 0xD00000:
   787 				switch (address & 0xFC0000) {
   788 					case 0xC00000:		// Expansion slot 0
   789 					case 0xC40000:		// Expansion slot 1
   790 					case 0xC80000:		// Expansion slot 2
   791 					case 0xCC0000:		// Expansion slot 3
   792 					case 0xD00000:		// Expansion slot 4
   793 					case 0xD40000:		// Expansion slot 5
   794 					case 0xD80000:		// Expansion slot 6
   795 					case 0xDC0000:		// Expansion slot 7
   796 						fprintf(stderr, "NOTE: WR32 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
   797 						handled = true;
   798 						break;
   799 				}
   800 				break;
   801 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   802 			case 0xF00000:
   803 				switch (address & 0x070000) {
   804 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   805 						break;
   806 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   807 						break;
   808 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   809 						break;
   810 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   811 						break;
   812 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   813 						switch (address & 0x077000) {
   814 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   815 								break;
   816 							case 0x041000:		// [ef][4c][19]xxx ==> P1E
   817 								break;
   818 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   819 								break;
   820 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   821 								state.romlmap = ((value & 0x8000) == 0x8000);
   822 								break;
   823 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   824 								break;
   825 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   826 								break;
   827 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   828 								break;
   829 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   830 								break;
   831 						}
   832 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   833 						break;
   834 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   835 						switch (address & 0x07F000) {
   836 							default:
   837 								break;
   838 						}
   839 						break;
   840 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   841 						break;
   842 				}
   843 		}
   844 	}
   846 	LOG_NOT_HANDLED_W(32);
   847 }
   849 /**
   850  * @brief Write M68K memory, 16-bit
   851  */
   852 void m68k_write_memory_16(uint32_t address, uint32_t value)
   853 {
   854 	bool handled = false;
   856 	// If ROMLMAP is set, force system to access ROM
   857 	if (!state.romlmap)
   858 		address |= 0x800000;
   860 	// Check access permissions
   861 	ACCESS_CHECK_WR(address, 16);
   863 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   864 		// ROM access
   865 		handled = true;
   866 	} else if (address <= (state.ram_size - 1)) {
   867 		// RAM access
   868 		WR16(state.ram, mapAddr(address, false), state.ram_size - 1, value);
   869 		handled = true;
   870 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   871 		// I/O register space, zone A
   872 		switch (address & 0x0F0000) {
   873 			case 0x000000:				// Map RAM access
   874 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   875 				WR16(state.map, address, 0x7FF, value);
   876 				handled = true;
   877 				break;
   878 			case 0x010000:				// General Status Register (read only)
   879 				handled = true;
   880 				break;
   881 			case 0x020000:				// Video RAM
   882 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   883 				WR16(state.vram, address, 0x7FFF, value);
   884 				handled = true;
   885 				break;
   886 			case 0x030000:				// Bus Status Register 0 (read only)
   887 				handled = true;
   888 				break;
   889 			case 0x040000:				// Bus Status Register 1 (read only)
   890 				handled = true;
   891 				break;
   892 			case 0x050000:				// Phone status
   893 				break;
   894 			case 0x060000:				// DMA Count
   895 				break;
   896 			case 0x070000:				// Line Printer Status Register
   897 				break;
   898 			case 0x080000:				// Real Time Clock
   899 				break;
   900 			case 0x090000:				// Phone registers
   901 				switch (address & 0x0FF000) {
   902 					case 0x090000:		// Handset relay
   903 					case 0x098000:
   904 						break;
   905 					case 0x091000:		// Line select 2
   906 					case 0x099000:
   907 						break;
   908 					case 0x092000:		// Hook relay 1
   909 					case 0x09A000:
   910 						break;
   911 					case 0x093000:		// Hook relay 2
   912 					case 0x09B000:
   913 						break;
   914 					case 0x094000:		// Line 1 hold
   915 					case 0x09C000:
   916 						break;
   917 					case 0x095000:		// Line 2 hold
   918 					case 0x09D000:
   919 						break;
   920 					case 0x096000:		// Line 1 A-lead
   921 					case 0x09E000:
   922 						break;
   923 					case 0x097000:		// Line 2 A-lead
   924 					case 0x09F000:
   925 						break;
   926 				}
   927 				break;
   928 			case 0x0A0000:				// Miscellaneous Control Register
   929 				break;
   930 			case 0x0B0000:				// TM/DIALWR
   931 				break;
   932 			case 0x0C0000:				// CSR
   933 				break;
   934 			case 0x0D0000:				// DMA Address Register
   935 				break;
   936 			case 0x0E0000:				// Disk Control Register
   937 				break;
   938 			case 0x0F0000:				// Line Printer Data Register
   939 				break;
   940 		}
   941 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   942 		// I/O register space, zone B
   943 		switch (address & 0xF00000) {
   944 			case 0xC00000:				// Expansion slots
   945 			case 0xD00000:
   946 				switch (address & 0xFC0000) {
   947 					case 0xC00000:		// Expansion slot 0
   948 					case 0xC40000:		// Expansion slot 1
   949 					case 0xC80000:		// Expansion slot 2
   950 					case 0xCC0000:		// Expansion slot 3
   951 					case 0xD00000:		// Expansion slot 4
   952 					case 0xD40000:		// Expansion slot 5
   953 					case 0xD80000:		// Expansion slot 6
   954 					case 0xDC0000:		// Expansion slot 7
   955 						fprintf(stderr, "NOTE: WR16 to expansion card space, addr=0x%08X, data=0x%04X\n", address, value);
   956 						break;
   957 				}
   958 				break;
   959 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   960 			case 0xF00000:
   961 				switch (address & 0x070000) {
   962 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   963 						break;
   964 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   965 						break;
   966 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   967 						break;
   968 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   969 						break;
   970 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   971 						switch (address & 0x077000) {
   972 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   973 								break;
   974 							case 0x041000:		// [ef][4c][19]xxx ==> P1E
   975 								break;
   976 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   977 								break;
   978 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   979 								state.romlmap = ((value & 0x8000) == 0x8000);
   980 								handled = true;
   981 								break;
   982 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   983 								break;
   984 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   985 								break;
   986 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   987 								break;
   988 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   989 								break;
   990 						}
   991 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   992 						break;
   993 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   994 						switch (address & 0x07F000) {
   995 							default:
   996 								break;
   997 						}
   998 						break;
   999 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
  1000 						break;
  1005 	LOG_NOT_HANDLED_W(16);
  1008 /**
  1009  * @brief Write M68K memory, 8-bit
  1010  */
  1011 void m68k_write_memory_8(uint32_t address, uint32_t value)
  1013 	bool handled = false;
  1015 	// If ROMLMAP is set, force system to access ROM
  1016 	if (!state.romlmap)
  1017 		address |= 0x800000;
  1019 	// Check access permissions
  1020 	ACCESS_CHECK_WR(address, 8);
  1022 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
  1023 		// ROM access (read only!)
  1024 		handled = true;
  1025 	} else if (address <= (state.ram_size - 1)) {
  1026 		// RAM access
  1027 		WR8(state.ram, mapAddr(address, false), state.ram_size - 1, value);
  1028 		handled = true;
  1029 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
  1030 		// I/O register space, zone A
  1031 		switch (address & 0x0F0000) {
  1032 			case 0x000000:				// Map RAM access
  1033 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=%08X, data=%02X\n", address, value);
  1034 				WR8(state.map, address, 0x7FF, value);
  1035 				handled = true;
  1036 				break;
  1037 			case 0x010000:				// General Status Register
  1038 				handled = true;
  1039 				break;
  1040 			case 0x020000:				// Video RAM
  1041 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=%08X\n, data=0x%02X", address, value);
  1042 				WR8(state.vram, address, 0x7FFF, value);
  1043 				handled = true;
  1044 				break;
  1045 			case 0x030000:				// Bus Status Register 0
  1046 				handled = true;
  1047 				break;
  1048 			case 0x040000:				// Bus Status Register 1
  1049 				handled = true;
  1050 				break;
  1051 			case 0x050000:				// Phone status
  1052 				break;
  1053 			case 0x060000:				// DMA Count
  1054 				break;
  1055 			case 0x070000:				// Line Printer Status Register
  1056 				break;
  1057 			case 0x080000:				// Real Time Clock
  1058 				break;
  1059 			case 0x090000:				// Phone registers
  1060 				switch (address & 0x0FF000) {
  1061 					case 0x090000:		// Handset relay
  1062 					case 0x098000:
  1063 						break;
  1064 					case 0x091000:		// Line select 2
  1065 					case 0x099000:
  1066 						break;
  1067 					case 0x092000:		// Hook relay 1
  1068 					case 0x09A000:
  1069 						break;
  1070 					case 0x093000:		// Hook relay 2
  1071 					case 0x09B000:
  1072 						break;
  1073 					case 0x094000:		// Line 1 hold
  1074 					case 0x09C000:
  1075 						break;
  1076 					case 0x095000:		// Line 2 hold
  1077 					case 0x09D000:
  1078 						break;
  1079 					case 0x096000:		// Line 1 A-lead
  1080 					case 0x09E000:
  1081 						break;
  1082 					case 0x097000:		// Line 2 A-lead
  1083 					case 0x09F000:
  1084 						break;
  1086 				break;
  1087 			case 0x0A0000:				// Miscellaneous Control Register
  1088 				break;
  1089 			case 0x0B0000:				// TM/DIALWR
  1090 				break;
  1091 			case 0x0C0000:				// CSR
  1092 				break;
  1093 			case 0x0D0000:				// DMA Address Register
  1094 				break;
  1095 			case 0x0E0000:				// Disk Control Register
  1096 				break;
  1097 			case 0x0F0000:				// Line Printer Data Register
  1098 				break;
  1100 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
  1101 		// I/O register space, zone B
  1102 		switch (address & 0xF00000) {
  1103 			case 0xC00000:				// Expansion slots
  1104 			case 0xD00000:
  1105 				switch (address & 0xFC0000) {
  1106 					case 0xC00000:		// Expansion slot 0
  1107 					case 0xC40000:		// Expansion slot 1
  1108 					case 0xC80000:		// Expansion slot 2
  1109 					case 0xCC0000:		// Expansion slot 3
  1110 					case 0xD00000:		// Expansion slot 4
  1111 					case 0xD40000:		// Expansion slot 5
  1112 					case 0xD80000:		// Expansion slot 6
  1113 					case 0xDC0000:		// Expansion slot 7
  1114 						fprintf(stderr, "NOTE: WR8 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
  1115 						break;
  1117 				break;
  1118 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
  1119 			case 0xF00000:
  1120 				switch (address & 0x070000) {
  1121 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
  1122 						break;
  1123 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
  1124 						break;
  1125 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
  1126 						break;
  1127 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
  1128 						break;
  1129 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
  1130 						switch (address & 0x077000) {
  1131 							case 0x040000:		// [ef][4c][08]xxx ==> EE
  1132 								break;
  1133 							case 0x041000:		// [ef][4c][19]xxx ==> P1E
  1134 								break;
  1135 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
  1136 								break;
  1137 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
  1138 								if ((address & 1) == 0)
  1139 									state.romlmap = ((value & 0x80) == 0x80);
  1140 								handled = true;
  1141 								break;
  1142 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
  1143 								break;
  1144 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
  1145 								break;
  1146 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
  1147 								break;
  1148 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
  1149 								break;
  1151 					case 0x050000:		// [ef][5d]xxxx ==> 8274
  1152 						break;
  1153 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
  1154 						switch (address & 0x07F000) {
  1155 							default:
  1156 								break;
  1158 						break;
  1159 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
  1160 						break;
  1161 					default:
  1162 						fprintf(stderr, "NOTE: WR8 to undefined E/F-block space, addr=0x%08X, data=0x%08X\n", address, value);
  1163 						break;
  1168 	LOG_NOT_HANDLED_W(8);
  1172 // for the disassembler
  1173 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
  1174 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
  1175 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }