Fri, 18 Jan 2013 17:03:48 +0000
experimental memory mapper, not quite working
1 #include <stdio.h>
2 #include <stdlib.h>
3 #include <stdint.h>
4 #include <stdbool.h>
5 #include <assert.h>
6 #include "musashi/m68k.h"
7 #include "state.h"
8 #include "utils.h"
9 #include "memory.h"
11 // The value which will be returned if the CPU attempts to read from empty memory
12 // TODO (FIXME?) - need to figure out if R/W ops wrap around. This seems to appease the UNIX kernel and P4TEST.
13 #define EMPTY 0xFFFFFFFFUL
14 // #define EMPTY 0x55555555UL
16 /******************
17 * Memory mapping
18 ******************/
20 /// Set a page bit
21 #define MAP_SET_PAGEBIT(addr, bit) state.map[(((addr) >> 12) & 0x3FF)*2] |= (bit << 2)
22 /// Clear a page bit
23 #define MAP_CLR_PAGEBIT(addr, bit) state.map[(((addr) >> 12) & 0x3FF)*2] &= ~(bit << 2)
26 /********************************************************
27 * m68k memory read/write support functions for Musashi
28 ********************************************************/
30 /**
31 * @brief Check memory access permissions for a write operation.
32 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
33 * gcc throws warnings when you have a return-with-value in a void
34 * function, even if the return-with-value is completely unreachable.
35 * Similarly it doesn't like it if you have a return without a value
36 * in a non-void function, even if it's impossible to ever reach the
37 * return-with-no-value. UGH!
38 */
39 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
40 #define ACCESS_CHECK_WR(address, bits) \
41 do { \
42 if (access_check_cpu(address, bits, true)) { \
43 return; \
44 } \
45 } while (0)
46 /*}}}*/
48 /**
49 * @brief Check memory access permissions for a read operation.
50 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
51 * gcc throws warnings when you have a return-with-value in a void
52 * function, even if the return-with-value is completely unreachable.
53 * Similarly it doesn't like it if you have a return without a value
54 * in a non-void function, even if it's impossible to ever reach the
55 * return-with-no-value. UGH!
56 */
57 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
58 #define ACCESS_CHECK_RD(address, bits) \
59 do { \
60 if (access_check_cpu(address, bits, false)) { \
61 if (bits == 32) \
62 return EMPTY & 0xFFFFFFFF; \
63 else \
64 return EMPTY & ((1UL << bits)-1); \
65 } \
66 } while (0)
67 /*}}}*/
70 /**
71 * Update the page bits for a given memory address
72 *
73 * @param addr Memory address being accessed
74 * @param l7intr Set to <i>true</i> if a level-seven interrupt has been
75 * signalled (even if <b>ENABLE ERROR</b> isn't set).
76 * @param write Set to <i>true</i> if the address is being written to.
77 */
78 static void update_page_bits(uint32_t addr, bool l7intr, bool write)
79 {
80 bool ps0_state = false;
82 // Don't try and update pagebits for non-RAM addresses
83 if (addr > 0x3FFFFF)
84 return;
86 if (l7intr) {
87 // if (!(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
88 // FIXME FUCKUP The ruddy TRM is wrong AGAIN! If above line is uncommented, Really Bad Things Happen.
89 if ((MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
90 // Level 7 interrupt, PS0 clear, PS1 don't-care. Set PS0.
91 ps0_state = true;
92 }
93 } else {
94 // No L7 interrupt
95 if ((write && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && (MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) ||
96 (write && (MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)))
97 {
98 // No L7 interrupt, PS[1:0] = 0b01, write
99 // No L7 interrupt, PS[1:0] = 0b10, write
100 ps0_state = true;
101 }
102 }
104 #ifdef MAPRAM_BIT_TEST
105 LOG("Starting Mapram Bit Test");
106 state.map[0] = state.map[1] = 0;
107 LOG("Start = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
108 MAP_SET_PAGEBIT(0, PAGE_BIT_WE);
109 LOG("Set WE = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
110 MAP_SET_PAGEBIT(0, PAGE_BIT_PS1);
111 LOG("Set PS1 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
112 MAP_SET_PAGEBIT(0, PAGE_BIT_PS0);
113 LOG("Set PS0 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
115 MAP_CLR_PAGEBIT(0, PAGE_BIT_WE);
116 LOG("Clr WE = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
117 MAP_CLR_PAGEBIT(0, PAGE_BIT_PS1);
118 LOG("Clr PS1 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
119 MAP_CLR_PAGEBIT(0, PAGE_BIT_PS0);
120 LOG("Clr PS0 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
121 exit(-1);
122 #endif
124 uint16_t old_pagebits = MAP_PAGEBITS(addr);
126 // PS1 is always set on access
127 MAP_SET_PAGEBIT(addr, PAGE_BIT_PS1);
129 uint16_t new_pagebit1 = MAP_PAGEBITS(addr);
131 // Update PS0
132 if (ps0_state) {
133 MAP_SET_PAGEBIT(addr, PAGE_BIT_PS0);
134 } else {
135 MAP_CLR_PAGEBIT(addr, PAGE_BIT_PS0);
136 }
138 uint16_t new_pagebit2 = MAP_PAGEBITS(addr);
139 switch (addr) {
140 case 0x000000:
141 case 0x001000:
142 case 0x002000:
143 case 0x003000:
144 case 0x004000:
145 case 0x033000:
146 case 0x034000:
147 case 0x035000:
148 LOG("Addr %08X MapNew %04X Pagebit update -- ps0 %d, %02X => %02X => %02X", addr, MAPRAM_ADDR(addr), ps0_state, old_pagebits, new_pagebit1, new_pagebit2);
149 default:
150 break;
151 }
152 }
154 bool access_check_dma(void)
155 {
156 // TODO FIXME BUGBUG Sanity check - Make sure DMAC is only accessing RAM addresses
158 // DMA access check -- make sure the page is mapped in
159 if (!(MAP_PAGEBITS(state.dma_address) & PAGE_BIT_PS0) && !(MAP_PAGEBITS(state.dma_address) & PAGE_BIT_PS1)) {
160 // DMA access to page which is not mapped in.
161 // Level 7 interrupt, page fault, DMA invoked
162 state.genstat = 0xABFF
163 | (state.dma_reading ? 0x4000 : 0)
164 | (state.pie ? 0x0400 : 0);
166 // XXX: Check all this stuff.
167 state.bsr0 = 0x3C00;
168 state.bsr0 |= (state.dma_address >> 16);
169 state.bsr1 = state.dma_address & 0xffff;
171 // Update page bits for this transfer
172 update_page_bits(state.dma_address, true, !state.dma_reading);
174 // XXX: is this right?
175 // Fire a Level 7 interrupt
176 /*if (state.ee)*/ m68k_set_irq(7);
178 LOG("BUS ERROR FROM DMA: genstat=%04X, bsr0=%04X, bsr1=%04X\n", state.genstat, state.bsr0, state.bsr1);
179 return false;
180 } else {
181 // No errors. Just update the page bits.
182 update_page_bits(state.dma_address, false, !state.dma_reading);
183 return true;
184 }
185 }
187 /**
188 * Check memory access permissions for a CPU memory access.
189 *
190 * @param addr Virtual memory address being accessed (from CPU address bus).
191 * @param bits Word size of this transfer (8, 16 or 32 bits).
192 * @param write <i>true</i> if this is a write operation, <i>false</i> if it is a read operation.
193 * @return <i>true</i> if the access was denied and a level-7 interrupt and/or bus error raised.
194 * <i>false</i> if the access was allowed.
195 */
196 bool access_check_cpu(uint32_t addr, int bits, bool write)
197 {
198 bool supervisor = (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000);
199 bool fault = false;
201 // TODO FIXME BUGBUG? Do we need to check for supervisor access here?
202 if ((addr >= 0x000000) && (addr <= 0x3FFFFF) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
203 // (A) Page Fault -- user access to page which is not mapped in
204 // Level 7 Interrupt, Bus Error, regs=PAGEFAULT
205 if (write) {
206 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0);
207 } else {
208 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0);
209 }
210 fault = true;
211 } else if (!supervisor && (addr >= 0x000000) && (addr <= 0x07FFFF)) {
212 // (B) User attempted to access the kernel
213 // Level 7 Interrupt, Bus Error, regs=KERNEL
214 if (write) {
215 // XXX: BUGBUG? Is this correct?
216 state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0);
217 } else {
218 state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0);
219 }
220 fault = true;
221 } else if (!supervisor && write && (addr >= 0x000000) && (addr <= 0x3FFFFF) && !(MAP_PAGEBITS(addr) & PAGE_BIT_WE)) {
222 // (C) User attempted to write to a page which is not write enabled
223 // Level 7 Interrupt, Bus Error, regs=WRITE_EN
224 if (write) {
225 // XXX: BUGBUG? Is this correct?
226 state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0);
227 } else {
228 state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0);
229 }
230 fault = true;
231 } else if (!supervisor && (addr >= 0x400000) && (addr <= 0xFFFFFF)) {
232 // (D) UIE - user I/O exception
233 // Bus Error only, regs=UIE
234 if (write) {
235 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0);
236 } else {
237 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0);
238 }
239 fault = true;
240 }
242 // Update the page bits first
243 update_page_bits(addr, fault, write);
245 if (fault) {
246 if (bits >= 16)
247 state.bsr0 = 0x7C00;
248 else
249 state.bsr0 = (addr & 1) ? 0x7E00 : 0x7D00;
250 // FIXME? Physical or virtual address here?
251 state.bsr0 |= (addr >> 16);
252 state.bsr1 = addr & 0xffff;
254 LOG("CPU Bus Error or L7Intr while %s, vaddr %08X, map %08X, pagebits 0x%02X bsr0=%04X bsr1=%04X genstat=%04X",
255 write ? "writing" : "reading", addr,
256 MAPRAM_ADDR(addr & 0x3fffff),
257 MAP_PAGEBITS(addr & 0x3fffff),
258 state.bsr0, state.bsr1, state.genstat);
260 // FIXME? BUGBUG? Does EE disable one or both of these?
261 // /*if (state.ee)*/ m68k_set_irq(7);
262 /*if (state.ee)*/ m68k_pulse_bus_error();
263 }
265 return fault;
266 }
268 // Logging macros
269 #define LOG_NOT_HANDLED_R(bits) \
270 if (!handled) fprintf(stderr, "unhandled read%02d, addr=0x%08X\n", bits, address);
272 #define LOG_NOT_HANDLED_W(bits) \
273 if (!handled) fprintf(stderr, "unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
275 /********************************************************
276 * I/O read/write functions
277 ********************************************************/
279 /**
280 * Issue a warning if a read operation is made with an invalid size
281 */
282 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
283 {
284 assert((bits == 8) || (bits == 16) || (bits == 32));
285 if ((bits & allowed) == 0) {
286 LOG("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
287 }
288 }
290 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
291 {
292 ENFORCE_SIZE(bits, address, true, allowed, regname);
293 }
295 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
296 {
297 ENFORCE_SIZE(bits, address, false, allowed, regname);
298 }
300 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
301 {
302 bool handled = false;
304 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
305 // I/O register space, zone A
306 switch (address & 0x0F0000) {
307 case 0x010000: // General Status Register
308 if (bits == 16)
309 state.genstat = (data & 0xffff);
310 else if (bits == 8) {
311 if (address & 0)
312 state.genstat = data;
313 else
314 state.genstat = data << 8;
315 }
316 handled = true;
317 break;
318 case 0x030000: // Bus Status Register 0
319 break;
320 case 0x040000: // Bus Status Register 1
321 break;
322 case 0x050000: // Phone status
323 break;
324 case 0x060000: // DMA Count
325 ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
326 state.dma_count = (data & 0x3FFF);
327 state.idmarw = ((data & 0x4000) == 0x4000);
328 state.dmaen = ((data & 0x8000) == 0x8000);
329 // This handles the "dummy DMA transfer" mentioned in the docs
330 // disabled because it causes the floppy test to fail
331 #if 0
332 if (!state.idmarw){
333 if (access_check_dma(true)){
334 uint32_t newAddr = mapAddr(state.dma_address, true);
335 // RAM access
336 if (newAddr <= 0x1fffff)
337 WR16(state.base_ram, newAddr, state.base_ram_size - 1, 0xFF);
338 else if (address <= 0x3FFFFF)
339 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, 0xFF);
340 }
341 }
342 #endif
343 state.dma_count++;
344 handled = true;
345 break;
346 case 0x070000: // Line Printer Status Register
347 break;
348 case 0x080000: // Real Time Clock
349 LOGS("REAL TIME CLOCK WRITE");
350 break;
351 case 0x090000: // Phone registers
352 switch (address & 0x0FF000) {
353 case 0x090000: // Handset relay
354 case 0x098000:
355 break;
356 case 0x091000: // Line select 2
357 case 0x099000:
358 break;
359 case 0x092000: // Hook relay 1
360 case 0x09A000:
361 break;
362 case 0x093000: // Hook relay 2
363 case 0x09B000:
364 break;
365 case 0x094000: // Line 1 hold
366 case 0x09C000:
367 break;
368 case 0x095000: // Line 2 hold
369 case 0x09D000:
370 break;
371 case 0x096000: // Line 1 A-lead
372 case 0x09E000:
373 break;
374 case 0x097000: // Line 2 A-lead
375 case 0x09F000:
376 break;
377 }
378 break;
379 case 0x0A0000: // Miscellaneous Control Register
380 ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
381 // TODO: handle the ctrl bits properly
382 if (data & 0x8000){
383 state.timer_enabled = 1;
384 }else{
385 state.timer_enabled = 0;
386 state.timer_asserted = 0;
387 }
388 state.dma_reading = (data & 0x4000);
389 if (state.leds != ((~data & 0xF00) >> 8)) {
390 state.leds = (~data & 0xF00) >> 8;
391 #ifdef SHOW_LEDS
392 printf("LEDs: %s %s %s %s\n",
393 (state.leds & 8) ? "R" : "-",
394 (state.leds & 4) ? "G" : "-",
395 (state.leds & 2) ? "Y" : "-",
396 (state.leds & 1) ? "R" : "-");
397 #endif
398 }
399 handled = true;
400 break;
401 case 0x0B0000: // TM/DIALWR
402 break;
403 case 0x0C0000: // Clear Status Register
404 state.genstat = 0xFFFF;
405 state.bsr0 = 0xFFFF;
406 state.bsr1 = 0xFFFF;
407 handled = true;
408 break;
409 case 0x0D0000: // DMA Address Register
410 if (address & 0x004000) {
411 // A14 high -- set most significant bits
412 state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
413 } else {
414 // A14 low -- set least significant bits
415 state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
416 }
417 handled = true;
418 break;
419 case 0x0E0000: // Disk Control Register
420 {
421 bool fd_selected;
422 bool hd_selected;
423 ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
424 // B7 = FDD controller reset
425 if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
426 // B6 = drive 0 select
427 fd_selected = (data & 0x40) != 0;
428 // B5 = motor enable -- TODO
429 // B4 = HDD controller reset
430 if ((data & 0x10) == 0) wd2010_reset(&state.hdc_ctx);
431 // B3 = HDD0 select
432 hd_selected = (data & 0x08) != 0;
433 // B2,1,0 = HDD0 head select -- TODO?
434 if (hd_selected && !state.hd_selected){
435 state.fd_selected = false;
436 state.hd_selected = true;
437 }else if (fd_selected && !state.fd_selected){
438 state.hd_selected = false;
439 state.fd_selected = true;
440 }
441 handled = true;
442 break;
443 }
444 case 0x0F0000: // Line Printer Data Register
445 break;
446 }
447 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
448 // I/O register space, zone B
449 switch (address & 0xF00000) {
450 case 0xC00000: // Expansion slots
451 case 0xD00000:
452 switch (address & 0xFC0000) {
453 case 0xC00000: // Expansion slot 0
454 case 0xC40000: // Expansion slot 1
455 case 0xC80000: // Expansion slot 2
456 case 0xCC0000: // Expansion slot 3
457 case 0xD00000: // Expansion slot 4
458 case 0xD40000: // Expansion slot 5
459 case 0xD80000: // Expansion slot 6
460 case 0xDC0000: // Expansion slot 7
461 fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
462 handled = true;
463 break;
464 }
465 break;
466 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
467 case 0xF00000:
468 switch (address & 0x070000) {
469 case 0x000000: // [ef][08]xxxx ==> WD2010 hard disc controller
470 wd2010_write_reg(&state.hdc_ctx, (address >> 1) & 7, data);
471 handled = true;
472 break;
473 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
474 /*ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");*/
475 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
476 handled = true;
477 break;
478 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
479 // MCR2 - UNIX PC Rev. P5.1 HDD head select b3 and potential HDD#2 select
480 wd2010_write_reg(&state.hdc_ctx, UNIXPC_REG_MCR2, data);
481 handled = true;
482 break;
483 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
484 LOGS("REAL TIME CLOCK DATA WRITE");
485 break;
486 case 0x040000: // [ef][4c]xxxx ==> General Control Register
487 switch (address & 0x077000) {
488 case 0x040000: // [ef][4c][08]xxx ==> EE
489 // Error Enable. If =0, Level7 intrs and bus errors are masked.
490 ENFORCE_SIZE_W(bits, address, 16, "EE");
491 state.ee = ((data & 0x8000) == 0x8000);
492 handled = true;
493 break;
494 case 0x041000: // [ef][4c][19]xxx ==> PIE
495 ENFORCE_SIZE_W(bits, address, 16, "PIE");
496 state.pie = ((data & 0x8000) == 0x8000);
497 handled = true;
498 break;
499 case 0x042000: // [ef][4c][2A]xxx ==> BP
500 break;
501 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
502 ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
503 state.romlmap = ((data & 0x8000) == 0x8000);
504 handled = true;
505 break;
506 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
507 ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
508 break;
509 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
510 ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
511 break;
512 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
513 ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
514 break;
515 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
516 ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
517 break;
518 }
519 case 0x050000: // [ef][5d]xxxx ==> 8274
520 break;
521 case 0x060000: // [ef][6e]xxxx ==> Control regs
522 switch (address & 0x07F000) {
523 default:
524 break;
525 }
526 break;
527 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
528 // TODO: figure out which sizes are valid (probably just 8 and 16)
529 // ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER");
530 if (bits == 8) {
531 #ifdef LOG_KEYBOARD_WRITES
532 LOG("KBD WR %02X => %02X\n", (address >> 1) & 3, data);
533 #endif
534 keyboard_write(&state.kbd, (address >> 1) & 3, data);
535 handled = true;
536 } else if (bits == 16) {
537 #ifdef LOG_KEYBOARD_WRITES
538 LOG("KBD WR %02X => %04X\n", (address >> 1) & 3, data);
539 #endif
540 keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8);
541 handled = true;
542 }
543 break;
544 }
545 }
546 }
548 LOG_NOT_HANDLED_W(bits);
549 }/*}}}*/
551 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
552 {
553 bool handled = false;
554 uint32_t data = EMPTY & 0xFFFFFFFF;
556 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
557 // I/O register space, zone A
558 switch (address & 0x0F0000) {
559 case 0x010000: // General Status Register
560 /* ENFORCE_SIZE_R(bits, address, 16, "GENSTAT"); */
561 if (bits == 32) {
562 return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
563 } else if (bits == 16) {
564 return (uint16_t)state.genstat;
565 } else {
566 return (uint8_t)(state.genstat & 0xff);
567 }
568 break;
569 case 0x030000: // Bus Status Register 0
570 ENFORCE_SIZE_R(bits, address, 16, "BSR0");
571 return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
572 break;
573 case 0x040000: // Bus Status Register 1
574 ENFORCE_SIZE_R(bits, address, 16, "BSR1");
575 return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
576 break;
577 case 0x050000: // Phone status
578 ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
579 break;
580 case 0x060000: // DMA Count
581 // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
582 // Bit 14 is always unused, so leave it set
583 ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
584 return (state.dma_count & 0x3fff) | 0xC000;
585 break;
586 case 0x070000: // Line Printer Status Register
587 data = 0x00120012; // no parity error, no line printer error, no irqs from FDD or HDD
588 data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0;
589 data |= wd2010_get_irq(&state.hdc_ctx) ? 0x00040004 : 0;
590 return data;
591 break;
592 case 0x080000: // Real Time Clock
593 LOGS("REAL TIME CLOCK READ");
594 break;
595 case 0x090000: // Phone registers
596 switch (address & 0x0FF000) {
597 case 0x090000: // Handset relay
598 case 0x098000:
599 break;
600 case 0x091000: // Line select 2
601 case 0x099000:
602 break;
603 case 0x092000: // Hook relay 1
604 case 0x09A000:
605 break;
606 case 0x093000: // Hook relay 2
607 case 0x09B000:
608 break;
609 case 0x094000: // Line 1 hold
610 case 0x09C000:
611 break;
612 case 0x095000: // Line 2 hold
613 case 0x09D000:
614 break;
615 case 0x096000: // Line 1 A-lead
616 case 0x09E000:
617 break;
618 case 0x097000: // Line 2 A-lead
619 case 0x09F000:
620 break;
621 }
622 break;
623 case 0x0A0000: // Miscellaneous Control Register -- write only!
624 handled = true;
625 break;
626 case 0x0B0000: // TM/DIALWR
627 break;
628 case 0x0C0000: // Clear Status Register -- write only!
629 handled = true;
630 break;
631 case 0x0D0000: // DMA Address Register
632 break;
633 case 0x0E0000: // Disk Control Register
634 break;
635 case 0x0F0000: // Line Printer Data Register
636 break;
637 }
638 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
639 // I/O register space, zone B
640 switch (address & 0xF00000) {
641 case 0xC00000: // Expansion slots
642 case 0xD00000:
643 switch (address & 0xFC0000) {
644 case 0xC00000: // Expansion slot 0
645 case 0xC40000: // Expansion slot 1
646 case 0xC80000: // Expansion slot 2
647 case 0xCC0000: // Expansion slot 3
648 case 0xD00000: // Expansion slot 4
649 case 0xD40000: // Expansion slot 5
650 case 0xD80000: // Expansion slot 6
651 case 0xDC0000: // Expansion slot 7
652 fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
653 handled = true;
654 break;
655 }
656 break;
657 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
658 case 0xF00000:
659 switch (address & 0x070000) {
660 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
661 return (wd2010_read_reg(&state.hdc_ctx, (address >> 1) & 7));
663 break;
664 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
665 /*ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");*/
666 return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
667 break;
668 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
669 break;
670 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
671 LOGS("REAL TIME CLOCK DATA READ");
672 break;
673 case 0x040000: // [ef][4c]xxxx ==> General Control Register
674 switch (address & 0x077000) {
675 case 0x040000: // [ef][4c][08]xxx ==> EE
676 case 0x041000: // [ef][4c][19]xxx ==> PIE
677 case 0x042000: // [ef][4c][2A]xxx ==> BP
678 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
679 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
680 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
681 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
682 // All write-only registers... TODO: bus error?
683 handled = true;
684 break;
685 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
686 break;
687 }
688 break;
689 case 0x050000: // [ef][5d]xxxx ==> 8274
690 break;
691 case 0x060000: // [ef][6e]xxxx ==> Control regs
692 switch (address & 0x07F000) {
693 default:
694 break;
695 }
696 break;
697 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
698 // TODO: figure out which sizes are valid (probably just 8 and 16)
699 //ENFORCE_SIZE_R(bits, address, 16, "KEYBOARD CONTROLLER");
700 {
701 if (bits == 8) {
702 return keyboard_read(&state.kbd, (address >> 1) & 3);
703 } else {
704 return keyboard_read(&state.kbd, (address >> 1) & 3) << 8;
705 }
706 return data;
707 }
708 break;
709 }
710 }
711 }
713 LOG_NOT_HANDLED_R(bits);
715 return data;
716 }/*}}}*/
719 /********************************************************
720 * m68k memory read/write support functions for Musashi
721 ********************************************************/
723 /**
724 * @brief Read M68K memory, 32-bit
725 */
726 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
727 {
728 uint32_t data = EMPTY & 0xFFFFFFFF;
730 // If ROMLMAP is set, force system to access ROM
731 if (!state.romlmap)
732 address |= 0x800000;
734 // Check access permissions
735 ACCESS_CHECK_RD(address, 32);
737 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
738 // ROM access
739 return RD32(state.rom, address, ROM_SIZE - 1);
740 } else if (address <= 0x3fffff) {
741 // RAM access
742 uint32_t newAddr = MAP_ADDR(address);
744 if (newAddr <= 0x1fffff) {
745 if (newAddr >= state.base_ram_size)
746 return EMPTY & 0xffffffff;
747 else
748 return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
749 } else {
750 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
751 return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
752 else
753 return EMPTY & 0xffffffff;
754 }
755 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
756 // I/O register space, zone A
757 switch (address & 0x0F0000) {
758 case 0x000000: // Map RAM access
759 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
760 return RD32(state.map, address, 0x7FF);
761 break;
762 case 0x020000: // Video RAM
763 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
764 return RD32(state.vram, address, 0x7FFF);
765 break;
766 default:
767 return IoRead(address, 32);
768 }
769 } else {
770 return IoRead(address, 32);
771 }
773 return data;
774 }/*}}}*/
776 /**
777 * @brief Read M68K memory, 16-bit
778 */
779 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
780 {
781 uint16_t data = EMPTY & 0xFFFF;
783 // If ROMLMAP is set, force system to access ROM
784 if (!state.romlmap)
785 address |= 0x800000;
787 // Check access permissions
788 ACCESS_CHECK_RD(address, 16);
790 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
791 // ROM access
792 data = RD16(state.rom, address, ROM_SIZE - 1);
793 } else if (address <= 0x3fffff) {
794 // RAM access
795 uint32_t newAddr = MAP_ADDR(address);
797 if (newAddr <= 0x1fffff) {
798 if (newAddr >= state.base_ram_size)
799 return EMPTY & 0xffff;
800 else
801 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
802 } else {
803 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
804 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
805 else
806 return EMPTY & 0xffff;
807 }
808 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
809 // I/O register space, zone A
810 switch (address & 0x0F0000) {
811 case 0x000000: // Map RAM access
812 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
813 data = RD16(state.map, address, 0x7FF);
814 break;
815 case 0x020000: // Video RAM
816 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
817 data = RD16(state.vram, address, 0x7FFF);
818 break;
819 default:
820 data = IoRead(address, 16);
821 }
822 } else {
823 data = IoRead(address, 16);
824 }
826 return data;
827 }/*}}}*/
829 /**
830 * @brief Read M68K memory, 8-bit
831 */
832 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
833 {
834 uint8_t data = EMPTY & 0xFF;
836 // If ROMLMAP is set, force system to access ROM
837 if (!state.romlmap)
838 address |= 0x800000;
840 // Check access permissions
841 ACCESS_CHECK_RD(address, 8);
843 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
844 // ROM access
845 data = RD8(state.rom, address, ROM_SIZE - 1);
846 } else if (address <= 0x3fffff) {
847 // RAM access
848 uint32_t newAddr = MAP_ADDR(address);
850 if (newAddr <= 0x1fffff) {
851 if (newAddr >= state.base_ram_size)
852 return EMPTY & 0xff;
853 else
854 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
855 } else {
856 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
857 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
858 else
859 return EMPTY & 0xff;
860 }
861 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
862 // I/O register space, zone A
863 switch (address & 0x0F0000) {
864 case 0x000000: // Map RAM access
865 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
866 data = RD8(state.map, address, 0x7FF);
867 break;
868 case 0x020000: // Video RAM
869 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
870 data = RD8(state.vram, address, 0x7FFF);
871 break;
872 default:
873 data = IoRead(address, 8);
874 }
875 } else {
876 data = IoRead(address, 8);
877 }
879 return data;
880 }/*}}}*/
882 /**
883 * @brief Write M68K memory, 32-bit
884 */
885 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
886 {
887 // If ROMLMAP is set, force system to access ROM
888 if (!state.romlmap)
889 address |= 0x800000;
891 // Check access permissions
892 ACCESS_CHECK_WR(address, 32);
894 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
895 // ROM access
896 } else if (address <= 0x3FFFFF) {
897 // RAM access
898 uint32_t newAddr = MAP_ADDR(address);
900 if (newAddr <= 0x1fffff) {
901 if (newAddr < state.base_ram_size) {
902 WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
903 }
904 } else {
905 if ((newAddr - 0x200000) < state.exp_ram_size) {
906 WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
907 }
908 }
909 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
910 // I/O register space, zone A
911 switch (address & 0x0F0000) {
912 case 0x000000: // Map RAM access
913 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X\n", address);
914 WR32(state.map, address, 0x7FF, value);
915 break;
916 case 0x020000: // Video RAM
917 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X\n", address);
918 WR32(state.vram, address, 0x7FFF, value);
919 break;
920 default:
921 IoWrite(address, value, 32);
922 }
923 } else {
924 IoWrite(address, value, 32);
925 }
926 }/*}}}*/
928 /**
929 * @brief Write M68K memory, 16-bit
930 */
931 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
932 {
933 // If ROMLMAP is set, force system to access ROM
934 if (!state.romlmap)
935 address |= 0x800000;
937 // Check access permissions
938 ACCESS_CHECK_WR(address, 16);
940 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
941 // ROM access
942 } else if (address <= 0x3FFFFF) {
943 // RAM access
944 uint32_t newAddr = MAP_ADDR(address);
946 if (newAddr <= 0x1fffff) {
947 if (newAddr < state.base_ram_size) {
948 WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
949 }
950 } else {
951 if ((newAddr - 0x200000) < state.exp_ram_size) {
952 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
953 }
954 }
955 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
956 // I/O register space, zone A
957 switch (address & 0x0F0000) {
958 case 0x000000: // Map RAM access
959 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
960 WR16(state.map, address, 0x7FF, value);
961 break;
962 case 0x020000: // Video RAM
963 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
964 WR16(state.vram, address, 0x7FFF, value);
965 break;
966 default:
967 IoWrite(address, value, 16);
968 }
969 } else {
970 IoWrite(address, value, 16);
971 }
972 }/*}}}*/
974 /**
975 * @brief Write M68K memory, 8-bit
976 */
977 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
978 {
979 // If ROMLMAP is set, force system to access ROM
980 if (!state.romlmap)
981 address |= 0x800000;
983 // Check access permissions
984 ACCESS_CHECK_WR(address, 8);
986 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
987 // ROM access (read only!)
988 } else if (address <= 0x3FFFFF) {
989 // RAM access
990 uint32_t newAddr = MAP_ADDR(address);
992 if (newAddr <= 0x1fffff) {
993 if (newAddr < state.base_ram_size) {
994 WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
995 }
996 } else {
997 if ((newAddr - 0x200000) < state.exp_ram_size) {
998 WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
999 }
1000 }
1001 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
1002 // I/O register space, zone A
1003 switch (address & 0x0F0000) {
1004 case 0x000000: // Map RAM access
1005 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
1006 WR8(state.map, address, 0x7FF, value);
1007 break;
1008 case 0x020000: // Video RAM
1009 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
1010 WR8(state.vram, address, 0x7FFF, value);
1011 break;
1012 default:
1013 IoWrite(address, value, 8);
1014 }
1015 } else {
1016 IoWrite(address, value, 8);
1017 }
1018 }/*}}}*/
1021 // for the disassembler
1022 uint32_t m68k_read_disassembler_32(uint32_t addr)
1023 {
1024 if (addr < 0x400000) {
1025 // XXX FIXME BUGBUG update this to use the new mapper macros!
1026 uint16_t page = (addr >> 12) & 0x3FF;
1027 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
1028 uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
1029 if (newAddr <= 0x1fffff) {
1030 if (newAddr >= state.base_ram_size)
1031 return EMPTY;
1032 else
1033 return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
1034 } else {
1035 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
1036 return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
1037 else
1038 return EMPTY;
1039 }
1040 } else {
1041 LOG("WARNING: Disassembler RD32 out of range 0x%08X\n", addr);
1042 return EMPTY;
1043 }
1044 }
1046 uint32_t m68k_read_disassembler_16(uint32_t addr)
1047 {
1048 if (addr < 0x400000) {
1049 uint16_t page = (addr >> 12) & 0x3FF;
1050 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
1051 uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
1052 if (newAddr <= 0x1fffff) {
1053 if (newAddr >= state.base_ram_size)
1054 return EMPTY & 0xffff;
1055 else
1056 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
1057 } else {
1058 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
1059 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
1060 else
1061 return EMPTY & 0xffff;
1062 }
1063 } else {
1064 LOG("WARNING: Disassembler RD16 out of range 0x%08X\n", addr);
1065 return EMPTY & 0xffff;
1066 }
1067 }
1069 uint32_t m68k_read_disassembler_8 (uint32_t addr)
1070 {
1071 if (addr < 0x400000) {
1072 uint16_t page = (addr >> 12) & 0x3FF;
1073 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
1074 uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
1075 if (newAddr <= 0x1fffff) {
1076 if (newAddr >= state.base_ram_size)
1077 return EMPTY & 0xff;
1078 else
1079 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
1080 } else {
1081 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
1082 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
1083 else
1084 return EMPTY & 0xff;
1085 }
1086 } else {
1087 LOG("WARNING: Disassembler RD8 out of range 0x%08X\n", addr);
1088 return EMPTY & 0xff;
1089 }
1090 }