src/memory.c

Fri, 03 Dec 2010 00:04:01 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Fri, 03 Dec 2010 00:04:01 +0000
changeset 43
4d59e4ceef52
parent 40
239bc48590ba
child 44
f928be115194
permissions
-rw-r--r--

add basic handling for Clear Status Register and fix mem access checks to provide PIE status

     1 #include <stdio.h>
     2 #include <stdlib.h>
     3 #include <stdint.h>
     4 #include <stdbool.h>
     5 #include "musashi/m68k.h"
     6 #include "state.h"
     7 #include "memory.h"
     9 /******************
    10  * Memory mapping
    11  ******************/
    13 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
    15 uint32_t mapAddr(uint32_t addr, bool writing)
    16 {
    17 	if (addr < 0x400000) {
    18 		// RAM access. Check against the Map RAM
    19 		// Start by getting the original page address
    20 		uint16_t page = (addr >> 12) & 0x3FF;
    22 		// Look it up in the map RAM and get the physical page address
    23 		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
    25 		// Update the Page Status bits
    26 		uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
    27 		if (pagebits != 0) {
    28 			if (writing)
    29 				state.map[page*2] |= 0x60;		// Page written to (dirty)
    30 			else
    31 				state.map[page*2] |= 0x40;		// Page accessed but not written
    32 		}
    34 		// Return the address with the new physical page spliced in
    35 		return (new_page_addr << 12) + (addr & 0xFFF);
    36 	} else {
    37 		// I/O, VRAM or MapRAM space; no mapping is performed or required
    38 		// TODO: assert here?
    39 		return addr;
    40 	}
    41 }
    43 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)
    44 {
    45 	// Are we in Supervisor mode?
    46 	if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
    47 		// Yes. We can do anything we like.
    48 		return MEM_ALLOWED;
    50 	// If we're here, then we must be in User mode.
    51 	// Check that the user didn't access memory outside of the RAM area
    52 	if (addr >= 0x400000)
    53 		return MEM_UIE;
    55 	// This leaves us with Page Fault checking. Get the page bits for this page.
    56 	uint16_t page = (addr >> 12) & 0x3FF;
    57 	uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
    59 	// Check page is present
    60 	if ((pagebits & 0x03) == 0)
    61 		return MEM_PAGEFAULT;
    63 	// User attempt to access the kernel
    64 	// A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
    65 	if (((addr >> 19) & 0x0F) == 0)
    66 		return MEM_KERNEL;
    68 	// Check page is write enabled
    69 	if ((pagebits & 0x04) == 0)
    70 		return MEM_PAGE_NO_WE;
    72 	// Page access allowed.
    73 	return MEM_ALLOWED;
    74 }
    76 #undef MAPRAM
    79 /********************************************************
    80  * m68k memory read/write support functions for Musashi
    81  ********************************************************/
    83 /**
    84  * @brief	Check memory access permissions for a write operation.
    85  * @note	This used to be a single macro (merged with ACCESS_CHECK_RD), but
    86  * 			gcc throws warnings when you have a return-with-value in a void
    87  * 			function, even if the return-with-value is completely unreachable.
    88  * 			Similarly it doesn't like it if you have a return without a value
    89  * 			in a non-void function, even if it's impossible to ever reach the
    90  * 			return-with-no-value. UGH!
    91  */
    92 #define ACCESS_CHECK_WR(address, bits) do {							\
    93 		bool fault = false;											\
    94 		/* MEM_STATUS st; */										\
    95 		switch (checkMemoryAccess(address, true)) {					\
    96 			case MEM_ALLOWED:										\
    97 				/* Access allowed */								\
    98 				break;												\
    99 			case MEM_PAGEFAULT:										\
   100 				/* Page fault */									\
   101 				state.genstat = 0x8BFF | (status.pie ? 0x0400 : 0);	\
   102 				fault = true;										\
   103 				break;												\
   104 			case MEM_UIE:											\
   105 				/* User access to memory above 4MB */				\
   106 				state.genstat = 0x9AFF | (status.pie ? 0x0400 : 0);	\
   107 				fault = true;										\
   108 				break;												\
   109 			case MEM_KERNEL:										\
   110 			case MEM_PAGE_NO_WE:									\
   111 				/* kernel access or page not write enabled */		\
   112 				/* TODO: which regs need setting? */				\
   113 				fault = true;										\
   114 				break;												\
   115 		}															\
   116 																	\
   117 		if (fault) {												\
   118 			if (bits >= 16)											\
   119 				state.bsr0 = 0x7F00;								\
   120 			else													\
   121 				state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00;		\
   122 			state.bsr0 |= (address >> 16);							\
   123 			state.bsr1 = address & 0xffff;							\
   124 			printf("ERR: BusError WR\n");							\
   125 			m68k_pulse_bus_error();									\
   126 			return;													\
   127 		}															\
   128 	} while (false)
   130 /**
   131  * @brief Check memory access permissions for a read operation.
   132  * @note	This used to be a single macro (merged with ACCESS_CHECK_WR), but
   133  * 			gcc throws warnings when you have a return-with-value in a void
   134  * 			function, even if the return-with-value is completely unreachable.
   135  * 			Similarly it doesn't like it if you have a return without a value
   136  * 			in a non-void function, even if it's impossible to ever reach the
   137  * 			return-with-no-value. UGH!
   138  */
   139 #define ACCESS_CHECK_RD(address, bits) do {							\
   140 		bool fault = false;											\
   141 		/* MEM_STATUS st; */										\
   142 		switch (checkMemoryAccess(address, false)) {				\
   143 			case MEM_ALLOWED:										\
   144 				/* Access allowed */								\
   145 				break;												\
   146 			case MEM_PAGEFAULT:										\
   147 				/* Page fault */									\
   148 				state.genstat = 0xCBFF | (status.pie ? 0x0400 : 0);	\
   149 				fault = true;										\
   150 				break;												\
   151 			case MEM_UIE:											\
   152 				/* User access to memory above 4MB */				\
   153 				state.genstat = 0xDAFF | (status.pie ? 0x0400 : 0);	\
   154 				fault = true;										\
   155 				break;												\
   156 			case MEM_KERNEL:										\
   157 			case MEM_PAGE_NO_WE:									\
   158 				/* kernel access or page not write enabled */		\
   159 				/* TODO: which regs need setting? */				\
   160 				fault = true;										\
   161 				break;												\
   162 		}															\
   163 																	\
   164 		if (fault) {												\
   165 			if (bits >= 16)											\
   166 				state.bsr0 = 0x7F00;								\
   167 			else													\
   168 				state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00;		\
   169 			state.bsr0 |= (address >> 16);							\
   170 			state.bsr1 = address & 0xffff;							\
   171 			printf("ERR: BusError RD\n");							\
   172 			m68k_pulse_bus_error();									\
   173 			return 0xFFFFFFFF;										\
   174 		}															\
   175 	} while (false)
   177 // Logging macros
   178 #define LOG_NOT_HANDLED_R(bits)																	\
   179 	do {																						\
   180 		if (!handled)																			\
   181 			printf("unhandled read%02d, addr=0x%08X\n", bits, address);							\
   182 	} while (0);
   184 #define LOG_NOT_HANDLED_W(bits)																	\
   185 	do {																						\
   186 		if (!handled)																			\
   187 			printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, value);	\
   188 	} while (0);
   190 /**
   191  * @brief Read M68K memory, 32-bit
   192  */
   193 uint32_t m68k_read_memory_32(uint32_t address)
   194 {
   195 	uint32_t data = 0xFFFFFFFF;
   196 	bool handled = false;
   198 	// If ROMLMAP is set, force system to access ROM
   199 	if (!state.romlmap)
   200 		address |= 0x800000;
   202 	// Check access permissions
   203 	ACCESS_CHECK_RD(address, 32);
   205 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   206 		// ROM access
   207 		data = RD32(state.rom, address, ROM_SIZE - 1);
   208 		handled = true;
   209 	} else if (address <= (state.ram_size - 1)) {
   210 		// RAM access
   211 		data = RD32(state.ram, mapAddr(address, false), state.ram_size - 1);
   212 		handled = true;
   213 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   214 		// I/O register space, zone A
   215 		switch (address & 0x0F0000) {
   216 			case 0x000000:				// Map RAM access
   217 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
   218 				data = RD32(state.map, address, 0x7FF);
   219 				handled = true;
   220 				break;
   221 			case 0x010000:				// General Status Register
   222 				data = ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
   223 				handled = true;
   224 				break;
   225 			case 0x020000:				// Video RAM
   226 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
   227 				data = RD32(state.vram, address, 0x7FFF);
   228 				handled = true;
   229 				break;
   230 			case 0x030000:				// Bus Status Register 0
   231 				data = ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
   232 				handled = true;
   233 				break;
   234 			case 0x040000:				// Bus Status Register 1
   235 				data = ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
   236 				handled = true;
   237 				break;
   238 			case 0x050000:				// Phone status
   239 				break;
   240 			case 0x060000:				// DMA Count
   241 				break;
   242 			case 0x070000:				// Line Printer Status Register
   243 				break;
   244 			case 0x080000:				// Real Time Clock
   245 				break;
   246 			case 0x090000:				// Phone registers
   247 				switch (address & 0x0FF000) {
   248 					case 0x090000:		// Handset relay
   249 					case 0x098000:
   250 						break;
   251 					case 0x091000:		// Line select 2
   252 					case 0x099000:
   253 						break;
   254 					case 0x092000:		// Hook relay 1
   255 					case 0x09A000:
   256 						break;
   257 					case 0x093000:		// Hook relay 2
   258 					case 0x09B000:
   259 						break;
   260 					case 0x094000:		// Line 1 hold
   261 					case 0x09C000:
   262 						break;
   263 					case 0x095000:		// Line 2 hold
   264 					case 0x09D000:
   265 						break;
   266 					case 0x096000:		// Line 1 A-lead
   267 					case 0x09E000:
   268 						break;
   269 					case 0x097000:		// Line 2 A-lead
   270 					case 0x09F000:
   271 						break;
   272 				}
   273 				break;
   274 			case 0x0A0000:				// Miscellaneous Control Register
   275 				break;
   276 			case 0x0B0000:				// TM/DIALWR
   277 				break;
   278 			case 0x0C0000:				// Clear Status Register
   279 				handled = true;
   280 				break;
   281 			case 0x0D0000:				// DMA Address Register
   282 				break;
   283 			case 0x0E0000:				// Disk Control Register
   284 				break;
   285 			case 0x0F0000:				// Line Printer Data Register
   286 				break;
   287 		}
   288 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   289 		// I/O register space, zone B
   290 		switch (address & 0xF00000) {
   291 			case 0xC00000:				// Expansion slots
   292 			case 0xD00000:
   293 				switch (address & 0xFC0000) {
   294 					case 0xC00000:		// Expansion slot 0
   295 					case 0xC40000:		// Expansion slot 1
   296 					case 0xC80000:		// Expansion slot 2
   297 					case 0xCC0000:		// Expansion slot 3
   298 					case 0xD00000:		// Expansion slot 4
   299 					case 0xD40000:		// Expansion slot 5
   300 					case 0xD80000:		// Expansion slot 6
   301 					case 0xDC0000:		// Expansion slot 7
   302 						fprintf(stderr, "NOTE: RD32 from expansion card space, addr=0x%08X\n", address);
   303 						break;
   304 				}
   305 				break;
   306 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   307 			case 0xF00000:
   308 				switch (address & 0x070000) {
   309 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   310 						break;
   311 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   312 						break;
   313 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   314 						break;
   315 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   316 						break;
   317 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   318 						switch (address & 0x077000) {
   319 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   320 								break;
   321 							case 0x041000:		// [ef][4c][19]xxx ==> P1E
   322 								break;
   323 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   324 								break;
   325 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   326 								break;
   327 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   328 								break;
   329 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   330 								break;
   331 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   332 								break;
   333 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   334 								break;
   335 						}
   336 						break;
   337 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   338 						break;
   339 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   340 						switch (address & 0x07F000) {
   341 							default:
   342 								break;
   343 						}
   344 						break;
   345 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   346 						break;
   347 				}
   348 		}
   349 	}
   351 	LOG_NOT_HANDLED_R(32);
   352 	return data;
   353 }
   355 /**
   356  * @brief Read M68K memory, 16-bit
   357  */
   358 uint32_t m68k_read_memory_16(uint32_t address)
   359 {
   360 	uint16_t data = 0xFFFF;
   361 	bool handled = false;
   363 	// If ROMLMAP is set, force system to access ROM
   364 	if (!state.romlmap)
   365 		address |= 0x800000;
   367 	// Check access permissions
   368 	ACCESS_CHECK_RD(address, 16);
   370 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   371 		// ROM access
   372 		data = RD16(state.rom, address, ROM_SIZE - 1);
   373 		handled = true;
   374 	} else if (address <= (state.ram_size - 1)) {
   375 		// RAM access
   376 		data = RD16(state.ram, mapAddr(address, false), state.ram_size - 1);
   377 		handled = true;
   378 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   379 		// I/O register space, zone A
   380 		switch (address & 0x0F0000) {
   381 			case 0x000000:				// Map RAM access
   382 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
   383 				data = RD16(state.map, address, 0x7FF);
   384 				handled = true;
   385 				break;
   386 			case 0x010000:				// General Status Register
   387 				data = state.genstat;
   388 				handled = true;
   389 				break;
   390 			case 0x020000:				// Video RAM
   391 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
   392 				data = RD16(state.vram, address, 0x7FFF);
   393 				handled = true;
   394 				break;
   395 			case 0x030000:				// Bus Status Register 0
   396 				data = state.bsr0;
   397 				handled = true;
   398 				break;
   399 			case 0x040000:				// Bus Status Register 1
   400 				data = state.bsr1;
   401 				handled = true;
   402 				break;
   403 			case 0x050000:				// Phone status
   404 				break;
   405 			case 0x060000:				// DMA Count
   406 				break;
   407 			case 0x070000:				// Line Printer Status Register
   408 				break;
   409 			case 0x080000:				// Real Time Clock
   410 				break;
   411 			case 0x090000:				// Phone registers
   412 				switch (address & 0x0FF000) {
   413 					case 0x090000:		// Handset relay
   414 					case 0x098000:
   415 						break;
   416 					case 0x091000:		// Line select 2
   417 					case 0x099000:
   418 						break;
   419 					case 0x092000:		// Hook relay 1
   420 					case 0x09A000:
   421 						break;
   422 					case 0x093000:		// Hook relay 2
   423 					case 0x09B000:
   424 						break;
   425 					case 0x094000:		// Line 1 hold
   426 					case 0x09C000:
   427 						break;
   428 					case 0x095000:		// Line 2 hold
   429 					case 0x09D000:
   430 						break;
   431 					case 0x096000:		// Line 1 A-lead
   432 					case 0x09E000:
   433 						break;
   434 					case 0x097000:		// Line 2 A-lead
   435 					case 0x09F000:
   436 						break;
   437 				}
   438 				break;
   439 			case 0x0A0000:				// Miscellaneous Control Register
   440 				break;
   441 			case 0x0B0000:				// TM/DIALWR
   442 				break;
   443 			case 0x0C0000:				// Clear Status Register
   444 				handled = true;
   445 				break;
   446 			case 0x0D0000:				// DMA Address Register
   447 				break;
   448 			case 0x0E0000:				// Disk Control Register
   449 				break;
   450 			case 0x0F0000:				// Line Printer Data Register
   451 				break;
   452 		}
   453 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   454 		// I/O register space, zone B
   455 		switch (address & 0xF00000) {
   456 			case 0xC00000:				// Expansion slots
   457 			case 0xD00000:
   458 				switch (address & 0xFC0000) {
   459 					case 0xC00000:		// Expansion slot 0
   460 					case 0xC40000:		// Expansion slot 1
   461 					case 0xC80000:		// Expansion slot 2
   462 					case 0xCC0000:		// Expansion slot 3
   463 					case 0xD00000:		// Expansion slot 4
   464 					case 0xD40000:		// Expansion slot 5
   465 					case 0xD80000:		// Expansion slot 6
   466 					case 0xDC0000:		// Expansion slot 7
   467 						fprintf(stderr, "NOTE: RD16 from expansion card space, addr=0x%08X\n", address);
   468 						break;
   469 				}
   470 				break;
   471 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   472 			case 0xF00000:
   473 				switch (address & 0x070000) {
   474 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   475 						break;
   476 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   477 						break;
   478 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   479 						break;
   480 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   481 						break;
   482 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   483 						switch (address & 0x077000) {
   484 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   485 								break;
   486 							case 0x041000:		// [ef][4c][19]xxx ==> P1E
   487 								break;
   488 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   489 								break;
   490 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   491 								break;
   492 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   493 								break;
   494 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   495 								break;
   496 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   497 								break;
   498 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   499 								break;
   500 						}
   501 						break;
   502 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   503 						break;
   504 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   505 						switch (address & 0x07F000) {
   506 							default:
   507 								break;
   508 						}
   509 						break;
   510 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   511 						break;
   512 				}
   513 		}
   514 	}
   516 	LOG_NOT_HANDLED_R(32);
   517 	return data;
   518 }
   520 /**
   521  * @brief Read M68K memory, 8-bit
   522  */
   523 uint32_t m68k_read_memory_8(uint32_t address)
   524 {
   525 	uint8_t data = 0xFF;
   526 	bool handled = false;
   528 	// If ROMLMAP is set, force system to access ROM
   529 	if (!state.romlmap)
   530 		address |= 0x800000;
   532 	// Check access permissions
   533 	ACCESS_CHECK_RD(address, 8);
   535 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   536 		// ROM access
   537 		data = RD8(state.rom, address, ROM_SIZE - 1);
   538 		handled = true;
   539 	} else if (address <= (state.ram_size - 1)) {
   540 		// RAM access
   541 		data = RD8(state.ram, mapAddr(address, false), state.ram_size - 1);
   542 		handled = true;
   543 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   544 		// I/O register space, zone A
   545 		switch (address & 0x0F0000) {
   546 			case 0x000000:				// Map RAM access
   547 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
   548 				data = RD8(state.map, address, 0x7FF);
   549 				handled = true;
   550 				break;
   551 			case 0x010000:				// General Status Register
   552 				if ((address & 1) == 0)
   553 					data = (state.genstat >> 8) & 0xff;
   554 				else
   555 					data = (state.genstat)      & 0xff;
   556 				handled = true;
   557 				break;
   558 			case 0x020000:				// Video RAM
   559 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
   560 				data = RD8(state.vram, address, 0x7FFF);
   561 				handled = true;
   562 				break;
   563 			case 0x030000:				// Bus Status Register 0
   564 				if ((address & 1) == 0)
   565 					data = (state.bsr0 >> 8) & 0xff;
   566 				else
   567 					data = (state.bsr0)      & 0xff;
   568 				handled = true;
   569 				break;
   570 			case 0x040000:				// Bus Status Register 1
   571 				if ((address & 1) == 0)
   572 					data = (state.bsr1 >> 8) & 0xff;
   573 				else
   574 					data = (state.bsr1)      & 0xff;
   575 				handled = true;
   576 				break;
   577 			case 0x050000:				// Phone status
   578 				break;
   579 			case 0x060000:				// DMA Count
   580 				break;
   581 			case 0x070000:				// Line Printer Status Register
   582 				break;
   583 			case 0x080000:				// Real Time Clock
   584 				break;
   585 			case 0x090000:				// Phone registers
   586 				switch (address & 0x0FF000) {
   587 					case 0x090000:		// Handset relay
   588 					case 0x098000:
   589 						break;
   590 					case 0x091000:		// Line select 2
   591 					case 0x099000:
   592 						break;
   593 					case 0x092000:		// Hook relay 1
   594 					case 0x09A000:
   595 						break;
   596 					case 0x093000:		// Hook relay 2
   597 					case 0x09B000:
   598 						break;
   599 					case 0x094000:		// Line 1 hold
   600 					case 0x09C000:
   601 						break;
   602 					case 0x095000:		// Line 2 hold
   603 					case 0x09D000:
   604 						break;
   605 					case 0x096000:		// Line 1 A-lead
   606 					case 0x09E000:
   607 						break;
   608 					case 0x097000:		// Line 2 A-lead
   609 					case 0x09F000:
   610 						break;
   611 				}
   612 				break;
   613 			case 0x0A0000:				// Miscellaneous Control Register
   614 				break;
   615 			case 0x0B0000:				// TM/DIALWR
   616 				break;
   617 			case 0x0C0000:				// Clear Status Register
   618 				handled = true;
   619 				break;
   620 			case 0x0D0000:				// DMA Address Register
   621 				break;
   622 			case 0x0E0000:				// Disk Control Register
   623 				break;
   624 			case 0x0F0000:				// Line Printer Data Register
   625 				break;
   626 		}
   627 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   628 		// I/O register space, zone B
   629 		switch (address & 0xF00000) {
   630 			case 0xC00000:				// Expansion slots
   631 			case 0xD00000:
   632 				switch (address & 0xFC0000) {
   633 					case 0xC00000:		// Expansion slot 0
   634 					case 0xC40000:		// Expansion slot 1
   635 					case 0xC80000:		// Expansion slot 2
   636 					case 0xCC0000:		// Expansion slot 3
   637 					case 0xD00000:		// Expansion slot 4
   638 					case 0xD40000:		// Expansion slot 5
   639 					case 0xD80000:		// Expansion slot 6
   640 					case 0xDC0000:		// Expansion slot 7
   641 						fprintf(stderr, "NOTE: RD8 from expansion card space, addr=0x%08X\n", address);
   642 						break;
   643 				}
   644 				break;
   645 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   646 			case 0xF00000:
   647 				switch (address & 0x070000) {
   648 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   649 						break;
   650 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   651 						break;
   652 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   653 						break;
   654 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   655 						break;
   656 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   657 						switch (address & 0x077000) {
   658 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   659 								break;
   660 							case 0x041000:		// [ef][4c][19]xxx ==> P1E
   661 								break;
   662 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   663 								break;
   664 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   665 								break;
   666 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   667 								break;
   668 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   669 								break;
   670 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   671 								break;
   672 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   673 								break;
   674 						}
   675 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   676 						break;
   677 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   678 						switch (address & 0x07F000) {
   679 							default:
   680 								break;
   681 						}
   682 						break;
   683 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   684 						break;
   685 				}
   686 		}
   687 	}
   689 	LOG_NOT_HANDLED_R(8);
   691 	return data;
   692 }
   694 /**
   695  * @brief Write M68K memory, 32-bit
   696  */
   697 void m68k_write_memory_32(uint32_t address, uint32_t value)
   698 {
   699 	bool handled = false;
   701 	// If ROMLMAP is set, force system to access ROM
   702 	if (!state.romlmap)
   703 		address |= 0x800000;
   705 	// Check access permissions
   706 	ACCESS_CHECK_WR(address, 32);
   708 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   709 		// ROM access
   710 		handled = true;
   711 	} else if (address <= (state.ram_size - 1)) {
   712 		// RAM access
   713 		WR32(state.ram, mapAddr(address, false), state.ram_size - 1, value);
   714 		handled = true;
   715 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   716 		// I/O register space, zone A
   717 		switch (address & 0x0F0000) {
   718 			case 0x000000:				// Map RAM access
   719 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
   720 				WR32(state.map, address, 0x7FF, value);
   721 				handled = true;
   722 				break;
   723 			case 0x010000:				// General Status Register
   724 				state.genstat = (value & 0xffff);
   725 				handled = true;
   726 				break;
   727 			case 0x020000:				// Video RAM
   728 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
   729 				WR32(state.vram, address, 0x7FFF, value);
   730 				handled = true;
   731 				break;
   732 			case 0x030000:				// Bus Status Register 0
   733 				break;
   734 			case 0x040000:				// Bus Status Register 1
   735 				break;
   736 			case 0x050000:				// Phone status
   737 				break;
   738 			case 0x060000:				// DMA Count
   739 				break;
   740 			case 0x070000:				// Line Printer Status Register
   741 				break;
   742 			case 0x080000:				// Real Time Clock
   743 				break;
   744 			case 0x090000:				// Phone registers
   745 				switch (address & 0x0FF000) {
   746 					case 0x090000:		// Handset relay
   747 					case 0x098000:
   748 						break;
   749 					case 0x091000:		// Line select 2
   750 					case 0x099000:
   751 						break;
   752 					case 0x092000:		// Hook relay 1
   753 					case 0x09A000:
   754 						break;
   755 					case 0x093000:		// Hook relay 2
   756 					case 0x09B000:
   757 						break;
   758 					case 0x094000:		// Line 1 hold
   759 					case 0x09C000:
   760 						break;
   761 					case 0x095000:		// Line 2 hold
   762 					case 0x09D000:
   763 						break;
   764 					case 0x096000:		// Line 1 A-lead
   765 					case 0x09E000:
   766 						break;
   767 					case 0x097000:		// Line 2 A-lead
   768 					case 0x09F000:
   769 						break;
   770 				}
   771 				break;
   772 			case 0x0A0000:				// Miscellaneous Control Register
   773 				break;
   774 			case 0x0B0000:				// TM/DIALWR
   775 				break;
   776 			case 0x0C0000:				// Clear Status Register
   777 				state.genstat = 0xFFFF;
   778 				state.bsr0 = 0xFFFF;
   779 				state.bsr1 = 0xFFFF;
   780 				handled = true;
   781 				break;
   782 			case 0x0D0000:				// DMA Address Register
   783 				break;
   784 			case 0x0E0000:				// Disk Control Register
   785 				break;
   786 			case 0x0F0000:				// Line Printer Data Register
   787 				break;
   788 		}
   789 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   790 		// I/O register space, zone B
   791 		switch (address & 0xF00000) {
   792 			case 0xC00000:				// Expansion slots
   793 			case 0xD00000:
   794 				switch (address & 0xFC0000) {
   795 					case 0xC00000:		// Expansion slot 0
   796 					case 0xC40000:		// Expansion slot 1
   797 					case 0xC80000:		// Expansion slot 2
   798 					case 0xCC0000:		// Expansion slot 3
   799 					case 0xD00000:		// Expansion slot 4
   800 					case 0xD40000:		// Expansion slot 5
   801 					case 0xD80000:		// Expansion slot 6
   802 					case 0xDC0000:		// Expansion slot 7
   803 						fprintf(stderr, "NOTE: WR32 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
   804 						handled = true;
   805 						break;
   806 				}
   807 				break;
   808 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   809 			case 0xF00000:
   810 				switch (address & 0x070000) {
   811 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   812 						break;
   813 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   814 						break;
   815 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   816 						break;
   817 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   818 						break;
   819 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   820 						switch (address & 0x077000) {
   821 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   822 								break;
   823 							case 0x041000:		// [ef][4c][19]xxx ==> P1E
   824 								break;
   825 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   826 								break;
   827 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   828 								state.romlmap = ((value & 0x8000) == 0x8000);
   829 								break;
   830 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   831 								break;
   832 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   833 								break;
   834 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   835 								break;
   836 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   837 								break;
   838 						}
   839 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   840 						break;
   841 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   842 						switch (address & 0x07F000) {
   843 							default:
   844 								break;
   845 						}
   846 						break;
   847 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   848 						break;
   849 				}
   850 		}
   851 	}
   853 	LOG_NOT_HANDLED_W(32);
   854 }
   856 /**
   857  * @brief Write M68K memory, 16-bit
   858  */
   859 void m68k_write_memory_16(uint32_t address, uint32_t value)
   860 {
   861 	bool handled = false;
   863 	// If ROMLMAP is set, force system to access ROM
   864 	if (!state.romlmap)
   865 		address |= 0x800000;
   867 	// Check access permissions
   868 	ACCESS_CHECK_WR(address, 16);
   870 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   871 		// ROM access
   872 		handled = true;
   873 	} else if (address <= (state.ram_size - 1)) {
   874 		// RAM access
   875 		WR16(state.ram, mapAddr(address, false), state.ram_size - 1, value);
   876 		handled = true;
   877 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   878 		// I/O register space, zone A
   879 		switch (address & 0x0F0000) {
   880 			case 0x000000:				// Map RAM access
   881 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   882 				WR16(state.map, address, 0x7FF, value);
   883 				handled = true;
   884 				break;
   885 			case 0x010000:				// General Status Register (read only)
   886 				handled = true;
   887 				break;
   888 			case 0x020000:				// Video RAM
   889 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   890 				WR16(state.vram, address, 0x7FFF, value);
   891 				handled = true;
   892 				break;
   893 			case 0x030000:				// Bus Status Register 0 (read only)
   894 				handled = true;
   895 				break;
   896 			case 0x040000:				// Bus Status Register 1 (read only)
   897 				handled = true;
   898 				break;
   899 			case 0x050000:				// Phone status
   900 				break;
   901 			case 0x060000:				// DMA Count
   902 				break;
   903 			case 0x070000:				// Line Printer Status Register
   904 				break;
   905 			case 0x080000:				// Real Time Clock
   906 				break;
   907 			case 0x090000:				// Phone registers
   908 				switch (address & 0x0FF000) {
   909 					case 0x090000:		// Handset relay
   910 					case 0x098000:
   911 						break;
   912 					case 0x091000:		// Line select 2
   913 					case 0x099000:
   914 						break;
   915 					case 0x092000:		// Hook relay 1
   916 					case 0x09A000:
   917 						break;
   918 					case 0x093000:		// Hook relay 2
   919 					case 0x09B000:
   920 						break;
   921 					case 0x094000:		// Line 1 hold
   922 					case 0x09C000:
   923 						break;
   924 					case 0x095000:		// Line 2 hold
   925 					case 0x09D000:
   926 						break;
   927 					case 0x096000:		// Line 1 A-lead
   928 					case 0x09E000:
   929 						break;
   930 					case 0x097000:		// Line 2 A-lead
   931 					case 0x09F000:
   932 						break;
   933 				}
   934 				break;
   935 			case 0x0A0000:				// Miscellaneous Control Register
   936 				break;
   937 			case 0x0B0000:				// TM/DIALWR
   938 				break;
   939 			case 0x0C0000:				// Clear Status Register
   940 				state.genstat = 0xFFFF;
   941 				state.bsr0 = 0xFFFF;
   942 				state.bsr1 = 0xFFFF;
   943 				handled = true;
   944 				break;
   945 			case 0x0D0000:				// DMA Address Register
   946 				break;
   947 			case 0x0E0000:				// Disk Control Register
   948 				break;
   949 			case 0x0F0000:				// Line Printer Data Register
   950 				break;
   951 		}
   952 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   953 		// I/O register space, zone B
   954 		switch (address & 0xF00000) {
   955 			case 0xC00000:				// Expansion slots
   956 			case 0xD00000:
   957 				switch (address & 0xFC0000) {
   958 					case 0xC00000:		// Expansion slot 0
   959 					case 0xC40000:		// Expansion slot 1
   960 					case 0xC80000:		// Expansion slot 2
   961 					case 0xCC0000:		// Expansion slot 3
   962 					case 0xD00000:		// Expansion slot 4
   963 					case 0xD40000:		// Expansion slot 5
   964 					case 0xD80000:		// Expansion slot 6
   965 					case 0xDC0000:		// Expansion slot 7
   966 						fprintf(stderr, "NOTE: WR16 to expansion card space, addr=0x%08X, data=0x%04X\n", address, value);
   967 						break;
   968 				}
   969 				break;
   970 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   971 			case 0xF00000:
   972 				switch (address & 0x070000) {
   973 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   974 						break;
   975 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   976 						break;
   977 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   978 						break;
   979 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   980 						break;
   981 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   982 						switch (address & 0x077000) {
   983 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   984 								break;
   985 							case 0x041000:		// [ef][4c][19]xxx ==> P1E
   986 								break;
   987 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   988 								break;
   989 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   990 								state.romlmap = ((value & 0x8000) == 0x8000);
   991 								handled = true;
   992 								break;
   993 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   994 								break;
   995 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   996 								break;
   997 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   998 								break;
   999 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
  1000 								break;
  1002 					case 0x050000:		// [ef][5d]xxxx ==> 8274
  1003 						break;
  1004 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
  1005 						switch (address & 0x07F000) {
  1006 							default:
  1007 								break;
  1009 						break;
  1010 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
  1011 						break;
  1016 	LOG_NOT_HANDLED_W(16);
  1019 /**
  1020  * @brief Write M68K memory, 8-bit
  1021  */
  1022 void m68k_write_memory_8(uint32_t address, uint32_t value)
  1024 	bool handled = false;
  1026 	// If ROMLMAP is set, force system to access ROM
  1027 	if (!state.romlmap)
  1028 		address |= 0x800000;
  1030 	// Check access permissions
  1031 	ACCESS_CHECK_WR(address, 8);
  1033 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
  1034 		// ROM access (read only!)
  1035 		handled = true;
  1036 	} else if (address <= (state.ram_size - 1)) {
  1037 		// RAM access
  1038 		WR8(state.ram, mapAddr(address, false), state.ram_size - 1, value);
  1039 		handled = true;
  1040 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
  1041 		// I/O register space, zone A
  1042 		switch (address & 0x0F0000) {
  1043 			case 0x000000:				// Map RAM access
  1044 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=%08X, data=%02X\n", address, value);
  1045 				WR8(state.map, address, 0x7FF, value);
  1046 				handled = true;
  1047 				break;
  1048 			case 0x010000:				// General Status Register
  1049 				handled = true;
  1050 				break;
  1051 			case 0x020000:				// Video RAM
  1052 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=%08X\n, data=0x%02X", address, value);
  1053 				WR8(state.vram, address, 0x7FFF, value);
  1054 				handled = true;
  1055 				break;
  1056 			case 0x030000:				// Bus Status Register 0
  1057 				handled = true;
  1058 				break;
  1059 			case 0x040000:				// Bus Status Register 1
  1060 				handled = true;
  1061 				break;
  1062 			case 0x050000:				// Phone status
  1063 				break;
  1064 			case 0x060000:				// DMA Count
  1065 				break;
  1066 			case 0x070000:				// Line Printer Status Register
  1067 				break;
  1068 			case 0x080000:				// Real Time Clock
  1069 				break;
  1070 			case 0x090000:				// Phone registers
  1071 				switch (address & 0x0FF000) {
  1072 					case 0x090000:		// Handset relay
  1073 					case 0x098000:
  1074 						break;
  1075 					case 0x091000:		// Line select 2
  1076 					case 0x099000:
  1077 						break;
  1078 					case 0x092000:		// Hook relay 1
  1079 					case 0x09A000:
  1080 						break;
  1081 					case 0x093000:		// Hook relay 2
  1082 					case 0x09B000:
  1083 						break;
  1084 					case 0x094000:		// Line 1 hold
  1085 					case 0x09C000:
  1086 						break;
  1087 					case 0x095000:		// Line 2 hold
  1088 					case 0x09D000:
  1089 						break;
  1090 					case 0x096000:		// Line 1 A-lead
  1091 					case 0x09E000:
  1092 						break;
  1093 					case 0x097000:		// Line 2 A-lead
  1094 					case 0x09F000:
  1095 						break;
  1097 				break;
  1098 			case 0x0A0000:				// Miscellaneous Control Register
  1099 				break;
  1100 			case 0x0B0000:				// TM/DIALWR
  1101 				break;
  1102 			case 0x0C0000:				// Clear Status Register
  1103 				state.genstat = 0xFFFF;
  1104 				state.bsr0 = 0xFFFF;
  1105 				state.bsr1 = 0xFFFF;
  1106 				handled = true;
  1107 				break;
  1108 			case 0x0D0000:				// DMA Address Register
  1109 				break;
  1110 			case 0x0E0000:				// Disk Control Register
  1111 				break;
  1112 			case 0x0F0000:				// Line Printer Data Register
  1113 				break;
  1115 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
  1116 		// I/O register space, zone B
  1117 		switch (address & 0xF00000) {
  1118 			case 0xC00000:				// Expansion slots
  1119 			case 0xD00000:
  1120 				switch (address & 0xFC0000) {
  1121 					case 0xC00000:		// Expansion slot 0
  1122 					case 0xC40000:		// Expansion slot 1
  1123 					case 0xC80000:		// Expansion slot 2
  1124 					case 0xCC0000:		// Expansion slot 3
  1125 					case 0xD00000:		// Expansion slot 4
  1126 					case 0xD40000:		// Expansion slot 5
  1127 					case 0xD80000:		// Expansion slot 6
  1128 					case 0xDC0000:		// Expansion slot 7
  1129 						fprintf(stderr, "NOTE: WR8 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
  1130 						break;
  1132 				break;
  1133 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
  1134 			case 0xF00000:
  1135 				switch (address & 0x070000) {
  1136 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
  1137 						break;
  1138 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
  1139 						break;
  1140 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
  1141 						break;
  1142 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
  1143 						break;
  1144 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
  1145 						switch (address & 0x077000) {
  1146 							case 0x040000:		// [ef][4c][08]xxx ==> EE
  1147 								break;
  1148 							case 0x041000:		// [ef][4c][19]xxx ==> P1E
  1149 								break;
  1150 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
  1151 								break;
  1152 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
  1153 								if ((address & 1) == 0)
  1154 									state.romlmap = ((value & 0x80) == 0x80);
  1155 								handled = true;
  1156 								break;
  1157 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
  1158 								break;
  1159 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
  1160 								break;
  1161 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
  1162 								break;
  1163 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
  1164 								break;
  1166 					case 0x050000:		// [ef][5d]xxxx ==> 8274
  1167 						break;
  1168 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
  1169 						switch (address & 0x07F000) {
  1170 							default:
  1171 								break;
  1173 						break;
  1174 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
  1175 						break;
  1176 					default:
  1177 						fprintf(stderr, "NOTE: WR8 to undefined E/F-block space, addr=0x%08X, data=0x%08X\n", address, value);
  1178 						break;
  1183 	LOG_NOT_HANDLED_W(8);
  1187 // for the disassembler
  1188 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
  1189 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
  1190 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }