src/memory.c

Fri, 04 Mar 2011 00:44:06 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Fri, 04 Mar 2011 00:44:06 +0000
changeset 102
4e1c29899aca
parent 100
d6f699f89303
child 103
b749a3356e8d
permissions
-rw-r--r--

add Error Enable bit to gcr write handler

     1 #include <stdio.h>
     2 #include <stdlib.h>
     3 #include <stdint.h>
     4 #include <stdbool.h>
     5 #include <assert.h>
     6 #include "musashi/m68k.h"
     7 #include "state.h"
     8 #include "utils.h"
     9 #include "memory.h"
    11 /******************
    12  * Memory mapping
    13  ******************/
    15 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
    17 uint32_t mapAddr(uint32_t addr, bool writing)/*{{{*/
    18 {
    19 	if (addr < 0x400000) {
    20 		// RAM access. Check against the Map RAM
    21 		// Start by getting the original page address
    22 		uint16_t page = (addr >> 12) & 0x3FF;
    24 		// Look it up in the map RAM and get the physical page address
    25 		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
    27 		// Update the Page Status bits
    28 		uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
    29 		// Pagebits --
    30 		//   0 = not present
    31 		//   1 = present but not accessed
    32 		//   2 = present, accessed (read from)
    33 		//   3 = present, dirty (written to)
    34 		switch (pagebits) {
    35 			case 0:
    36 				// Page not present
    37 				// This should cause a page fault
    38 				LOGS("Whoa! Pagebit update, when the page is not present!");
    39 				break;
    41 			case 1:
    42 				// Page present -- first access
    43 				state.map[page*2] &= 0x1F;	// turn off "present" bit
    44 				if (writing)
    45 					state.map[page*2] |= 0x60;		// Page written to (dirty)
    46 				else
    47 					state.map[page*2] |= 0x40;		// Page accessed but not written
    48 				break;
    50 			case 2:
    51 			case 3:
    52 				// Page present, 2nd or later access
    53 				if (writing)
    54 					state.map[page*2] |= 0x60;		// Page written to (dirty)
    55 				break;
    56 		}
    58 		// Return the address with the new physical page spliced in
    59 		return (new_page_addr << 12) + (addr & 0xFFF);
    60 	} else {
    61 		// I/O, VRAM or MapRAM space; no mapping is performed or required
    62 		// TODO: assert here?
    63 		return addr;
    64 	}
    65 }/*}}}*/
    67 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)/*{{{*/
    68 {
    69 	// Are we in Supervisor mode?
    70 	if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
    71 		// Yes. We can do anything we like.
    72 		return MEM_ALLOWED;
    74 	// If we're here, then we must be in User mode.
    75 	// Check that the user didn't access memory outside of the RAM area
    76 	if (addr >= 0x400000)
    77 		return MEM_UIE;
    79 	// This leaves us with Page Fault checking. Get the page bits for this page.
    80 	uint16_t page = (addr >> 12) & 0x3FF;
    81 	uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
    83 	// Check page is present
    84 	if ((pagebits & 0x03) == 0)
    85 		return MEM_PAGEFAULT;
    87 	// User attempt to access the kernel
    88 	// A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
    89 	if (((addr >> 19) & 0x0F) == 0)
    90 		return MEM_KERNEL;
    92 	// Check page is write enabled
    93 	if (writing && ((pagebits & 0x04) == 0))
    94 		return MEM_PAGE_NO_WE;
    96 	// Page access allowed.
    97 	return MEM_ALLOWED;
    98 }/*}}}*/
   100 #undef MAPRAM
   103 /********************************************************
   104  * m68k memory read/write support functions for Musashi
   105  ********************************************************/
   107 /**
   108  * @brief	Check memory access permissions for a write operation.
   109  * @note	This used to be a single macro (merged with ACCESS_CHECK_RD), but
   110  * 			gcc throws warnings when you have a return-with-value in a void
   111  * 			function, even if the return-with-value is completely unreachable.
   112  * 			Similarly it doesn't like it if you have a return without a value
   113  * 			in a non-void function, even if it's impossible to ever reach the
   114  * 			return-with-no-value. UGH!
   115  */
   116 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
   117 #define ACCESS_CHECK_WR(address, bits)								\
   118 	do {															\
   119 		bool fault = false;											\
   120 		/* MEM_STATUS st; */										\
   121 		switch (checkMemoryAccess(address, true)) {					\
   122 			case MEM_ALLOWED:										\
   123 				/* Access allowed */								\
   124 				break;												\
   125 			case MEM_PAGEFAULT:										\
   126 				/* Page fault */									\
   127 				state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0);	\
   128 				fault = true;										\
   129 				break;												\
   130 			case MEM_UIE:											\
   131 				/* User access to memory above 4MB */				\
   132 				state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0);	\
   133 				fault = true;										\
   134 				break;												\
   135 			case MEM_KERNEL:										\
   136 			case MEM_PAGE_NO_WE:									\
   137 				/* kernel access or page not write enabled */		\
   138 				/* FIXME: which regs need setting? */				\
   139 				fault = true;										\
   140 				break;												\
   141 		}															\
   142 																	\
   143 		if (fault) {												\
   144 			if (bits >= 16)											\
   145 				state.bsr0 = 0x7C00;								\
   146 			else													\
   147 				state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00;		\
   148 			state.bsr0 |= (address >> 16);							\
   149 			state.bsr1 = address & 0xffff;							\
   150 			printf("ERR: BusError WR\n");							\
   151 			m68k_pulse_bus_error();									\
   152 			return;													\
   153 		}															\
   154 	} while (0)
   155 /*}}}*/
   157 /**
   158  * @brief Check memory access permissions for a read operation.
   159  * @note	This used to be a single macro (merged with ACCESS_CHECK_WR), but
   160  * 			gcc throws warnings when you have a return-with-value in a void
   161  * 			function, even if the return-with-value is completely unreachable.
   162  * 			Similarly it doesn't like it if you have a return without a value
   163  * 			in a non-void function, even if it's impossible to ever reach the
   164  * 			return-with-no-value. UGH!
   165  */
   166 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
   167 #define ACCESS_CHECK_RD(address, bits)								\
   168 	do {															\
   169 		bool fault = false;											\
   170 		/* MEM_STATUS st; */										\
   171 		switch (checkMemoryAccess(address, false)) {				\
   172 			case MEM_ALLOWED:										\
   173 				/* Access allowed */								\
   174 				break;												\
   175 			case MEM_PAGEFAULT:										\
   176 				/* Page fault */									\
   177 				state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0);	\
   178 				fault = true;										\
   179 				break;												\
   180 			case MEM_UIE:											\
   181 				/* User access to memory above 4MB */				\
   182 				state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0);	\
   183 				fault = true;										\
   184 				break;												\
   185 			case MEM_KERNEL:										\
   186 			case MEM_PAGE_NO_WE:									\
   187 				/* kernel access or page not write enabled */		\
   188 				/* FIXME: which regs need setting? */				\
   189 				fault = true;										\
   190 				break;												\
   191 		}															\
   192 																	\
   193 		if (fault) {												\
   194 			if (bits >= 16)											\
   195 				state.bsr0 = 0x7C00;								\
   196 			else													\
   197 				state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00;		\
   198 			state.bsr0 |= (address >> 16);							\
   199 			state.bsr1 = address & 0xffff;							\
   200 			printf("ERR: BusError RD\n");							\
   201 			m68k_pulse_bus_error();									\
   202 			return 0xFFFFFFFF;										\
   203 		}															\
   204 	} while (0)
   205 /*}}}*/
   207 // Logging macros
   208 #define LOG_NOT_HANDLED_R(bits)															\
   209 	if (!handled) printf("unhandled read%02d, addr=0x%08X\n", bits, address);
   211 #define LOG_NOT_HANDLED_W(bits)															\
   212 	if (!handled) printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
   214 /********************************************************
   215  * I/O read/write functions
   216  ********************************************************/
   218 /**
   219  * Issue a warning if a read operation is made with an invalid size
   220  */
   221 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
   222 {
   223 	assert((bits == 8) || (bits == 16) || (bits == 32));
   224 	if ((bits & allowed) == 0) {
   225 		printf("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
   226 	}
   227 }
   229 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
   230 {
   231 	ENFORCE_SIZE(bits, address, true, allowed, regname);
   232 }
   234 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
   235 {
   236 	ENFORCE_SIZE(bits, address, false, allowed, regname);
   237 }
   239 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
   240 {
   241 	bool handled = false;
   243 	if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   244 		// I/O register space, zone A
   245 		switch (address & 0x0F0000) {
   246 			case 0x010000:				// General Status Register
   247 				if (bits == 16)
   248 					state.genstat = (data & 0xffff);
   249 				else if (bits == 8) {
   250 					if (address & 0)
   251 						state.genstat = data;
   252 					else
   253 						state.genstat = data << 8;
   254 				}
   255 				handled = true;
   256 				break;
   257 			case 0x030000:				// Bus Status Register 0
   258 				break;
   259 			case 0x040000:				// Bus Status Register 1
   260 				break;
   261 			case 0x050000:				// Phone status
   262 				break;
   263 			case 0x060000:				// DMA Count
   264 				ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
   265 				state.dma_count = (data & 0x3FFF);
   266 				state.idmarw = ((data & 0x4000) == 0x4000);
   267 				state.dmaen = ((data & 0x8000) == 0x8000);
   268 				// This handles the "dummy DMA transfer" mentioned in the docs
   269 				// TODO: access check, peripheral access
   270 				if (!state.idmarw)
   271 					WR32(state.base_ram, mapAddr(address, true), state.base_ram_size - 1, 0xDEAD);
   272 				state.dma_count++;
   273 				handled = true;
   274 				break;
   275 			case 0x070000:				// Line Printer Status Register
   276 				break;
   277 			case 0x080000:				// Real Time Clock
   278 				break;
   279 			case 0x090000:				// Phone registers
   280 				switch (address & 0x0FF000) {
   281 					case 0x090000:		// Handset relay
   282 					case 0x098000:
   283 						break;
   284 					case 0x091000:		// Line select 2
   285 					case 0x099000:
   286 						break;
   287 					case 0x092000:		// Hook relay 1
   288 					case 0x09A000:
   289 						break;
   290 					case 0x093000:		// Hook relay 2
   291 					case 0x09B000:
   292 						break;
   293 					case 0x094000:		// Line 1 hold
   294 					case 0x09C000:
   295 						break;
   296 					case 0x095000:		// Line 2 hold
   297 					case 0x09D000:
   298 						break;
   299 					case 0x096000:		// Line 1 A-lead
   300 					case 0x09E000:
   301 						break;
   302 					case 0x097000:		// Line 2 A-lead
   303 					case 0x09F000:
   304 						break;
   305 				}
   306 				break;
   307 			case 0x0A0000:				// Miscellaneous Control Register
   308 				ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
   309 				// TODO: handle the ctrl bits properly
   310 				// TODO: &0x8000 --> dismiss 60hz intr
   311 				if (data & 0x8000){
   312 					state.timer_enabled = 1;
   313 				}else{
   314 					state.timer_enabled = 0;
   315 					state.timer_asserted = 0;
   316 				}
   317 				state.dma_reading = (data & 0x4000);
   318 				if (state.leds != ((~data & 0xF00) >> 8)) {
   319 					state.leds = (~data & 0xF00) >> 8;
   320 					printf("LEDs: %s %s %s %s\n",
   321 							(state.leds & 8) ? "R" : "-",
   322 							(state.leds & 4) ? "G" : "-",
   323 							(state.leds & 2) ? "Y" : "-",
   324 							(state.leds & 1) ? "R" : "-");
   325 				}
   326 				handled = true;
   327 				break;
   328 			case 0x0B0000:				// TM/DIALWR
   329 				break;
   330 			case 0x0C0000:				// Clear Status Register
   331 				state.genstat = 0xFFFF;
   332 				state.bsr0 = 0xFFFF;
   333 				state.bsr1 = 0xFFFF;
   334 				handled = true;
   335 				break;
   336 			case 0x0D0000:				// DMA Address Register
   337 				if (address & 0x004000) {
   338 					// A14 high -- set most significant bits
   339 					state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
   340 				} else {
   341 					// A14 low -- set least significant bits
   342 					state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
   343 				}
   344 				handled = true;
   345 				break;
   346 			case 0x0E0000:				// Disk Control Register
   347 				ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
   348 				// B7 = FDD controller reset
   349 				if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
   350 				// B6 = drive 0 select -- TODO
   351 				// B5 = motor enable -- TODO
   352 				// B4 = HDD controller reset -- TODO
   353 				// B3 = HDD0 select -- TODO
   354 				// B2,1,0 = HDD0 head select
   355 				handled = true;
   356 				break;
   357 			case 0x0F0000:				// Line Printer Data Register
   358 				break;
   359 		}
   360 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   361 		// I/O register space, zone B
   362 		switch (address & 0xF00000) {
   363 			case 0xC00000:				// Expansion slots
   364 			case 0xD00000:
   365 				switch (address & 0xFC0000) {
   366 					case 0xC00000:		// Expansion slot 0
   367 					case 0xC40000:		// Expansion slot 1
   368 					case 0xC80000:		// Expansion slot 2
   369 					case 0xCC0000:		// Expansion slot 3
   370 					case 0xD00000:		// Expansion slot 4
   371 					case 0xD40000:		// Expansion slot 5
   372 					case 0xD80000:		// Expansion slot 6
   373 					case 0xDC0000:		// Expansion slot 7
   374 						fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
   375 						handled = true;
   376 						break;
   377 				}
   378 				break;
   379 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   380 			case 0xF00000:
   381 				switch (address & 0x070000) {
   382 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   383 						break;
   384 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   385 						ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");
   386 						wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
   387 						handled = true;
   388 						break;
   389 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   390 						break;
   391 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   392 						break;
   393 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   394 						switch (address & 0x077000) {
   395 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   396 								// Error Enable. If =0, Level7 intrs and bus errors are masked.
   397 								ENFORCE_SIZE_W(bits, address, 16, "EE");
   398 								state.ee = ((data & 0x8000) == 0x8000);
   399 								handled = true;
   400 								break;
   401 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   402 								ENFORCE_SIZE_W(bits, address, 16, "PIE");
   403 								state.pie = ((data & 0x8000) == 0x8000);
   404 								handled = true;
   405 								break;
   406 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   407 								break;
   408 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   409 								ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
   410 								state.romlmap = ((data & 0x8000) == 0x8000);
   411 								handled = true;
   412 								break;
   413 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   414 								ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
   415 								break;
   416 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   417 								ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
   418 								break;
   419 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   420 								ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
   421 								break;
   422 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   423 								ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
   424 								break;
   425 						}
   426 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   427 						break;
   428 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   429 						switch (address & 0x07F000) {
   430 							default:
   431 								break;
   432 						}
   433 						break;
   434 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   435 						// TODO: figure out which sizes are valid (probably just 8 and 16)
   436 						// ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER");
   437 						if (bits == 8) {
   438 							printf("KBD WR %02X => %02X\n", (address >> 1) & 3, data);
   439 							keyboard_write(&state.kbd, (address >> 1) & 3, data);
   440 							handled = true;
   441 						} else if (bits == 16) {
   442 							printf("KBD WR %02X => %04X\n", (address >> 1) & 3, data);
   443 							keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8);
   444 							handled = true;
   445 						}
   446 						break;
   447 				}
   448 		}
   449 	}
   451 	LOG_NOT_HANDLED_W(bits);
   452 }/*}}}*/
   454 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
   455 {
   456 	bool handled = false;
   457 	uint32_t data = 0xFFFFFFFF;
   459 	if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   460 		// I/O register space, zone A
   461 		switch (address & 0x0F0000) {
   462 			case 0x010000:				// General Status Register
   463 				ENFORCE_SIZE_R(bits, address, 16, "GENSTAT");
   464 				return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
   465 				break;
   466 			case 0x030000:				// Bus Status Register 0
   467 				ENFORCE_SIZE_R(bits, address, 16, "BSR0");
   468 				return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
   469 				break;
   470 			case 0x040000:				// Bus Status Register 1
   471 				ENFORCE_SIZE_R(bits, address, 16, "BSR1");
   472 				return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
   473 				break;
   474 			case 0x050000:				// Phone status
   475 				ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
   476 				break;
   477 			case 0x060000:				// DMA Count
   478 				// TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
   479 				// Bit 14 is always unused, so leave it set
   480 				ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
   481 				return (state.dma_count & 0x3fff) | 0xC000;
   482 				break;
   483 			case 0x070000:				// Line Printer Status Register
   484 				data = 0x00120012;	// no parity error, no line printer error, no irqs from FDD or HDD
   485 				data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0;
   486 				return data;
   487 				break;
   488 			case 0x080000:				// Real Time Clock
   489 				printf("READ NOTIMP: Realtime Clock\n");
   490 				break;
   491 			case 0x090000:				// Phone registers
   492 				switch (address & 0x0FF000) {
   493 					case 0x090000:		// Handset relay
   494 					case 0x098000:
   495 						break;
   496 					case 0x091000:		// Line select 2
   497 					case 0x099000:
   498 						break;
   499 					case 0x092000:		// Hook relay 1
   500 					case 0x09A000:
   501 						break;
   502 					case 0x093000:		// Hook relay 2
   503 					case 0x09B000:
   504 						break;
   505 					case 0x094000:		// Line 1 hold
   506 					case 0x09C000:
   507 						break;
   508 					case 0x095000:		// Line 2 hold
   509 					case 0x09D000:
   510 						break;
   511 					case 0x096000:		// Line 1 A-lead
   512 					case 0x09E000:
   513 						break;
   514 					case 0x097000:		// Line 2 A-lead
   515 					case 0x09F000:
   516 						break;
   517 				}
   518 				break;
   519 			case 0x0A0000:				// Miscellaneous Control Register -- write only!
   520 				handled = true;
   521 				break;
   522 			case 0x0B0000:				// TM/DIALWR
   523 				break;
   524 			case 0x0C0000:				// Clear Status Register -- write only!
   525 				handled = true;
   526 				break;
   527 			case 0x0D0000:				// DMA Address Register
   528 				break;
   529 			case 0x0E0000:				// Disk Control Register
   530 				break;
   531 			case 0x0F0000:				// Line Printer Data Register
   532 				break;
   533 		}
   534 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   535 		// I/O register space, zone B
   536 		switch (address & 0xF00000) {
   537 			case 0xC00000:				// Expansion slots
   538 			case 0xD00000:
   539 				switch (address & 0xFC0000) {
   540 					case 0xC00000:		// Expansion slot 0
   541 					case 0xC40000:		// Expansion slot 1
   542 					case 0xC80000:		// Expansion slot 2
   543 					case 0xCC0000:		// Expansion slot 3
   544 					case 0xD00000:		// Expansion slot 4
   545 					case 0xD40000:		// Expansion slot 5
   546 					case 0xD80000:		// Expansion slot 6
   547 					case 0xDC0000:		// Expansion slot 7
   548 						fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
   549 						handled = true;
   550 						break;
   551 				}
   552 				break;
   553 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   554 			case 0xF00000:
   555 				switch (address & 0x070000) {
   556 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   557 						break;
   558 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   559 						ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");
   560 						return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
   561 						break;
   562 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   563 						break;
   564 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   565 						break;
   566 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   567 						switch (address & 0x077000) {
   568 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   569 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   570 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   571 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   572 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   573 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   574 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   575 								// All write-only registers... TODO: bus error?
   576 								handled = true;
   577 								break;
   578 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
   579 								break;
   580 						}
   581 						break;
   582 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   583 						break;
   584 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   585 						switch (address & 0x07F000) {
   586 							default:
   587 								break;
   588 						}
   589 						break;
   590 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   591 						// TODO: figure out which sizes are valid (probably just 8 and 16)
   592 						//ENFORCE_SIZE_R(bits, address, 16, "KEYBOARD CONTROLLER");
   593 						{
   594 							if (bits == 8) {
   595 								return keyboard_read(&state.kbd, (address >> 1) & 3);
   596 							} else {
   597 								return keyboard_read(&state.kbd, (address >> 1) & 3) << 8;
   598 							}
   599 							return data;
   600 						}
   601 						break;
   602 				}
   603 		}
   604 	}
   606 	LOG_NOT_HANDLED_R(bits);
   608 	return data;
   609 }/*}}}*/
   612 /********************************************************
   613  * m68k memory read/write support functions for Musashi
   614  ********************************************************/
   616 /**
   617  * @brief Read M68K memory, 32-bit
   618  */
   619 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
   620 {
   621 	uint32_t data = 0xFFFFFFFF;
   623 	// If ROMLMAP is set, force system to access ROM
   624 	if (!state.romlmap)
   625 		address |= 0x800000;
   627 	// Check access permissions
   628 	ACCESS_CHECK_RD(address, 32);
   630 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   631 		// ROM access
   632 		return RD32(state.rom, address, ROM_SIZE - 1);
   633 	} else if (address <= 0x3fffff) {
   634 		// RAM access
   635 		uint32_t newAddr = mapAddr(address, false);
   636 		if (newAddr <= 0x1fffff) {
   637 			return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
   638 		} else {
   639 			if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
   640 				return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   641 			else
   642 				return 0xffffffff;
   643 		}
   644 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   645 		// I/O register space, zone A
   646 		switch (address & 0x0F0000) {
   647 			case 0x000000:				// Map RAM access
   648 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
   649 				return RD32(state.map, address, 0x7FF);
   650 				break;
   651 			case 0x020000:				// Video RAM
   652 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
   653 				return RD32(state.vram, address, 0x7FFF);
   654 				break;
   655 			default:
   656 				return IoRead(address, 32);
   657 		}
   658 	} else {
   659 		return IoRead(address, 32);
   660 	}
   662 	return data;
   663 }/*}}}*/
   665 /**
   666  * @brief Read M68K memory, 16-bit
   667  */
   668 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
   669 {
   670 	uint16_t data = 0xFFFF;
   672 	// If ROMLMAP is set, force system to access ROM
   673 	if (!state.romlmap)
   674 		address |= 0x800000;
   676 	// Check access permissions
   677 	ACCESS_CHECK_RD(address, 16);
   679 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   680 		// ROM access
   681 		data = RD16(state.rom, address, ROM_SIZE - 1);
   682 	} else if (address <= 0x3fffff) {
   683 		// RAM access
   684 		uint32_t newAddr = mapAddr(address, false);
   685 		if (newAddr <= 0x1fffff) {
   686 			return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
   687 		} else {
   688 			if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
   689 				return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   690 			else
   691 				return 0xffff;
   692 		}
   693 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   694 		// I/O register space, zone A
   695 		switch (address & 0x0F0000) {
   696 			case 0x000000:				// Map RAM access
   697 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
   698 				data = RD16(state.map, address, 0x7FF);
   699 				break;
   700 			case 0x020000:				// Video RAM
   701 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
   702 				data = RD16(state.vram, address, 0x7FFF);
   703 				break;
   704 			default:
   705 				data = IoRead(address, 16);
   706 		}
   707 	} else {
   708 		data = IoRead(address, 16);
   709 	}
   711 	return data;
   712 }/*}}}*/
   714 /**
   715  * @brief Read M68K memory, 8-bit
   716  */
   717 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
   718 {
   719 	uint8_t data = 0xFF;
   721 	// If ROMLMAP is set, force system to access ROM
   722 	if (!state.romlmap)
   723 		address |= 0x800000;
   725 	// Check access permissions
   726 	ACCESS_CHECK_RD(address, 8);
   728 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   729 		// ROM access
   730 		data = RD8(state.rom, address, ROM_SIZE - 1);
   731 	} else if (address <= 0x3fffff) {
   732 		// RAM access
   733 		uint32_t newAddr = mapAddr(address, false);
   734 		if (newAddr <= 0x1fffff) {
   735 			return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
   736 		} else {
   737 			if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
   738 				return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   739 			else
   740 				return 0xff;
   741 		}
   742 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   743 		// I/O register space, zone A
   744 		switch (address & 0x0F0000) {
   745 			case 0x000000:				// Map RAM access
   746 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
   747 				data = RD8(state.map, address, 0x7FF);
   748 				break;
   749 			case 0x020000:				// Video RAM
   750 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
   751 				data = RD8(state.vram, address, 0x7FFF);
   752 				break;
   753 			default:
   754 				data = IoRead(address, 8);
   755 		}
   756 	} else {
   757 		data = IoRead(address, 8);
   758 	}
   760 	return data;
   761 }/*}}}*/
   763 /**
   764  * @brief Write M68K memory, 32-bit
   765  */
   766 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
   767 {
   768 	// If ROMLMAP is set, force system to access ROM
   769 	if (!state.romlmap)
   770 		address |= 0x800000;
   772 	// Check access permissions
   773 	ACCESS_CHECK_WR(address, 32);
   775 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   776 		// ROM access
   777 	} else if (address <= 0x3FFFFF) {
   778 		// RAM access
   779 		uint32_t newAddr = mapAddr(address, true);
   780 		if (newAddr <= 0x1fffff)
   781 			WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
   782 		else
   783 			WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   784 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   785 		// I/O register space, zone A
   786 		switch (address & 0x0F0000) {
   787 			case 0x000000:				// Map RAM access
   788 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
   789 				WR32(state.map, address, 0x7FF, value);
   790 				break;
   791 			case 0x020000:				// Video RAM
   792 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
   793 				WR32(state.vram, address, 0x7FFF, value);
   794 				break;
   795 			default:
   796 				IoWrite(address, value, 32);
   797 		}
   798 	} else {
   799 		IoWrite(address, value, 32);
   800 	}
   801 }/*}}}*/
   803 /**
   804  * @brief Write M68K memory, 16-bit
   805  */
   806 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
   807 {
   808 	// If ROMLMAP is set, force system to access ROM
   809 	if (!state.romlmap)
   810 		address |= 0x800000;
   812 	// Check access permissions
   813 	ACCESS_CHECK_WR(address, 16);
   815 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   816 		// ROM access
   817 	} else if (address <= 0x3FFFFF) {
   818 		// RAM access
   819 		uint32_t newAddr = mapAddr(address, true);
   820 		if (newAddr <= 0x1fffff)
   821 			WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
   822 		else
   823 			WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   824 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   825 		// I/O register space, zone A
   826 		switch (address & 0x0F0000) {
   827 			case 0x000000:				// Map RAM access
   828 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   829 				WR16(state.map, address, 0x7FF, value);
   830 				break;
   831 			case 0x020000:				// Video RAM
   832 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   833 				WR16(state.vram, address, 0x7FFF, value);
   834 				break;
   835 			default:
   836 				IoWrite(address, value, 16);
   837 		}
   838 	} else {
   839 		IoWrite(address, value, 16);
   840 	}
   841 }/*}}}*/
   843 /**
   844  * @brief Write M68K memory, 8-bit
   845  */
   846 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
   847 {
   848 	// If ROMLMAP is set, force system to access ROM
   849 	if (!state.romlmap)
   850 		address |= 0x800000;
   852 	// Check access permissions
   853 	ACCESS_CHECK_WR(address, 8);
   855 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   856 		// ROM access (read only!)
   857 	} else if (address <= 0x3FFFFF) {
   858 		// RAM access
   859 		uint32_t newAddr = mapAddr(address, true);
   860 		if (newAddr <= 0x1fffff)
   861 			WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
   862 		else
   863 			WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   864 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   865 		// I/O register space, zone A
   866 		switch (address & 0x0F0000) {
   867 			case 0x000000:				// Map RAM access
   868 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   869 				WR8(state.map, address, 0x7FF, value);
   870 				break;
   871 			case 0x020000:				// Video RAM
   872 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   873 				WR8(state.vram, address, 0x7FFF, value);
   874 				break;
   875 			default:
   876 				IoWrite(address, value, 8);
   877 		}
   878 	} else {
   879 		IoWrite(address, value, 8);
   880 	}
   881 }/*}}}*/
   884 // for the disassembler
   885 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
   886 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
   887 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }