src/memory.c

Tue, 28 Dec 2010 18:19:48 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Tue, 28 Dec 2010 18:19:48 +0000
changeset 64
5005879cb6fc
parent 63
f772d3c40531
child 65
dc28926b353c
permissions
-rw-r--r--

turn logging of unhandled I/O R/W ops back on

     1 #include <stdio.h>
     2 #include <stdlib.h>
     3 #include <stdint.h>
     4 #include <stdbool.h>
     5 #include <assert.h>
     6 #include "musashi/m68k.h"
     7 #include "state.h"
     8 #include "memory.h"
    10 /******************
    11  * Memory mapping
    12  ******************/
    14 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
    16 uint32_t mapAddr(uint32_t addr, bool writing)/*{{{*/
    17 {
    18 	if (addr < 0x400000) {
    19 		// RAM access. Check against the Map RAM
    20 		// Start by getting the original page address
    21 		uint16_t page = (addr >> 12) & 0x3FF;
    23 		// Look it up in the map RAM and get the physical page address
    24 		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
    26 		// Update the Page Status bits
    27 		uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
    28 		if (pagebits != 0) {
    29 			if (writing)
    30 				state.map[page*2] |= 0x60;		// Page written to (dirty)
    31 			else
    32 				state.map[page*2] |= 0x40;		// Page accessed but not written
    33 		}
    35 		// Return the address with the new physical page spliced in
    36 		return (new_page_addr << 12) + (addr & 0xFFF);
    37 	} else {
    38 		// I/O, VRAM or MapRAM space; no mapping is performed or required
    39 		// TODO: assert here?
    40 		return addr;
    41 	}
    42 }/*}}}*/
    44 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)/*{{{*/
    45 {
    46 	// Are we in Supervisor mode?
    47 	if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
    48 		// Yes. We can do anything we like.
    49 		return MEM_ALLOWED;
    51 	// If we're here, then we must be in User mode.
    52 	// Check that the user didn't access memory outside of the RAM area
    53 	if (addr >= 0x400000)
    54 		return MEM_UIE;
    56 	// This leaves us with Page Fault checking. Get the page bits for this page.
    57 	uint16_t page = (addr >> 12) & 0x3FF;
    58 	uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
    60 	// Check page is present
    61 	if ((pagebits & 0x03) == 0)
    62 		return MEM_PAGEFAULT;
    64 	// User attempt to access the kernel
    65 	// A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
    66 	if (((addr >> 19) & 0x0F) == 0)
    67 		return MEM_KERNEL;
    69 	// Check page is write enabled
    70 	if ((pagebits & 0x04) == 0)
    71 		return MEM_PAGE_NO_WE;
    73 	// Page access allowed.
    74 	return MEM_ALLOWED;
    75 }/*}}}*/
    77 #undef MAPRAM
    80 /********************************************************
    81  * m68k memory read/write support functions for Musashi
    82  ********************************************************/
    84 /**
    85  * @brief	Check memory access permissions for a write operation.
    86  * @note	This used to be a single macro (merged with ACCESS_CHECK_RD), but
    87  * 			gcc throws warnings when you have a return-with-value in a void
    88  * 			function, even if the return-with-value is completely unreachable.
    89  * 			Similarly it doesn't like it if you have a return without a value
    90  * 			in a non-void function, even if it's impossible to ever reach the
    91  * 			return-with-no-value. UGH!
    92  */
    93 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
    94 #define ACCESS_CHECK_WR(address, bits)								\
    95 	do {															\
    96 		bool fault = false;											\
    97 		/* MEM_STATUS st; */										\
    98 		switch (checkMemoryAccess(address, true)) {					\
    99 			case MEM_ALLOWED:										\
   100 				/* Access allowed */								\
   101 				break;												\
   102 			case MEM_PAGEFAULT:										\
   103 				/* Page fault */									\
   104 				state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0);	\
   105 				fault = true;										\
   106 				break;												\
   107 			case MEM_UIE:											\
   108 				/* User access to memory above 4MB */				\
   109 				state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0);	\
   110 				fault = true;										\
   111 				break;												\
   112 			case MEM_KERNEL:										\
   113 			case MEM_PAGE_NO_WE:									\
   114 				/* kernel access or page not write enabled */		\
   115 				/* TODO: which regs need setting? */				\
   116 				fault = true;										\
   117 				break;												\
   118 		}															\
   119 																	\
   120 		if (fault) {												\
   121 			if (bits >= 16)											\
   122 				state.bsr0 = 0x7F00;								\
   123 			else													\
   124 				state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00;		\
   125 			state.bsr0 |= (address >> 16);							\
   126 			state.bsr1 = address & 0xffff;							\
   127 			printf("ERR: BusError WR\n");							\
   128 			m68k_pulse_bus_error();									\
   129 			return;													\
   130 		}															\
   131 	} while (false)
   132 /*}}}*/
   134 /**
   135  * @brief Check memory access permissions for a read operation.
   136  * @note	This used to be a single macro (merged with ACCESS_CHECK_WR), but
   137  * 			gcc throws warnings when you have a return-with-value in a void
   138  * 			function, even if the return-with-value is completely unreachable.
   139  * 			Similarly it doesn't like it if you have a return without a value
   140  * 			in a non-void function, even if it's impossible to ever reach the
   141  * 			return-with-no-value. UGH!
   142  */
   143 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
   144 #define ACCESS_CHECK_RD(address, bits)								\
   145 	do {															\
   146 		bool fault = false;											\
   147 		/* MEM_STATUS st; */										\
   148 		switch (checkMemoryAccess(address, false)) {				\
   149 			case MEM_ALLOWED:										\
   150 				/* Access allowed */								\
   151 				break;												\
   152 			case MEM_PAGEFAULT:										\
   153 				/* Page fault */									\
   154 				state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0);	\
   155 				fault = true;										\
   156 				break;												\
   157 			case MEM_UIE:											\
   158 				/* User access to memory above 4MB */				\
   159 				state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0);	\
   160 				fault = true;										\
   161 				break;												\
   162 			case MEM_KERNEL:										\
   163 			case MEM_PAGE_NO_WE:									\
   164 				/* kernel access or page not write enabled */		\
   165 				/* TODO: which regs need setting? */				\
   166 				fault = true;										\
   167 				break;												\
   168 		}															\
   169 																	\
   170 		if (fault) {												\
   171 			if (bits >= 16)											\
   172 				state.bsr0 = 0x7F00;								\
   173 			else													\
   174 				state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00;		\
   175 			state.bsr0 |= (address >> 16);							\
   176 			state.bsr1 = address & 0xffff;							\
   177 			printf("ERR: BusError RD\n");							\
   178 			m68k_pulse_bus_error();									\
   179 			return 0xFFFFFFFF;										\
   180 		}															\
   181 	} while (false)
   182 /*}}}*/
   184 // Logging macros
   185 #define LOG_NOT_HANDLED_R(bits)															\
   186 	if (!handled) printf("unhandled read%02d, addr=0x%08X\n", bits, address);
   188 #define LOG_NOT_HANDLED_W(bits)															\
   189 	if (!handled) printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
   191 /********************************************************
   192  * I/O read/write functions
   193  ********************************************************/
   195 /**
   196  * Issue a warning if a read operation is made with an invalid size
   197  */
   198 inline static void ENFORCE_SIZE(int bits, uint32_t address, int allowed, char *regname)
   199 {
   200 	assert((bits == 8) || (bits == 16) || (bits == 32));
   201 	if ((bits & allowed) == 0) {
   202 		printf("WARNING: write to 0x%08X (%s) with invalid size %d!\n", address, regname, bits);
   203 	}
   204 }
   206 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
   207 {
   208 	bool handled = false;
   210 	if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   211 		// I/O register space, zone A
   212 		switch (address & 0x0F0000) {
   213 			case 0x010000:				// General Status Register
   214 				if (bits == 16)
   215 					state.genstat = (data & 0xffff);
   216 				else if (bits == 8) {
   217 					if (address & 0)
   218 						state.genstat = data;
   219 					else
   220 						state.genstat = data << 8;
   221 				}
   222 				handled = true;
   223 				break;
   224 			case 0x030000:				// Bus Status Register 0
   225 				break;
   226 			case 0x040000:				// Bus Status Register 1
   227 				break;
   228 			case 0x050000:				// Phone status
   229 				break;
   230 			case 0x060000:				// DMA Count
   231 				ENFORCE_SIZE(bits, address, 16, "DMACOUNT");
   232 				state.dma_count = (data & 0x3FFF);
   233 				state.idmarw = ((data & 0x4000) == 0x4000);
   234 				state.dmaen = ((data & 0x8000) == 0x8000);
   235 				// This handles the "dummy DMA transfer" mentioned in the docs
   236 				// TODO: access check, peripheral access
   237 				if (!state.idmarw)
   238 					WR32(state.base_ram, mapAddr(address, true), state.base_ram_size - 1, 0xDEAD);
   239 				state.dma_count++;
   240 				handled = true;
   241 				break;
   242 			case 0x070000:				// Line Printer Status Register
   243 				break;
   244 			case 0x080000:				// Real Time Clock
   245 				break;
   246 			case 0x090000:				// Phone registers
   247 				switch (address & 0x0FF000) {
   248 					case 0x090000:		// Handset relay
   249 					case 0x098000:
   250 						break;
   251 					case 0x091000:		// Line select 2
   252 					case 0x099000:
   253 						break;
   254 					case 0x092000:		// Hook relay 1
   255 					case 0x09A000:
   256 						break;
   257 					case 0x093000:		// Hook relay 2
   258 					case 0x09B000:
   259 						break;
   260 					case 0x094000:		// Line 1 hold
   261 					case 0x09C000:
   262 						break;
   263 					case 0x095000:		// Line 2 hold
   264 					case 0x09D000:
   265 						break;
   266 					case 0x096000:		// Line 1 A-lead
   267 					case 0x09E000:
   268 						break;
   269 					case 0x097000:		// Line 2 A-lead
   270 					case 0x09F000:
   271 						break;
   272 				}
   273 				break;
   274 			case 0x0A0000:				// Miscellaneous Control Register
   275 				ENFORCE_SIZE(bits, address, 16, "MISCCON");
   276 				// TODO: handle the ctrl bits properly
   277 				// TODO: &0x8000 --> dismiss 60hz intr
   278 				state.dma_reading = (data & 0x4000);
   279 				state.leds = (~data & 0xF00) >> 8;
   280 				printf("LEDs: %s %s %s %s\n",
   281 						(state.leds & 8) ? "R" : "-",
   282 						(state.leds & 4) ? "G" : "-",
   283 						(state.leds & 2) ? "Y" : "-",
   284 						(state.leds & 1) ? "R" : "-");
   285 				handled = true;
   286 				break;
   287 			case 0x0B0000:				// TM/DIALWR
   288 				break;
   289 			case 0x0C0000:				// Clear Status Register
   290 				state.genstat = 0xFFFF;
   291 				state.bsr0 = 0xFFFF;
   292 				state.bsr1 = 0xFFFF;
   293 				handled = true;
   294 				break;
   295 			case 0x0D0000:				// DMA Address Register
   296 				if (address & 0x004000) {
   297 					// A14 high -- set most significant bits
   298 					state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
   299 				} else {
   300 					// A14 low -- set least significant bits
   301 					state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
   302 				}
   303 				handled = true;
   304 				break;
   305 			case 0x0E0000:				// Disk Control Register
   306 				ENFORCE_SIZE(bits, address, 16, "DISKCON");
   307 				// B7 = FDD controller reset
   308 				if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
   309 				// B6 = drive 0 select -- TODO
   310 				// B5 = motor enable -- TODO
   311 				// B4 = HDD controller reset -- TODO
   312 				// B3 = HDD0 select -- TODO
   313 				// B2,1,0 = HDD0 head select
   314 				handled = true;
   315 				break;
   316 			case 0x0F0000:				// Line Printer Data Register
   317 				break;
   318 		}
   319 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   320 		// I/O register space, zone B
   321 		switch (address & 0xF00000) {
   322 			case 0xC00000:				// Expansion slots
   323 			case 0xD00000:
   324 				switch (address & 0xFC0000) {
   325 					case 0xC00000:		// Expansion slot 0
   326 					case 0xC40000:		// Expansion slot 1
   327 					case 0xC80000:		// Expansion slot 2
   328 					case 0xCC0000:		// Expansion slot 3
   329 					case 0xD00000:		// Expansion slot 4
   330 					case 0xD40000:		// Expansion slot 5
   331 					case 0xD80000:		// Expansion slot 6
   332 					case 0xDC0000:		// Expansion slot 7
   333 						fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
   334 						handled = true;
   335 						break;
   336 				}
   337 				break;
   338 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   339 			case 0xF00000:
   340 				switch (address & 0x070000) {
   341 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   342 						break;
   343 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   344 						ENFORCE_SIZE(bits, address, 16, "FDC REGISTERS");
   345 						wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
   346 						handled = true;
   347 						break;
   348 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   349 						break;
   350 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   351 						break;
   352 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   353 						switch (address & 0x077000) {
   354 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   355 								break;
   356 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   357 								ENFORCE_SIZE(bits, address, 16, "PIE");
   358 								state.pie = ((data & 0x8000) == 0x8000);
   359 								handled = true;
   360 								break;
   361 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   362 								break;
   363 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   364 								ENFORCE_SIZE(bits, address, 16, "ROMLMAP");
   365 								state.romlmap = ((data & 0x8000) == 0x8000);
   366 								handled = true;
   367 								break;
   368 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   369 								ENFORCE_SIZE(bits, address, 16, "L1 MODEM");
   370 								break;
   371 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   372 								ENFORCE_SIZE(bits, address, 16, "L2 MODEM");
   373 								break;
   374 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   375 								ENFORCE_SIZE(bits, address, 16, "D/N CONNECT");
   376 								break;
   377 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   378 								ENFORCE_SIZE(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
   379 								break;
   380 						}
   381 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   382 						break;
   383 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   384 						switch (address & 0x07F000) {
   385 							default:
   386 								break;
   387 						}
   388 						break;
   389 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   390 						break;
   391 				}
   392 		}
   393 	}
   395 	LOG_NOT_HANDLED_W(bits);
   396 }/*}}}*/
   398 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
   399 {
   400 	bool handled = false;
   401 	uint32_t data = 0xFFFFFFFF;
   403 	if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   404 		// I/O register space, zone A
   405 		switch (address & 0x0F0000) {
   406 			case 0x010000:				// General Status Register
   407 				ENFORCE_SIZE(bits, address, 16, "GENSTAT");
   408 				return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
   409 				break;
   410 			case 0x030000:				// Bus Status Register 0
   411 				ENFORCE_SIZE(bits, address, 16, "BSR0");
   412 				return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
   413 				break;
   414 			case 0x040000:				// Bus Status Register 1
   415 				ENFORCE_SIZE(bits, address, 16, "BSR1");
   416 				return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
   417 				break;
   418 			case 0x050000:				// Phone status
   419 				ENFORCE_SIZE(bits, address, 16, "PHONE STATUS");
   420 				break;
   421 			case 0x060000:				// DMA Count
   422 				// TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
   423 				// Bit 14 is always unused, so leave it set
   424 				ENFORCE_SIZE(bits, address, 16, "DMACOUNT");
   425 				return (state.dma_count & 0x3fff) | 0xC000;
   426 				break;
   427 			case 0x070000:				// Line Printer Status Register
   428 				data = 0x00120012;	// no parity error, no line printer error, no irqs from FDD or HDD
   429 				data |= (state.fdc_ctx.irql) ? 0x00080008 : 0;	// FIXME! HACKHACKHACK! shouldn't peek inside FDC structs like this
   430 				return data;
   431 				break;
   432 			case 0x080000:				// Real Time Clock
   433 				printf("READ NOTIMP: Realtime Clock\n");
   434 				break;
   435 			case 0x090000:				// Phone registers
   436 				switch (address & 0x0FF000) {
   437 					case 0x090000:		// Handset relay
   438 					case 0x098000:
   439 						break;
   440 					case 0x091000:		// Line select 2
   441 					case 0x099000:
   442 						break;
   443 					case 0x092000:		// Hook relay 1
   444 					case 0x09A000:
   445 						break;
   446 					case 0x093000:		// Hook relay 2
   447 					case 0x09B000:
   448 						break;
   449 					case 0x094000:		// Line 1 hold
   450 					case 0x09C000:
   451 						break;
   452 					case 0x095000:		// Line 2 hold
   453 					case 0x09D000:
   454 						break;
   455 					case 0x096000:		// Line 1 A-lead
   456 					case 0x09E000:
   457 						break;
   458 					case 0x097000:		// Line 2 A-lead
   459 					case 0x09F000:
   460 						break;
   461 				}
   462 				break;
   463 			case 0x0A0000:				// Miscellaneous Control Register -- write only!
   464 				handled = true;
   465 				break;
   466 			case 0x0B0000:				// TM/DIALWR
   467 				break;
   468 			case 0x0C0000:				// Clear Status Register -- write only!
   469 				handled = true;
   470 				break;
   471 			case 0x0D0000:				// DMA Address Register
   472 				break;
   473 			case 0x0E0000:				// Disk Control Register
   474 				break;
   475 			case 0x0F0000:				// Line Printer Data Register
   476 				break;
   477 		}
   478 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   479 		// I/O register space, zone B
   480 		switch (address & 0xF00000) {
   481 			case 0xC00000:				// Expansion slots
   482 			case 0xD00000:
   483 				switch (address & 0xFC0000) {
   484 					case 0xC00000:		// Expansion slot 0
   485 					case 0xC40000:		// Expansion slot 1
   486 					case 0xC80000:		// Expansion slot 2
   487 					case 0xCC0000:		// Expansion slot 3
   488 					case 0xD00000:		// Expansion slot 4
   489 					case 0xD40000:		// Expansion slot 5
   490 					case 0xD80000:		// Expansion slot 6
   491 					case 0xDC0000:		// Expansion slot 7
   492 						fprintf(stderr, "NOTE: RD32 from expansion card space, addr=0x%08X\n", address);
   493 						break;
   494 				}
   495 				break;
   496 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   497 			case 0xF00000:
   498 				switch (address & 0x070000) {
   499 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   500 						break;
   501 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   502 						ENFORCE_SIZE(bits, address, 16, "FDC REGISTERS");
   503 						return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
   504 						break;
   505 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   506 						break;
   507 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   508 						break;
   509 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   510 						switch (address & 0x077000) {
   511 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   512 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   513 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   514 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   515 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   516 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   517 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   518 								// All write-only registers... TODO: bus error?
   519 								handled = true;
   520 								break;
   521 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
   522 								break;
   523 						}
   524 						break;
   525 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   526 						break;
   527 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   528 						switch (address & 0x07F000) {
   529 							default:
   530 								break;
   531 						}
   532 						break;
   533 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   534 						break;
   535 				}
   536 		}
   537 	}
   539 	LOG_NOT_HANDLED_R(bits);
   541 	return data;
   542 }/*}}}*/
   545 /********************************************************
   546  * m68k memory read/write support functions for Musashi
   547  ********************************************************/
   549 /**
   550  * @brief Read M68K memory, 32-bit
   551  */
   552 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
   553 {
   554 	uint32_t data = 0xFFFFFFFF;
   556 	// If ROMLMAP is set, force system to access ROM
   557 	if (!state.romlmap)
   558 		address |= 0x800000;
   560 	// Check access permissions
   561 	ACCESS_CHECK_RD(address, 32);
   563 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   564 		// ROM access
   565 		return RD32(state.rom, address, ROM_SIZE - 1);
   566 	} else if (address <= 0x3fffff) {
   567 		// RAM access
   568 		uint32_t newAddr = mapAddr(address, false);
   569 		if (newAddr <= 0x1fffff) {
   570 			return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
   571 		} else {
   572 			if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
   573 				return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   574 			else
   575 				return 0xffffffff;
   576 		}
   577 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   578 		// I/O register space, zone A
   579 		switch (address & 0x0F0000) {
   580 			case 0x000000:				// Map RAM access
   581 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
   582 				return RD32(state.map, address, 0x7FF);
   583 				break;
   584 			case 0x020000:				// Video RAM
   585 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
   586 				return RD32(state.vram, address, 0x7FFF);
   587 				break;
   588 			default:
   589 				return IoRead(address, 32);
   590 		}
   591 	} else {
   592 		return IoRead(address, 32);
   593 	}
   595 	return data;
   596 }/*}}}*/
   598 /**
   599  * @brief Read M68K memory, 16-bit
   600  */
   601 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
   602 {
   603 	uint16_t data = 0xFFFF;
   605 	// If ROMLMAP is set, force system to access ROM
   606 	if (!state.romlmap)
   607 		address |= 0x800000;
   609 	// Check access permissions
   610 	ACCESS_CHECK_RD(address, 16);
   612 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   613 		// ROM access
   614 		data = RD16(state.rom, address, ROM_SIZE - 1);
   615 	} else if (address <= 0x3fffff) {
   616 		// RAM access
   617 		uint32_t newAddr = mapAddr(address, false);
   618 		if (newAddr <= 0x1fffff) {
   619 			return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
   620 		} else {
   621 			if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
   622 				return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   623 			else
   624 				return 0xffff;
   625 		}
   626 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   627 		// I/O register space, zone A
   628 		switch (address & 0x0F0000) {
   629 			case 0x000000:				// Map RAM access
   630 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
   631 				data = RD16(state.map, address, 0x7FF);
   632 				break;
   633 			case 0x020000:				// Video RAM
   634 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
   635 				data = RD16(state.vram, address, 0x7FFF);
   636 				break;
   637 			default:
   638 				data = IoRead(address, 16);
   639 		}
   640 	} else {
   641 		data = IoRead(address, 16);
   642 	}
   644 	return data;
   645 }/*}}}*/
   647 /**
   648  * @brief Read M68K memory, 8-bit
   649  */
   650 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
   651 {
   652 	uint8_t data = 0xFF;
   654 	// If ROMLMAP is set, force system to access ROM
   655 	if (!state.romlmap)
   656 		address |= 0x800000;
   658 	// Check access permissions
   659 	ACCESS_CHECK_RD(address, 8);
   661 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   662 		// ROM access
   663 		data = RD8(state.rom, address, ROM_SIZE - 1);
   664 	} else if (address <= 0x3fffff) {
   665 		// RAM access
   666 		uint32_t newAddr = mapAddr(address, false);
   667 		if (newAddr <= 0x1fffff) {
   668 			return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
   669 		} else {
   670 			if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
   671 				return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   672 			else
   673 				return 0xff;
   674 		}
   675 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   676 		// I/O register space, zone A
   677 		switch (address & 0x0F0000) {
   678 			case 0x000000:				// Map RAM access
   679 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
   680 				data = RD8(state.map, address, 0x7FF);
   681 				break;
   682 			case 0x020000:				// Video RAM
   683 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
   684 				data = RD8(state.vram, address, 0x7FFF);
   685 				break;
   686 			default:
   687 				data = IoRead(address, 8);
   688 		}
   689 	} else {
   690 		data = IoRead(address, 8);
   691 	}
   693 	return data;
   694 }/*}}}*/
   696 /**
   697  * @brief Write M68K memory, 32-bit
   698  */
   699 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
   700 {
   701 	// If ROMLMAP is set, force system to access ROM
   702 	if (!state.romlmap)
   703 		address |= 0x800000;
   705 	// Check access permissions
   706 	ACCESS_CHECK_WR(address, 32);
   708 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   709 		// ROM access
   710 	} else if (address <= 0x3FFFFF) {
   711 		// RAM access
   712 		uint32_t newAddr = mapAddr(address, true);
   713 		if (newAddr <= 0x1fffff) {
   714 			WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
   715 		} else {
   716 //			WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   717 		}
   718 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   719 		// I/O register space, zone A
   720 		switch (address & 0x0F0000) {
   721 			case 0x000000:				// Map RAM access
   722 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
   723 				WR32(state.map, address, 0x7FF, value);
   724 				break;
   725 			case 0x020000:				// Video RAM
   726 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
   727 				WR32(state.vram, address, 0x7FFF, value);
   728 				break;
   729 			default:
   730 				IoWrite(address, value, 32);
   731 		}
   732 	} else {
   733 		IoWrite(address, value, 32);
   734 	}
   735 }/*}}}*/
   737 /**
   738  * @brief Write M68K memory, 16-bit
   739  */
   740 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
   741 {
   742 	// If ROMLMAP is set, force system to access ROM
   743 	if (!state.romlmap)
   744 		address |= 0x800000;
   746 	// Check access permissions
   747 	ACCESS_CHECK_WR(address, 16);
   749 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   750 		// ROM access
   751 	} else if (address <= 0x3FFFFF) {
   752 		// RAM access
   753 		uint32_t newAddr = mapAddr(address, true);
   754 		if (newAddr <= 0x1fffff) {
   755 			WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
   756 		} else {
   757 //			WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   758 		}
   759 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   760 		// I/O register space, zone A
   761 		switch (address & 0x0F0000) {
   762 			case 0x000000:				// Map RAM access
   763 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   764 				WR16(state.map, address, 0x7FF, value);
   765 				break;
   766 			case 0x020000:				// Video RAM
   767 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   768 				WR16(state.vram, address, 0x7FFF, value);
   769 				break;
   770 			default:
   771 				IoWrite(address, value, 16);
   772 		}
   773 	} else {
   774 		IoWrite(address, value, 16);
   775 	}
   776 }/*}}}*/
   778 /**
   779  * @brief Write M68K memory, 8-bit
   780  */
   781 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
   782 {
   783 	// If ROMLMAP is set, force system to access ROM
   784 	if (!state.romlmap)
   785 		address |= 0x800000;
   787 	// Check access permissions
   788 	ACCESS_CHECK_WR(address, 8);
   790 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   791 		// ROM access (read only!)
   792 	} else if (address <= 0x3FFFFF) {
   793 		// RAM access
   794 		uint32_t newAddr = mapAddr(address, true);
   795 		if (newAddr <= 0x1fffff) {
   796 			WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
   797 		} else {
   798 //			WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   799 		}
   800 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   801 		// I/O register space, zone A
   802 		switch (address & 0x0F0000) {
   803 			case 0x000000:				// Map RAM access
   804 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   805 				WR8(state.map, address, 0x7FF, value);
   806 				break;
   807 			case 0x020000:				// Video RAM
   808 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   809 				WR8(state.vram, address, 0x7FFF, value);
   810 				break;
   811 			default:
   812 				IoWrite(address, value, 8);
   813 		}
   814 	} else {
   815 		IoWrite(address, value, 8);
   816 	}
   817 }/*}}}*/
   820 // for the disassembler
   821 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
   822 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
   823 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }