Tue, 28 Dec 2010 19:23:57 +0000
tidy up WR_nn macros
1 #include <stdio.h>
2 #include <stdlib.h>
3 #include <stdint.h>
4 #include <stdbool.h>
5 #include <assert.h>
6 #include "musashi/m68k.h"
7 #include "state.h"
8 #include "memory.h"
10 /******************
11 * Memory mapping
12 ******************/
14 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
16 uint32_t mapAddr(uint32_t addr, bool writing)/*{{{*/
17 {
18 if (addr < 0x400000) {
19 // RAM access. Check against the Map RAM
20 // Start by getting the original page address
21 uint16_t page = (addr >> 12) & 0x3FF;
23 // Look it up in the map RAM and get the physical page address
24 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
26 // Update the Page Status bits
27 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
28 if (pagebits != 0) {
29 if (writing)
30 state.map[page*2] |= 0x60; // Page written to (dirty)
31 else
32 state.map[page*2] |= 0x40; // Page accessed but not written
33 }
35 // Return the address with the new physical page spliced in
36 return (new_page_addr << 12) + (addr & 0xFFF);
37 } else {
38 // I/O, VRAM or MapRAM space; no mapping is performed or required
39 // TODO: assert here?
40 return addr;
41 }
42 }/*}}}*/
44 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)/*{{{*/
45 {
46 // Are we in Supervisor mode?
47 if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
48 // Yes. We can do anything we like.
49 return MEM_ALLOWED;
51 // If we're here, then we must be in User mode.
52 // Check that the user didn't access memory outside of the RAM area
53 if (addr >= 0x400000)
54 return MEM_UIE;
56 // This leaves us with Page Fault checking. Get the page bits for this page.
57 uint16_t page = (addr >> 12) & 0x3FF;
58 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
60 // Check page is present
61 if ((pagebits & 0x03) == 0)
62 return MEM_PAGEFAULT;
64 // User attempt to access the kernel
65 // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
66 if (((addr >> 19) & 0x0F) == 0)
67 return MEM_KERNEL;
69 // Check page is write enabled
70 if (writing && ((pagebits & 0x04) == 0))
71 return MEM_PAGE_NO_WE;
73 // Page access allowed.
74 return MEM_ALLOWED;
75 }/*}}}*/
77 #undef MAPRAM
80 /********************************************************
81 * m68k memory read/write support functions for Musashi
82 ********************************************************/
84 /**
85 * @brief Check memory access permissions for a write operation.
86 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
87 * gcc throws warnings when you have a return-with-value in a void
88 * function, even if the return-with-value is completely unreachable.
89 * Similarly it doesn't like it if you have a return without a value
90 * in a non-void function, even if it's impossible to ever reach the
91 * return-with-no-value. UGH!
92 */
93 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
94 #define ACCESS_CHECK_WR(address, bits) \
95 do { \
96 bool fault = false; \
97 /* MEM_STATUS st; */ \
98 switch (checkMemoryAccess(address, true)) { \
99 case MEM_ALLOWED: \
100 /* Access allowed */ \
101 break; \
102 case MEM_PAGEFAULT: \
103 /* Page fault */ \
104 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0); \
105 fault = true; \
106 break; \
107 case MEM_UIE: \
108 /* User access to memory above 4MB */ \
109 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0); \
110 fault = true; \
111 break; \
112 case MEM_KERNEL: \
113 case MEM_PAGE_NO_WE: \
114 /* kernel access or page not write enabled */ \
115 /* FIXME: which regs need setting? */ \
116 fault = true; \
117 break; \
118 } \
119 \
120 if (fault) { \
121 if (bits >= 16) \
122 state.bsr0 = 0x7C00; \
123 else \
124 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
125 state.bsr0 |= (address >> 16); \
126 state.bsr1 = address & 0xffff; \
127 printf("ERR: BusError WR\n"); \
128 m68k_pulse_bus_error(); \
129 return; \
130 } \
131 } while (0)
132 /*}}}*/
134 /**
135 * @brief Check memory access permissions for a read operation.
136 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
137 * gcc throws warnings when you have a return-with-value in a void
138 * function, even if the return-with-value is completely unreachable.
139 * Similarly it doesn't like it if you have a return without a value
140 * in a non-void function, even if it's impossible to ever reach the
141 * return-with-no-value. UGH!
142 */
143 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
144 #define ACCESS_CHECK_RD(address, bits) \
145 do { \
146 bool fault = false; \
147 /* MEM_STATUS st; */ \
148 switch (checkMemoryAccess(address, false)) { \
149 case MEM_ALLOWED: \
150 /* Access allowed */ \
151 break; \
152 case MEM_PAGEFAULT: \
153 /* Page fault */ \
154 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0); \
155 fault = true; \
156 break; \
157 case MEM_UIE: \
158 /* User access to memory above 4MB */ \
159 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0); \
160 fault = true; \
161 break; \
162 case MEM_KERNEL: \
163 case MEM_PAGE_NO_WE: \
164 /* kernel access or page not write enabled */ \
165 /* FIXME: which regs need setting? */ \
166 fault = true; \
167 break; \
168 } \
169 \
170 if (fault) { \
171 if (bits >= 16) \
172 state.bsr0 = 0x7C00; \
173 else \
174 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
175 state.bsr0 |= (address >> 16); \
176 state.bsr1 = address & 0xffff; \
177 printf("ERR: BusError RD\n"); \
178 m68k_pulse_bus_error(); \
179 return 0xFFFFFFFF; \
180 } \
181 } while (0)
182 /*}}}*/
184 // Logging macros
185 #define LOG_NOT_HANDLED_R(bits) \
186 if (!handled) printf("unhandled read%02d, addr=0x%08X\n", bits, address);
188 #define LOG_NOT_HANDLED_W(bits) \
189 if (!handled) printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
191 /********************************************************
192 * I/O read/write functions
193 ********************************************************/
195 /**
196 * Issue a warning if a read operation is made with an invalid size
197 */
198 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
199 {
200 assert((bits == 8) || (bits == 16) || (bits == 32));
201 if ((bits & allowed) == 0) {
202 printf("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
203 }
204 }
206 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
207 {
208 ENFORCE_SIZE(bits, address, true, allowed, regname);
209 }
211 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
212 {
213 ENFORCE_SIZE(bits, address, false, allowed, regname);
214 }
216 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
217 {
218 bool handled = false;
220 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
221 // I/O register space, zone A
222 switch (address & 0x0F0000) {
223 case 0x010000: // General Status Register
224 if (bits == 16)
225 state.genstat = (data & 0xffff);
226 else if (bits == 8) {
227 if (address & 0)
228 state.genstat = data;
229 else
230 state.genstat = data << 8;
231 }
232 handled = true;
233 break;
234 case 0x030000: // Bus Status Register 0
235 break;
236 case 0x040000: // Bus Status Register 1
237 break;
238 case 0x050000: // Phone status
239 break;
240 case 0x060000: // DMA Count
241 ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
242 state.dma_count = (data & 0x3FFF);
243 state.idmarw = ((data & 0x4000) == 0x4000);
244 state.dmaen = ((data & 0x8000) == 0x8000);
245 // This handles the "dummy DMA transfer" mentioned in the docs
246 // TODO: access check, peripheral access
247 if (!state.idmarw)
248 WR32(state.base_ram, mapAddr(address, true), state.base_ram_size - 1, 0xDEAD);
249 state.dma_count++;
250 handled = true;
251 break;
252 case 0x070000: // Line Printer Status Register
253 break;
254 case 0x080000: // Real Time Clock
255 break;
256 case 0x090000: // Phone registers
257 switch (address & 0x0FF000) {
258 case 0x090000: // Handset relay
259 case 0x098000:
260 break;
261 case 0x091000: // Line select 2
262 case 0x099000:
263 break;
264 case 0x092000: // Hook relay 1
265 case 0x09A000:
266 break;
267 case 0x093000: // Hook relay 2
268 case 0x09B000:
269 break;
270 case 0x094000: // Line 1 hold
271 case 0x09C000:
272 break;
273 case 0x095000: // Line 2 hold
274 case 0x09D000:
275 break;
276 case 0x096000: // Line 1 A-lead
277 case 0x09E000:
278 break;
279 case 0x097000: // Line 2 A-lead
280 case 0x09F000:
281 break;
282 }
283 break;
284 case 0x0A0000: // Miscellaneous Control Register
285 ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
286 // TODO: handle the ctrl bits properly
287 // TODO: &0x8000 --> dismiss 60hz intr
288 state.dma_reading = (data & 0x4000);
289 state.leds = (~data & 0xF00) >> 8;
290 printf("LEDs: %s %s %s %s\n",
291 (state.leds & 8) ? "R" : "-",
292 (state.leds & 4) ? "G" : "-",
293 (state.leds & 2) ? "Y" : "-",
294 (state.leds & 1) ? "R" : "-");
295 handled = true;
296 break;
297 case 0x0B0000: // TM/DIALWR
298 break;
299 case 0x0C0000: // Clear Status Register
300 state.genstat = 0xFFFF;
301 state.bsr0 = 0xFFFF;
302 state.bsr1 = 0xFFFF;
303 handled = true;
304 break;
305 case 0x0D0000: // DMA Address Register
306 if (address & 0x004000) {
307 // A14 high -- set most significant bits
308 state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
309 } else {
310 // A14 low -- set least significant bits
311 state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
312 }
313 handled = true;
314 break;
315 case 0x0E0000: // Disk Control Register
316 ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
317 // B7 = FDD controller reset
318 if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
319 // B6 = drive 0 select -- TODO
320 // B5 = motor enable -- TODO
321 // B4 = HDD controller reset -- TODO
322 // B3 = HDD0 select -- TODO
323 // B2,1,0 = HDD0 head select
324 handled = true;
325 break;
326 case 0x0F0000: // Line Printer Data Register
327 break;
328 }
329 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
330 // I/O register space, zone B
331 switch (address & 0xF00000) {
332 case 0xC00000: // Expansion slots
333 case 0xD00000:
334 switch (address & 0xFC0000) {
335 case 0xC00000: // Expansion slot 0
336 case 0xC40000: // Expansion slot 1
337 case 0xC80000: // Expansion slot 2
338 case 0xCC0000: // Expansion slot 3
339 case 0xD00000: // Expansion slot 4
340 case 0xD40000: // Expansion slot 5
341 case 0xD80000: // Expansion slot 6
342 case 0xDC0000: // Expansion slot 7
343 fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
344 handled = true;
345 break;
346 }
347 break;
348 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
349 case 0xF00000:
350 switch (address & 0x070000) {
351 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
352 break;
353 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
354 ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");
355 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
356 handled = true;
357 break;
358 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
359 break;
360 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
361 break;
362 case 0x040000: // [ef][4c]xxxx ==> General Control Register
363 switch (address & 0x077000) {
364 case 0x040000: // [ef][4c][08]xxx ==> EE
365 break;
366 case 0x041000: // [ef][4c][19]xxx ==> PIE
367 ENFORCE_SIZE_W(bits, address, 16, "PIE");
368 state.pie = ((data & 0x8000) == 0x8000);
369 handled = true;
370 break;
371 case 0x042000: // [ef][4c][2A]xxx ==> BP
372 break;
373 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
374 ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
375 state.romlmap = ((data & 0x8000) == 0x8000);
376 handled = true;
377 break;
378 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
379 ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
380 break;
381 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
382 ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
383 break;
384 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
385 ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
386 break;
387 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
388 ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
389 break;
390 }
391 case 0x050000: // [ef][5d]xxxx ==> 8274
392 break;
393 case 0x060000: // [ef][6e]xxxx ==> Control regs
394 switch (address & 0x07F000) {
395 default:
396 break;
397 }
398 break;
399 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
400 break;
401 }
402 }
403 }
405 LOG_NOT_HANDLED_W(bits);
406 }/*}}}*/
408 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
409 {
410 bool handled = false;
411 uint32_t data = 0xFFFFFFFF;
413 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
414 // I/O register space, zone A
415 switch (address & 0x0F0000) {
416 case 0x010000: // General Status Register
417 ENFORCE_SIZE_R(bits, address, 16, "GENSTAT");
418 return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
419 break;
420 case 0x030000: // Bus Status Register 0
421 ENFORCE_SIZE_R(bits, address, 16, "BSR0");
422 return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
423 break;
424 case 0x040000: // Bus Status Register 1
425 ENFORCE_SIZE_R(bits, address, 16, "BSR1");
426 return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
427 break;
428 case 0x050000: // Phone status
429 ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
430 break;
431 case 0x060000: // DMA Count
432 // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
433 // Bit 14 is always unused, so leave it set
434 ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
435 return (state.dma_count & 0x3fff) | 0xC000;
436 break;
437 case 0x070000: // Line Printer Status Register
438 data = 0x00120012; // no parity error, no line printer error, no irqs from FDD or HDD
439 data |= (state.fdc_ctx.irql) ? 0x00080008 : 0; // FIXME! HACKHACKHACK! shouldn't peek inside FDC structs like this
440 return data;
441 break;
442 case 0x080000: // Real Time Clock
443 printf("READ NOTIMP: Realtime Clock\n");
444 break;
445 case 0x090000: // Phone registers
446 switch (address & 0x0FF000) {
447 case 0x090000: // Handset relay
448 case 0x098000:
449 break;
450 case 0x091000: // Line select 2
451 case 0x099000:
452 break;
453 case 0x092000: // Hook relay 1
454 case 0x09A000:
455 break;
456 case 0x093000: // Hook relay 2
457 case 0x09B000:
458 break;
459 case 0x094000: // Line 1 hold
460 case 0x09C000:
461 break;
462 case 0x095000: // Line 2 hold
463 case 0x09D000:
464 break;
465 case 0x096000: // Line 1 A-lead
466 case 0x09E000:
467 break;
468 case 0x097000: // Line 2 A-lead
469 case 0x09F000:
470 break;
471 }
472 break;
473 case 0x0A0000: // Miscellaneous Control Register -- write only!
474 handled = true;
475 break;
476 case 0x0B0000: // TM/DIALWR
477 break;
478 case 0x0C0000: // Clear Status Register -- write only!
479 handled = true;
480 break;
481 case 0x0D0000: // DMA Address Register
482 break;
483 case 0x0E0000: // Disk Control Register
484 break;
485 case 0x0F0000: // Line Printer Data Register
486 break;
487 }
488 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
489 // I/O register space, zone B
490 switch (address & 0xF00000) {
491 case 0xC00000: // Expansion slots
492 case 0xD00000:
493 switch (address & 0xFC0000) {
494 case 0xC00000: // Expansion slot 0
495 case 0xC40000: // Expansion slot 1
496 case 0xC80000: // Expansion slot 2
497 case 0xCC0000: // Expansion slot 3
498 case 0xD00000: // Expansion slot 4
499 case 0xD40000: // Expansion slot 5
500 case 0xD80000: // Expansion slot 6
501 case 0xDC0000: // Expansion slot 7
502 fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
503 handled = true;
504 break;
505 }
506 break;
507 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
508 case 0xF00000:
509 switch (address & 0x070000) {
510 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
511 break;
512 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
513 ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");
514 return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
515 break;
516 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
517 break;
518 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
519 break;
520 case 0x040000: // [ef][4c]xxxx ==> General Control Register
521 switch (address & 0x077000) {
522 case 0x040000: // [ef][4c][08]xxx ==> EE
523 case 0x041000: // [ef][4c][19]xxx ==> PIE
524 case 0x042000: // [ef][4c][2A]xxx ==> BP
525 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
526 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
527 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
528 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
529 // All write-only registers... TODO: bus error?
530 handled = true;
531 break;
532 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
533 break;
534 }
535 break;
536 case 0x050000: // [ef][5d]xxxx ==> 8274
537 break;
538 case 0x060000: // [ef][6e]xxxx ==> Control regs
539 switch (address & 0x07F000) {
540 default:
541 break;
542 }
543 break;
544 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
545 break;
546 }
547 }
548 }
550 LOG_NOT_HANDLED_R(bits);
552 return data;
553 }/*}}}*/
556 /********************************************************
557 * m68k memory read/write support functions for Musashi
558 ********************************************************/
560 /**
561 * @brief Read M68K memory, 32-bit
562 */
563 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
564 {
565 uint32_t data = 0xFFFFFFFF;
567 // If ROMLMAP is set, force system to access ROM
568 if (!state.romlmap)
569 address |= 0x800000;
571 // Check access permissions
572 ACCESS_CHECK_RD(address, 32);
574 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
575 // ROM access
576 return RD32(state.rom, address, ROM_SIZE - 1);
577 } else if (address <= 0x3fffff) {
578 // RAM access
579 uint32_t newAddr = mapAddr(address, false);
580 if (newAddr <= 0x1fffff) {
581 return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
582 } else {
583 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
584 return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
585 else
586 return 0xffffffff;
587 }
588 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
589 // I/O register space, zone A
590 switch (address & 0x0F0000) {
591 case 0x000000: // Map RAM access
592 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
593 return RD32(state.map, address, 0x7FF);
594 break;
595 case 0x020000: // Video RAM
596 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
597 return RD32(state.vram, address, 0x7FFF);
598 break;
599 default:
600 return IoRead(address, 32);
601 }
602 } else {
603 return IoRead(address, 32);
604 }
606 return data;
607 }/*}}}*/
609 /**
610 * @brief Read M68K memory, 16-bit
611 */
612 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
613 {
614 uint16_t data = 0xFFFF;
616 // If ROMLMAP is set, force system to access ROM
617 if (!state.romlmap)
618 address |= 0x800000;
620 // Check access permissions
621 ACCESS_CHECK_RD(address, 16);
623 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
624 // ROM access
625 data = RD16(state.rom, address, ROM_SIZE - 1);
626 } else if (address <= 0x3fffff) {
627 // RAM access
628 uint32_t newAddr = mapAddr(address, false);
629 if (newAddr <= 0x1fffff) {
630 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
631 } else {
632 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
633 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
634 else
635 return 0xffff;
636 }
637 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
638 // I/O register space, zone A
639 switch (address & 0x0F0000) {
640 case 0x000000: // Map RAM access
641 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
642 data = RD16(state.map, address, 0x7FF);
643 break;
644 case 0x020000: // Video RAM
645 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
646 data = RD16(state.vram, address, 0x7FFF);
647 break;
648 default:
649 data = IoRead(address, 16);
650 }
651 } else {
652 data = IoRead(address, 16);
653 }
655 return data;
656 }/*}}}*/
658 /**
659 * @brief Read M68K memory, 8-bit
660 */
661 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
662 {
663 uint8_t data = 0xFF;
665 // If ROMLMAP is set, force system to access ROM
666 if (!state.romlmap)
667 address |= 0x800000;
669 // Check access permissions
670 ACCESS_CHECK_RD(address, 8);
672 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
673 // ROM access
674 data = RD8(state.rom, address, ROM_SIZE - 1);
675 } else if (address <= 0x3fffff) {
676 // RAM access
677 uint32_t newAddr = mapAddr(address, false);
678 if (newAddr <= 0x1fffff) {
679 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
680 } else {
681 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
682 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
683 else
684 return 0xff;
685 }
686 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
687 // I/O register space, zone A
688 switch (address & 0x0F0000) {
689 case 0x000000: // Map RAM access
690 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
691 data = RD8(state.map, address, 0x7FF);
692 break;
693 case 0x020000: // Video RAM
694 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
695 data = RD8(state.vram, address, 0x7FFF);
696 break;
697 default:
698 data = IoRead(address, 8);
699 }
700 } else {
701 data = IoRead(address, 8);
702 }
704 return data;
705 }/*}}}*/
707 /**
708 * @brief Write M68K memory, 32-bit
709 */
710 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
711 {
712 // If ROMLMAP is set, force system to access ROM
713 if (!state.romlmap)
714 address |= 0x800000;
716 // Check access permissions
717 ACCESS_CHECK_WR(address, 32);
719 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
720 // ROM access
721 } else if (address <= 0x3FFFFF) {
722 // RAM access
723 uint32_t newAddr = mapAddr(address, true);
724 if (newAddr <= 0x1fffff)
725 WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
726 else
727 WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
728 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
729 // I/O register space, zone A
730 switch (address & 0x0F0000) {
731 case 0x000000: // Map RAM access
732 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
733 WR32(state.map, address, 0x7FF, value);
734 break;
735 case 0x020000: // Video RAM
736 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
737 WR32(state.vram, address, 0x7FFF, value);
738 break;
739 default:
740 IoWrite(address, value, 32);
741 }
742 } else {
743 IoWrite(address, value, 32);
744 }
745 }/*}}}*/
747 /**
748 * @brief Write M68K memory, 16-bit
749 */
750 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
751 {
752 // If ROMLMAP is set, force system to access ROM
753 if (!state.romlmap)
754 address |= 0x800000;
756 // Check access permissions
757 ACCESS_CHECK_WR(address, 16);
759 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
760 // ROM access
761 } else if (address <= 0x3FFFFF) {
762 // RAM access
763 uint32_t newAddr = mapAddr(address, true);
764 if (newAddr <= 0x1fffff)
765 WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
766 else
767 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
768 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
769 // I/O register space, zone A
770 switch (address & 0x0F0000) {
771 case 0x000000: // Map RAM access
772 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
773 WR16(state.map, address, 0x7FF, value);
774 break;
775 case 0x020000: // Video RAM
776 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
777 WR16(state.vram, address, 0x7FFF, value);
778 break;
779 default:
780 IoWrite(address, value, 16);
781 }
782 } else {
783 IoWrite(address, value, 16);
784 }
785 }/*}}}*/
787 /**
788 * @brief Write M68K memory, 8-bit
789 */
790 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
791 {
792 // If ROMLMAP is set, force system to access ROM
793 if (!state.romlmap)
794 address |= 0x800000;
796 // Check access permissions
797 ACCESS_CHECK_WR(address, 8);
799 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
800 // ROM access (read only!)
801 } else if (address <= 0x3FFFFF) {
802 // RAM access
803 uint32_t newAddr = mapAddr(address, true);
804 if (newAddr <= 0x1fffff)
805 WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
806 else
807 WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
808 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
809 // I/O register space, zone A
810 switch (address & 0x0F0000) {
811 case 0x000000: // Map RAM access
812 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
813 WR8(state.map, address, 0x7FF, value);
814 break;
815 case 0x020000: // Video RAM
816 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
817 WR8(state.vram, address, 0x7FFF, value);
818 break;
819 default:
820 IoWrite(address, value, 8);
821 }
822 } else {
823 IoWrite(address, value, 8);
824 }
825 }/*}}}*/
828 // for the disassembler
829 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
830 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
831 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }