Fri, 03 Dec 2010 01:43:57 +0000
add comments for some write-only regs, fix LOG_NOT_HANDLED_R(32) in read16, basic LED reg decoding
1 #include <stdio.h>
2 #include <stdlib.h>
3 #include <stdint.h>
4 #include <stdbool.h>
5 #include "musashi/m68k.h"
6 #include "state.h"
7 #include "memory.h"
9 /******************
10 * Memory mapping
11 ******************/
13 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
15 uint32_t mapAddr(uint32_t addr, bool writing)
16 {
17 if (addr < 0x400000) {
18 // RAM access. Check against the Map RAM
19 // Start by getting the original page address
20 uint16_t page = (addr >> 12) & 0x3FF;
22 // Look it up in the map RAM and get the physical page address
23 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
25 // Update the Page Status bits
26 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
27 if (pagebits != 0) {
28 if (writing)
29 state.map[page*2] |= 0x60; // Page written to (dirty)
30 else
31 state.map[page*2] |= 0x40; // Page accessed but not written
32 }
34 // Return the address with the new physical page spliced in
35 return (new_page_addr << 12) + (addr & 0xFFF);
36 } else {
37 // I/O, VRAM or MapRAM space; no mapping is performed or required
38 // TODO: assert here?
39 return addr;
40 }
41 }
43 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)
44 {
45 // Are we in Supervisor mode?
46 if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
47 // Yes. We can do anything we like.
48 return MEM_ALLOWED;
50 // If we're here, then we must be in User mode.
51 // Check that the user didn't access memory outside of the RAM area
52 if (addr >= 0x400000)
53 return MEM_UIE;
55 // This leaves us with Page Fault checking. Get the page bits for this page.
56 uint16_t page = (addr >> 12) & 0x3FF;
57 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
59 // Check page is present
60 if ((pagebits & 0x03) == 0)
61 return MEM_PAGEFAULT;
63 // User attempt to access the kernel
64 // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
65 if (((addr >> 19) & 0x0F) == 0)
66 return MEM_KERNEL;
68 // Check page is write enabled
69 if ((pagebits & 0x04) == 0)
70 return MEM_PAGE_NO_WE;
72 // Page access allowed.
73 return MEM_ALLOWED;
74 }
76 #undef MAPRAM
79 /********************************************************
80 * m68k memory read/write support functions for Musashi
81 ********************************************************/
83 /**
84 * @brief Check memory access permissions for a write operation.
85 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
86 * gcc throws warnings when you have a return-with-value in a void
87 * function, even if the return-with-value is completely unreachable.
88 * Similarly it doesn't like it if you have a return without a value
89 * in a non-void function, even if it's impossible to ever reach the
90 * return-with-no-value. UGH!
91 */
92 #define ACCESS_CHECK_WR(address, bits) do { \
93 bool fault = false; \
94 /* MEM_STATUS st; */ \
95 switch (checkMemoryAccess(address, true)) { \
96 case MEM_ALLOWED: \
97 /* Access allowed */ \
98 break; \
99 case MEM_PAGEFAULT: \
100 /* Page fault */ \
101 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0); \
102 fault = true; \
103 break; \
104 case MEM_UIE: \
105 /* User access to memory above 4MB */ \
106 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0); \
107 fault = true; \
108 break; \
109 case MEM_KERNEL: \
110 case MEM_PAGE_NO_WE: \
111 /* kernel access or page not write enabled */ \
112 /* TODO: which regs need setting? */ \
113 fault = true; \
114 break; \
115 } \
116 \
117 if (fault) { \
118 if (bits >= 16) \
119 state.bsr0 = 0x7F00; \
120 else \
121 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
122 state.bsr0 |= (address >> 16); \
123 state.bsr1 = address & 0xffff; \
124 printf("ERR: BusError WR\n"); \
125 m68k_pulse_bus_error(); \
126 return; \
127 } \
128 } while (false)
130 /**
131 * @brief Check memory access permissions for a read operation.
132 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
133 * gcc throws warnings when you have a return-with-value in a void
134 * function, even if the return-with-value is completely unreachable.
135 * Similarly it doesn't like it if you have a return without a value
136 * in a non-void function, even if it's impossible to ever reach the
137 * return-with-no-value. UGH!
138 */
139 #define ACCESS_CHECK_RD(address, bits) do { \
140 bool fault = false; \
141 /* MEM_STATUS st; */ \
142 switch (checkMemoryAccess(address, false)) { \
143 case MEM_ALLOWED: \
144 /* Access allowed */ \
145 break; \
146 case MEM_PAGEFAULT: \
147 /* Page fault */ \
148 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0); \
149 fault = true; \
150 break; \
151 case MEM_UIE: \
152 /* User access to memory above 4MB */ \
153 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0); \
154 fault = true; \
155 break; \
156 case MEM_KERNEL: \
157 case MEM_PAGE_NO_WE: \
158 /* kernel access or page not write enabled */ \
159 /* TODO: which regs need setting? */ \
160 fault = true; \
161 break; \
162 } \
163 \
164 if (fault) { \
165 if (bits >= 16) \
166 state.bsr0 = 0x7F00; \
167 else \
168 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
169 state.bsr0 |= (address >> 16); \
170 state.bsr1 = address & 0xffff; \
171 printf("ERR: BusError RD\n"); \
172 m68k_pulse_bus_error(); \
173 return 0xFFFFFFFF; \
174 } \
175 } while (false)
177 // Logging macros
178 #define LOG_NOT_HANDLED_R(bits) \
179 do { \
180 if (!handled) \
181 printf("unhandled read%02d, addr=0x%08X\n", bits, address); \
182 } while (0);
184 #define LOG_NOT_HANDLED_W(bits) \
185 do { \
186 if (!handled) \
187 printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, value); \
188 } while (0);
190 /**
191 * @brief Read M68K memory, 32-bit
192 */
193 uint32_t m68k_read_memory_32(uint32_t address)
194 {
195 uint32_t data = 0xFFFFFFFF;
196 bool handled = false;
198 // If ROMLMAP is set, force system to access ROM
199 if (!state.romlmap)
200 address |= 0x800000;
202 // Check access permissions
203 ACCESS_CHECK_RD(address, 32);
205 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
206 // ROM access
207 data = RD32(state.rom, address, ROM_SIZE - 1);
208 handled = true;
209 } else if (address <= (state.ram_size - 1)) {
210 // RAM access
211 data = RD32(state.ram, mapAddr(address, false), state.ram_size - 1);
212 handled = true;
213 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
214 // I/O register space, zone A
215 switch (address & 0x0F0000) {
216 case 0x000000: // Map RAM access
217 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
218 data = RD32(state.map, address, 0x7FF);
219 handled = true;
220 break;
221 case 0x010000: // General Status Register
222 data = ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
223 handled = true;
224 break;
225 case 0x020000: // Video RAM
226 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
227 data = RD32(state.vram, address, 0x7FFF);
228 handled = true;
229 break;
230 case 0x030000: // Bus Status Register 0
231 data = ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
232 handled = true;
233 break;
234 case 0x040000: // Bus Status Register 1
235 data = ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
236 handled = true;
237 break;
238 case 0x050000: // Phone status
239 break;
240 case 0x060000: // DMA Count
241 break;
242 case 0x070000: // Line Printer Status Register
243 break;
244 case 0x080000: // Real Time Clock
245 break;
246 case 0x090000: // Phone registers
247 switch (address & 0x0FF000) {
248 case 0x090000: // Handset relay
249 case 0x098000:
250 break;
251 case 0x091000: // Line select 2
252 case 0x099000:
253 break;
254 case 0x092000: // Hook relay 1
255 case 0x09A000:
256 break;
257 case 0x093000: // Hook relay 2
258 case 0x09B000:
259 break;
260 case 0x094000: // Line 1 hold
261 case 0x09C000:
262 break;
263 case 0x095000: // Line 2 hold
264 case 0x09D000:
265 break;
266 case 0x096000: // Line 1 A-lead
267 case 0x09E000:
268 break;
269 case 0x097000: // Line 2 A-lead
270 case 0x09F000:
271 break;
272 }
273 break;
274 case 0x0A0000: // Miscellaneous Control Register -- write only!
275 handled = true;
276 break;
277 case 0x0B0000: // TM/DIALWR
278 break;
279 case 0x0C0000: // Clear Status Register -- write only!
280 handled = true;
281 break;
282 case 0x0D0000: // DMA Address Register
283 break;
284 case 0x0E0000: // Disk Control Register
285 break;
286 case 0x0F0000: // Line Printer Data Register
287 break;
288 }
289 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
290 // I/O register space, zone B
291 switch (address & 0xF00000) {
292 case 0xC00000: // Expansion slots
293 case 0xD00000:
294 switch (address & 0xFC0000) {
295 case 0xC00000: // Expansion slot 0
296 case 0xC40000: // Expansion slot 1
297 case 0xC80000: // Expansion slot 2
298 case 0xCC0000: // Expansion slot 3
299 case 0xD00000: // Expansion slot 4
300 case 0xD40000: // Expansion slot 5
301 case 0xD80000: // Expansion slot 6
302 case 0xDC0000: // Expansion slot 7
303 fprintf(stderr, "NOTE: RD32 from expansion card space, addr=0x%08X\n", address);
304 break;
305 }
306 break;
307 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
308 case 0xF00000:
309 switch (address & 0x070000) {
310 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
311 break;
312 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
313 break;
314 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
315 break;
316 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
317 break;
318 case 0x040000: // [ef][4c]xxxx ==> General Control Register
319 switch (address & 0x077000) {
320 case 0x040000: // [ef][4c][08]xxx ==> EE
321 case 0x041000: // [ef][4c][19]xxx ==> PIE
322 case 0x042000: // [ef][4c][2A]xxx ==> BP
323 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
324 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
325 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
326 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
327 // All write-only registers... TODO: bus error?
328 handled = true;
329 break;
330 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
331 break;
332 }
333 break;
334 case 0x050000: // [ef][5d]xxxx ==> 8274
335 break;
336 case 0x060000: // [ef][6e]xxxx ==> Control regs
337 switch (address & 0x07F000) {
338 default:
339 break;
340 }
341 break;
342 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
343 break;
344 }
345 }
346 }
348 LOG_NOT_HANDLED_R(32);
349 return data;
350 }
352 /**
353 * @brief Read M68K memory, 16-bit
354 */
355 uint32_t m68k_read_memory_16(uint32_t address)
356 {
357 uint16_t data = 0xFFFF;
358 bool handled = false;
360 // If ROMLMAP is set, force system to access ROM
361 if (!state.romlmap)
362 address |= 0x800000;
364 // Check access permissions
365 ACCESS_CHECK_RD(address, 16);
367 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
368 // ROM access
369 data = RD16(state.rom, address, ROM_SIZE - 1);
370 handled = true;
371 } else if (address <= (state.ram_size - 1)) {
372 // RAM access
373 data = RD16(state.ram, mapAddr(address, false), state.ram_size - 1);
374 handled = true;
375 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
376 // I/O register space, zone A
377 switch (address & 0x0F0000) {
378 case 0x000000: // Map RAM access
379 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
380 data = RD16(state.map, address, 0x7FF);
381 handled = true;
382 break;
383 case 0x010000: // General Status Register
384 data = state.genstat;
385 handled = true;
386 break;
387 case 0x020000: // Video RAM
388 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
389 data = RD16(state.vram, address, 0x7FFF);
390 handled = true;
391 break;
392 case 0x030000: // Bus Status Register 0
393 data = state.bsr0;
394 handled = true;
395 break;
396 case 0x040000: // Bus Status Register 1
397 data = state.bsr1;
398 handled = true;
399 break;
400 case 0x050000: // Phone status
401 break;
402 case 0x060000: // DMA Count
403 break;
404 case 0x070000: // Line Printer Status Register
405 break;
406 case 0x080000: // Real Time Clock
407 break;
408 case 0x090000: // Phone registers
409 switch (address & 0x0FF000) {
410 case 0x090000: // Handset relay
411 case 0x098000:
412 break;
413 case 0x091000: // Line select 2
414 case 0x099000:
415 break;
416 case 0x092000: // Hook relay 1
417 case 0x09A000:
418 break;
419 case 0x093000: // Hook relay 2
420 case 0x09B000:
421 break;
422 case 0x094000: // Line 1 hold
423 case 0x09C000:
424 break;
425 case 0x095000: // Line 2 hold
426 case 0x09D000:
427 break;
428 case 0x096000: // Line 1 A-lead
429 case 0x09E000:
430 break;
431 case 0x097000: // Line 2 A-lead
432 case 0x09F000:
433 break;
434 }
435 break;
436 case 0x0A0000: // Miscellaneous Control Register -- write only!
437 handled = true;
438 break;
439 case 0x0B0000: // TM/DIALWR
440 break;
441 case 0x0C0000: // Clear Status Register -- write only!
442 handled = true;
443 break;
444 case 0x0D0000: // DMA Address Register
445 break;
446 case 0x0E0000: // Disk Control Register
447 break;
448 case 0x0F0000: // Line Printer Data Register
449 break;
450 }
451 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
452 // I/O register space, zone B
453 switch (address & 0xF00000) {
454 case 0xC00000: // Expansion slots
455 case 0xD00000:
456 switch (address & 0xFC0000) {
457 case 0xC00000: // Expansion slot 0
458 case 0xC40000: // Expansion slot 1
459 case 0xC80000: // Expansion slot 2
460 case 0xCC0000: // Expansion slot 3
461 case 0xD00000: // Expansion slot 4
462 case 0xD40000: // Expansion slot 5
463 case 0xD80000: // Expansion slot 6
464 case 0xDC0000: // Expansion slot 7
465 fprintf(stderr, "NOTE: RD16 from expansion card space, addr=0x%08X\n", address);
466 break;
467 }
468 break;
469 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
470 case 0xF00000:
471 switch (address & 0x070000) {
472 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
473 break;
474 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
475 break;
476 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
477 break;
478 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
479 break;
480 case 0x040000: // [ef][4c]xxxx ==> General Control Register
481 switch (address & 0x077000) {
482 case 0x040000: // [ef][4c][08]xxx ==> EE
483 case 0x041000: // [ef][4c][19]xxx ==> PIE
484 case 0x042000: // [ef][4c][2A]xxx ==> BP
485 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
486 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
487 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
488 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
489 // All write-only registers... TODO: bus error?
490 handled = true;
491 break;
492 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
493 break;
494 }
495 break;
496 case 0x050000: // [ef][5d]xxxx ==> 8274
497 break;
498 case 0x060000: // [ef][6e]xxxx ==> Control regs
499 switch (address & 0x07F000) {
500 default:
501 break;
502 }
503 break;
504 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
505 break;
506 }
507 }
508 }
510 LOG_NOT_HANDLED_R(16);
511 return data;
512 }
514 /**
515 * @brief Read M68K memory, 8-bit
516 */
517 uint32_t m68k_read_memory_8(uint32_t address)
518 {
519 uint8_t data = 0xFF;
520 bool handled = false;
522 // If ROMLMAP is set, force system to access ROM
523 if (!state.romlmap)
524 address |= 0x800000;
526 // Check access permissions
527 ACCESS_CHECK_RD(address, 8);
529 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
530 // ROM access
531 data = RD8(state.rom, address, ROM_SIZE - 1);
532 handled = true;
533 } else if (address <= (state.ram_size - 1)) {
534 // RAM access
535 data = RD8(state.ram, mapAddr(address, false), state.ram_size - 1);
536 handled = true;
537 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
538 // I/O register space, zone A
539 switch (address & 0x0F0000) {
540 case 0x000000: // Map RAM access
541 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
542 data = RD8(state.map, address, 0x7FF);
543 handled = true;
544 break;
545 case 0x010000: // General Status Register
546 if ((address & 1) == 0)
547 data = (state.genstat >> 8) & 0xff;
548 else
549 data = (state.genstat) & 0xff;
550 handled = true;
551 break;
552 case 0x020000: // Video RAM
553 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
554 data = RD8(state.vram, address, 0x7FFF);
555 handled = true;
556 break;
557 case 0x030000: // Bus Status Register 0
558 if ((address & 1) == 0)
559 data = (state.bsr0 >> 8) & 0xff;
560 else
561 data = (state.bsr0) & 0xff;
562 handled = true;
563 break;
564 case 0x040000: // Bus Status Register 1
565 if ((address & 1) == 0)
566 data = (state.bsr1 >> 8) & 0xff;
567 else
568 data = (state.bsr1) & 0xff;
569 handled = true;
570 break;
571 case 0x050000: // Phone status
572 break;
573 case 0x060000: // DMA Count
574 break;
575 case 0x070000: // Line Printer Status Register
576 break;
577 case 0x080000: // Real Time Clock
578 break;
579 case 0x090000: // Phone registers
580 switch (address & 0x0FF000) {
581 case 0x090000: // Handset relay
582 case 0x098000:
583 break;
584 case 0x091000: // Line select 2
585 case 0x099000:
586 break;
587 case 0x092000: // Hook relay 1
588 case 0x09A000:
589 break;
590 case 0x093000: // Hook relay 2
591 case 0x09B000:
592 break;
593 case 0x094000: // Line 1 hold
594 case 0x09C000:
595 break;
596 case 0x095000: // Line 2 hold
597 case 0x09D000:
598 break;
599 case 0x096000: // Line 1 A-lead
600 case 0x09E000:
601 break;
602 case 0x097000: // Line 2 A-lead
603 case 0x09F000:
604 break;
605 }
606 break;
607 case 0x0A0000: // Miscellaneous Control Register -- write only!
608 handled = true;
609 break;
610 case 0x0B0000: // TM/DIALWR
611 break;
612 case 0x0C0000: // Clear Status Register -- write only!
613 handled = true;
614 break;
615 case 0x0D0000: // DMA Address Register
616 break;
617 case 0x0E0000: // Disk Control Register
618 break;
619 case 0x0F0000: // Line Printer Data Register
620 break;
621 }
622 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
623 // I/O register space, zone B
624 switch (address & 0xF00000) {
625 case 0xC00000: // Expansion slots
626 case 0xD00000:
627 switch (address & 0xFC0000) {
628 case 0xC00000: // Expansion slot 0
629 case 0xC40000: // Expansion slot 1
630 case 0xC80000: // Expansion slot 2
631 case 0xCC0000: // Expansion slot 3
632 case 0xD00000: // Expansion slot 4
633 case 0xD40000: // Expansion slot 5
634 case 0xD80000: // Expansion slot 6
635 case 0xDC0000: // Expansion slot 7
636 fprintf(stderr, "NOTE: RD8 from expansion card space, addr=0x%08X\n", address);
637 break;
638 }
639 break;
640 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
641 case 0xF00000:
642 switch (address & 0x070000) {
643 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
644 break;
645 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
646 break;
647 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
648 break;
649 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
650 break;
651 case 0x040000: // [ef][4c]xxxx ==> General Control Register
652 switch (address & 0x077000) {
653 case 0x040000: // [ef][4c][08]xxx ==> EE
654 case 0x041000: // [ef][4c][19]xxx ==> PIE
655 case 0x042000: // [ef][4c][2A]xxx ==> BP
656 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
657 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
658 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
659 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
660 // All write-only registers... TODO: bus error?
661 handled = true;
662 break;
663 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
664 break;
665 }
666 case 0x050000: // [ef][5d]xxxx ==> 8274
667 break;
668 case 0x060000: // [ef][6e]xxxx ==> Control regs
669 switch (address & 0x07F000) {
670 default:
671 break;
672 }
673 break;
674 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
675 break;
676 }
677 }
678 }
680 LOG_NOT_HANDLED_R(8);
682 return data;
683 }
685 /**
686 * @brief Write M68K memory, 32-bit
687 */
688 void m68k_write_memory_32(uint32_t address, uint32_t value)
689 {
690 bool handled = false;
692 // If ROMLMAP is set, force system to access ROM
693 if (!state.romlmap)
694 address |= 0x800000;
696 // Check access permissions
697 ACCESS_CHECK_WR(address, 32);
699 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
700 // ROM access
701 handled = true;
702 } else if (address <= (state.ram_size - 1)) {
703 // RAM access
704 WR32(state.ram, mapAddr(address, false), state.ram_size - 1, value);
705 handled = true;
706 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
707 // I/O register space, zone A
708 switch (address & 0x0F0000) {
709 case 0x000000: // Map RAM access
710 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
711 WR32(state.map, address, 0x7FF, value);
712 handled = true;
713 break;
714 case 0x010000: // General Status Register
715 state.genstat = (value & 0xffff);
716 handled = true;
717 break;
718 case 0x020000: // Video RAM
719 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
720 WR32(state.vram, address, 0x7FFF, value);
721 handled = true;
722 break;
723 case 0x030000: // Bus Status Register 0
724 break;
725 case 0x040000: // Bus Status Register 1
726 break;
727 case 0x050000: // Phone status
728 break;
729 case 0x060000: // DMA Count
730 break;
731 case 0x070000: // Line Printer Status Register
732 break;
733 case 0x080000: // Real Time Clock
734 break;
735 case 0x090000: // Phone registers
736 switch (address & 0x0FF000) {
737 case 0x090000: // Handset relay
738 case 0x098000:
739 break;
740 case 0x091000: // Line select 2
741 case 0x099000:
742 break;
743 case 0x092000: // Hook relay 1
744 case 0x09A000:
745 break;
746 case 0x093000: // Hook relay 2
747 case 0x09B000:
748 break;
749 case 0x094000: // Line 1 hold
750 case 0x09C000:
751 break;
752 case 0x095000: // Line 2 hold
753 case 0x09D000:
754 break;
755 case 0x096000: // Line 1 A-lead
756 case 0x09E000:
757 break;
758 case 0x097000: // Line 2 A-lead
759 case 0x09F000:
760 break;
761 }
762 break;
763 case 0x0A0000: // Miscellaneous Control Register
764 // TODO: handle the ctrl bits properly
765 state.leds = (~value & 0xF00) >> 8;
766 printf("LEDs: %s %s %s %s\n",
767 (state.leds & 8) ? "R" : "-",
768 (state.leds & 4) ? "G" : "-",
769 (state.leds & 2) ? "Y" : "-",
770 (state.leds & 1) ? "R" : "-");
771 handled = true;
772 break;
773 case 0x0B0000: // TM/DIALWR
774 break;
775 case 0x0C0000: // Clear Status Register
776 state.genstat = 0xFFFF;
777 state.bsr0 = 0xFFFF;
778 state.bsr1 = 0xFFFF;
779 handled = true;
780 break;
781 case 0x0D0000: // DMA Address Register
782 break;
783 case 0x0E0000: // Disk Control Register
784 break;
785 case 0x0F0000: // Line Printer Data Register
786 break;
787 }
788 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
789 // I/O register space, zone B
790 switch (address & 0xF00000) {
791 case 0xC00000: // Expansion slots
792 case 0xD00000:
793 switch (address & 0xFC0000) {
794 case 0xC00000: // Expansion slot 0
795 case 0xC40000: // Expansion slot 1
796 case 0xC80000: // Expansion slot 2
797 case 0xCC0000: // Expansion slot 3
798 case 0xD00000: // Expansion slot 4
799 case 0xD40000: // Expansion slot 5
800 case 0xD80000: // Expansion slot 6
801 case 0xDC0000: // Expansion slot 7
802 fprintf(stderr, "NOTE: WR32 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
803 handled = true;
804 break;
805 }
806 break;
807 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
808 case 0xF00000:
809 switch (address & 0x070000) {
810 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
811 break;
812 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
813 break;
814 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
815 break;
816 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
817 break;
818 case 0x040000: // [ef][4c]xxxx ==> General Control Register
819 switch (address & 0x077000) {
820 case 0x040000: // [ef][4c][08]xxx ==> EE
821 break;
822 case 0x041000: // [ef][4c][19]xxx ==> PIE
823 state.pie = ((value & 0x8000) == 0x8000);
824 handled = true;
825 break;
826 case 0x042000: // [ef][4c][2A]xxx ==> BP
827 break;
828 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
829 state.romlmap = ((value & 0x8000) == 0x8000);
830 handled = true;
831 break;
832 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
833 break;
834 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
835 break;
836 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
837 break;
838 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
839 break;
840 }
841 case 0x050000: // [ef][5d]xxxx ==> 8274
842 break;
843 case 0x060000: // [ef][6e]xxxx ==> Control regs
844 switch (address & 0x07F000) {
845 default:
846 break;
847 }
848 break;
849 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
850 break;
851 }
852 }
853 }
855 LOG_NOT_HANDLED_W(32);
856 }
858 /**
859 * @brief Write M68K memory, 16-bit
860 */
861 void m68k_write_memory_16(uint32_t address, uint32_t value)
862 {
863 bool handled = false;
865 // If ROMLMAP is set, force system to access ROM
866 if (!state.romlmap)
867 address |= 0x800000;
869 // Check access permissions
870 ACCESS_CHECK_WR(address, 16);
872 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
873 // ROM access
874 handled = true;
875 } else if (address <= (state.ram_size - 1)) {
876 // RAM access
877 WR16(state.ram, mapAddr(address, false), state.ram_size - 1, value);
878 handled = true;
879 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
880 // I/O register space, zone A
881 switch (address & 0x0F0000) {
882 case 0x000000: // Map RAM access
883 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
884 WR16(state.map, address, 0x7FF, value);
885 handled = true;
886 break;
887 case 0x010000: // General Status Register (read only)
888 handled = true;
889 break;
890 case 0x020000: // Video RAM
891 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
892 WR16(state.vram, address, 0x7FFF, value);
893 handled = true;
894 break;
895 case 0x030000: // Bus Status Register 0 (read only)
896 handled = true;
897 break;
898 case 0x040000: // Bus Status Register 1 (read only)
899 handled = true;
900 break;
901 case 0x050000: // Phone status
902 break;
903 case 0x060000: // DMA Count
904 break;
905 case 0x070000: // Line Printer Status Register
906 break;
907 case 0x080000: // Real Time Clock
908 break;
909 case 0x090000: // Phone registers
910 switch (address & 0x0FF000) {
911 case 0x090000: // Handset relay
912 case 0x098000:
913 break;
914 case 0x091000: // Line select 2
915 case 0x099000:
916 break;
917 case 0x092000: // Hook relay 1
918 case 0x09A000:
919 break;
920 case 0x093000: // Hook relay 2
921 case 0x09B000:
922 break;
923 case 0x094000: // Line 1 hold
924 case 0x09C000:
925 break;
926 case 0x095000: // Line 2 hold
927 case 0x09D000:
928 break;
929 case 0x096000: // Line 1 A-lead
930 case 0x09E000:
931 break;
932 case 0x097000: // Line 2 A-lead
933 case 0x09F000:
934 break;
935 }
936 break;
937 case 0x0A0000: // Miscellaneous Control Register
938 // TODO: handle the ctrl bits properly
939 state.leds = (~value & 0xF00) >> 8;
940 printf("LEDs: %s %s %s %s\n",
941 (state.leds & 8) ? "R" : "-",
942 (state.leds & 4) ? "G" : "-",
943 (state.leds & 2) ? "Y" : "-",
944 (state.leds & 1) ? "R" : "-");
945 handled = true;
946 break;
947 case 0x0B0000: // TM/DIALWR
948 break;
949 case 0x0C0000: // Clear Status Register
950 state.genstat = 0xFFFF;
951 state.bsr0 = 0xFFFF;
952 state.bsr1 = 0xFFFF;
953 handled = true;
954 break;
955 case 0x0D0000: // DMA Address Register
956 break;
957 case 0x0E0000: // Disk Control Register
958 break;
959 case 0x0F0000: // Line Printer Data Register
960 break;
961 }
962 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
963 // I/O register space, zone B
964 switch (address & 0xF00000) {
965 case 0xC00000: // Expansion slots
966 case 0xD00000:
967 switch (address & 0xFC0000) {
968 case 0xC00000: // Expansion slot 0
969 case 0xC40000: // Expansion slot 1
970 case 0xC80000: // Expansion slot 2
971 case 0xCC0000: // Expansion slot 3
972 case 0xD00000: // Expansion slot 4
973 case 0xD40000: // Expansion slot 5
974 case 0xD80000: // Expansion slot 6
975 case 0xDC0000: // Expansion slot 7
976 fprintf(stderr, "NOTE: WR16 to expansion card space, addr=0x%08X, data=0x%04X\n", address, value);
977 break;
978 }
979 break;
980 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
981 case 0xF00000:
982 switch (address & 0x070000) {
983 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
984 break;
985 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
986 break;
987 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
988 break;
989 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
990 break;
991 case 0x040000: // [ef][4c]xxxx ==> General Control Register
992 switch (address & 0x077000) {
993 case 0x040000: // [ef][4c][08]xxx ==> EE
994 break;
995 case 0x041000: // [ef][4c][19]xxx ==> PIE
996 state.pie = ((value & 0x8000) == 0x8000);
997 handled = true;
998 break;
999 case 0x042000: // [ef][4c][2A]xxx ==> BP
1000 break;
1001 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
1002 state.romlmap = ((value & 0x8000) == 0x8000);
1003 handled = true;
1004 break;
1005 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
1006 break;
1007 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
1008 break;
1009 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
1010 break;
1011 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
1012 break;
1013 }
1014 case 0x050000: // [ef][5d]xxxx ==> 8274
1015 break;
1016 case 0x060000: // [ef][6e]xxxx ==> Control regs
1017 switch (address & 0x07F000) {
1018 default:
1019 break;
1020 }
1021 break;
1022 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
1023 break;
1024 }
1025 }
1026 }
1028 LOG_NOT_HANDLED_W(16);
1029 }
1031 /**
1032 * @brief Write M68K memory, 8-bit
1033 */
1034 void m68k_write_memory_8(uint32_t address, uint32_t value)
1035 {
1036 bool handled = false;
1038 // If ROMLMAP is set, force system to access ROM
1039 if (!state.romlmap)
1040 address |= 0x800000;
1042 // Check access permissions
1043 ACCESS_CHECK_WR(address, 8);
1045 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
1046 // ROM access (read only!)
1047 handled = true;
1048 } else if (address <= (state.ram_size - 1)) {
1049 // RAM access
1050 WR8(state.ram, mapAddr(address, false), state.ram_size - 1, value);
1051 handled = true;
1052 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
1053 // I/O register space, zone A
1054 switch (address & 0x0F0000) {
1055 case 0x000000: // Map RAM access
1056 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=%08X, data=%02X\n", address, value);
1057 WR8(state.map, address, 0x7FF, value);
1058 handled = true;
1059 break;
1060 case 0x010000: // General Status Register
1061 handled = true;
1062 break;
1063 case 0x020000: // Video RAM
1064 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=%08X, data=0x%02X\n", address, value);
1065 WR8(state.vram, address, 0x7FFF, value);
1066 handled = true;
1067 break;
1068 case 0x030000: // Bus Status Register 0
1069 handled = true;
1070 break;
1071 case 0x040000: // Bus Status Register 1
1072 handled = true;
1073 break;
1074 case 0x050000: // Phone status
1075 break;
1076 case 0x060000: // DMA Count
1077 break;
1078 case 0x070000: // Line Printer Status Register
1079 break;
1080 case 0x080000: // Real Time Clock
1081 break;
1082 case 0x090000: // Phone registers
1083 switch (address & 0x0FF000) {
1084 case 0x090000: // Handset relay
1085 case 0x098000:
1086 break;
1087 case 0x091000: // Line select 2
1088 case 0x099000:
1089 break;
1090 case 0x092000: // Hook relay 1
1091 case 0x09A000:
1092 break;
1093 case 0x093000: // Hook relay 2
1094 case 0x09B000:
1095 break;
1096 case 0x094000: // Line 1 hold
1097 case 0x09C000:
1098 break;
1099 case 0x095000: // Line 2 hold
1100 case 0x09D000:
1101 break;
1102 case 0x096000: // Line 1 A-lead
1103 case 0x09E000:
1104 break;
1105 case 0x097000: // Line 2 A-lead
1106 case 0x09F000:
1107 break;
1108 }
1109 break;
1110 case 0x0A0000: // Miscellaneous Control Register
1111 // TODO: handle the ctrl bits properly
1112 if ((address & 1) == 0)
1113 ;// CTL bits
1114 else
1115 state.leds = (~value & 0xF);
1116 printf("LEDs: %s %s %s %s\n",
1117 (state.leds & 8) ? "R" : "-",
1118 (state.leds & 4) ? "G" : "-",
1119 (state.leds & 2) ? "Y" : "-",
1120 (state.leds & 1) ? "R" : "-");
1121 handled = true;
1122 break;
1123 case 0x0B0000: // TM/DIALWR
1124 break;
1125 case 0x0C0000: // Clear Status Register
1126 state.genstat = 0xFFFF;
1127 state.bsr0 = 0xFFFF;
1128 state.bsr1 = 0xFFFF;
1129 handled = true;
1130 break;
1131 case 0x0D0000: // DMA Address Register
1132 break;
1133 case 0x0E0000: // Disk Control Register
1134 break;
1135 case 0x0F0000: // Line Printer Data Register
1136 break;
1137 }
1138 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
1139 // I/O register space, zone B
1140 switch (address & 0xF00000) {
1141 case 0xC00000: // Expansion slots
1142 case 0xD00000:
1143 switch (address & 0xFC0000) {
1144 case 0xC00000: // Expansion slot 0
1145 case 0xC40000: // Expansion slot 1
1146 case 0xC80000: // Expansion slot 2
1147 case 0xCC0000: // Expansion slot 3
1148 case 0xD00000: // Expansion slot 4
1149 case 0xD40000: // Expansion slot 5
1150 case 0xD80000: // Expansion slot 6
1151 case 0xDC0000: // Expansion slot 7
1152 fprintf(stderr, "NOTE: WR8 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
1153 break;
1154 }
1155 break;
1156 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
1157 case 0xF00000:
1158 switch (address & 0x070000) {
1159 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
1160 break;
1161 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
1162 break;
1163 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
1164 break;
1165 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
1166 break;
1167 case 0x040000: // [ef][4c]xxxx ==> General Control Register
1168 switch (address & 0x077000) {
1169 case 0x040000: // [ef][4c][08]xxx ==> EE
1170 break;
1171 case 0x041000: // [ef][4c][19]xxx ==> PIE
1172 if ((address & 1) == 0)
1173 state.pie = ((value & 0x80) == 0x80);
1174 handled = true;
1175 break;
1176 case 0x042000: // [ef][4c][2A]xxx ==> BP
1177 break;
1178 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
1179 if ((address & 1) == 0)
1180 state.romlmap = ((value & 0x80) == 0x80);
1181 handled = true;
1182 break;
1183 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
1184 break;
1185 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
1186 break;
1187 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
1188 break;
1189 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
1190 break;
1191 }
1192 case 0x050000: // [ef][5d]xxxx ==> 8274
1193 break;
1194 case 0x060000: // [ef][6e]xxxx ==> Control regs
1195 switch (address & 0x07F000) {
1196 default:
1197 break;
1198 }
1199 break;
1200 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
1201 break;
1202 default:
1203 fprintf(stderr, "NOTE: WR8 to undefined E/F-block space, addr=0x%08X, data=0x%08X\n", address, value);
1204 break;
1205 }
1206 }
1207 }
1209 LOG_NOT_HANDLED_W(8);
1210 }
1213 // for the disassembler
1214 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
1215 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
1216 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }