src/memory.c

Fri, 12 Apr 2013 12:36:28 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Fri, 12 Apr 2013 12:36:28 +0100
branch
experimental_memory_mapper_v2
changeset 141
8460d432606f
parent 140
1e4c45b144c4
child 144
609707511166
permissions
-rw-r--r--

Make mapper debug logic more verbose (but disable by default)

     1 #include <stdio.h>
     2 #include <stdlib.h>
     3 #include <stdint.h>
     4 #include <stdbool.h>
     5 #include <assert.h>
     6 #include "musashi/m68k.h"
     7 #include "state.h"
     8 #include "utils.h"
     9 #include "memory.h"
    11 // The value which will be returned if the CPU attempts to read from empty memory
    12 // TODO (FIXME?) - need to figure out if R/W ops wrap around. This seems to appease the UNIX kernel and P4TEST.
    13 #define EMPTY 0xFFFFFFFFUL
    14 //#define EMPTY 0x55555555UL
    15 //#define EMPTY 0x00000000UL
    17 /******************
    18  * Memory mapping
    19  ******************/
    21 /// Set a page bit
    22 #define MAP_SET_PAGEBIT(addr, bit) state.map[(MAP_ADDR_TO_PAGE(addr))*2] |=  ((uint8_t)bit << 2)
    23 /// Clear a page bit
    24 #define MAP_CLR_PAGEBIT(addr, bit) state.map[(MAP_ADDR_TO_PAGE(addr))*2] &= ~((uint8_t)bit << 2)
    27 /********************************************************
    28  * m68k memory read/write support functions for Musashi
    29  ********************************************************/
    31 /**
    32  * @brief	Check memory access permissions for a write operation.
    33  * @note	This used to be a single macro (merged with ACCESS_CHECK_RD), but
    34  * 			gcc throws warnings when you have a return-with-value in a void
    35  * 			function, even if the return-with-value is completely unreachable.
    36  * 			Similarly it doesn't like it if you have a return without a value
    37  * 			in a non-void function, even if it's impossible to ever reach the
    38  * 			return-with-no-value. UGH!
    39  */
    40 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
    41 #define ACCESS_CHECK_WR(address, bits)								\
    42 	do {															\
    43 		if (access_check_cpu(address, bits, true)) {				\
    44 			return;													\
    45 		}															\
    46 	} while (0)
    47 /*}}}*/
    49 /**
    50  * @brief Check memory access permissions for a read operation.
    51  * @note	This used to be a single macro (merged with ACCESS_CHECK_WR), but
    52  * 			gcc throws warnings when you have a return-with-value in a void
    53  * 			function, even if the return-with-value is completely unreachable.
    54  * 			Similarly it doesn't like it if you have a return without a value
    55  * 			in a non-void function, even if it's impossible to ever reach the
    56  * 			return-with-no-value. UGH!
    57  */
    58 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
    59 #define ACCESS_CHECK_RD(address, bits)								\
    60 	do {															\
    61 		if (access_check_cpu(address, bits, false)) {				\
    62 			if (bits == 32)											\
    63 				return EMPTY & 0xFFFFFFFF;							\
    64 			else													\
    65 				return EMPTY & ((1UL << bits)-1);					\
    66 		}															\
    67 	} while (0)
    68 /*}}}*/
    71 /**
    72  * Update the page bits for a given memory address
    73  *
    74  * @param	addr	Memory address being accessed
    75  * @param	l7intr	Set to <i>true</i> if a level-seven interrupt has been
    76  * 					signalled (even if <b>ENABLE ERROR</b> isn't set).
    77  * @param	write	Set to <i>true</i> if the address is being written to.
    78  */
    79 static void update_page_bits(uint32_t addr, bool l7intr, bool write)
    80 {
    81 	bool ps0_state = false;
    83 	// Don't try and update pagebits for non-RAM addresses
    84 	if (addr > 0x3FFFFF)
    85 		return;
    87 	if (l7intr) {
    88 //		if (!(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
    89 			// FIXME FUCKUP The ruddy TRM is wrong AGAIN! If above line is uncommented, Really Bad Things Happen.
    90 		if ((MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
    91 			// Level 7 interrupt, PS0 clear, PS1 don't-care. Set PS0.
    92 			ps0_state = true;
    93 		}
    94 	} else {
    95 		// No L7 interrupt
    96 		if ((write && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS1) &&  (MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) ||
    97 			(write &&  (MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) ||
    98 			(          (MAP_PAGEBITS(addr) & PAGE_BIT_PS1) &&  (MAP_PAGEBITS(addr) & PAGE_BIT_PS0)))  /* NOTE -- Once again, this case was missing from the PAL equations in the TRM... */
    99 		{
   100 			// No L7 interrupt, PS[1:0] = 0b01, write
   101 			// No L7 interrupt, PS[1:0] = 0b10, write
   102 			ps0_state = true;
   103 		}
   104 	}
   106 #ifdef MAPRAM_BIT_TEST
   107 	LOG("Starting Mapram Bit Test");
   108 	state.map[0] = state.map[1] = 0;
   109 	LOG("Start   = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   110 	MAP_SET_PAGEBIT(0, PAGE_BIT_WE);
   111 	LOG("Set WE  = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   112 	MAP_SET_PAGEBIT(0, PAGE_BIT_PS1);
   113 	LOG("Set PS1 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   114 	MAP_SET_PAGEBIT(0, PAGE_BIT_PS0);
   115 	LOG("Set PS0 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   117 	MAP_CLR_PAGEBIT(0, PAGE_BIT_WE);
   118 	LOG("Clr WE  = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   119 	MAP_CLR_PAGEBIT(0, PAGE_BIT_PS1);
   120 	LOG("Clr PS1 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   121 	MAP_CLR_PAGEBIT(0, PAGE_BIT_PS0);
   122 	LOG("Clr PS0 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   123 	exit(-1);
   124 #endif
   126 #ifdef MAPRAM_DEBUG_MESSAGES
   127 	uint16_t old_pagebits = MAP_PAGEBITS(addr);
   128 #endif
   130 	// PS1 is always set on access
   131 	MAP_SET_PAGEBIT(addr, PAGE_BIT_PS1);
   133 #ifdef MAPRAM_DEBUG_MESSAGES
   134 	uint16_t new_pagebit1 = MAP_PAGEBITS(addr);
   135 #endif
   137 	// Update PS0
   138 	if (ps0_state) {
   139 		MAP_SET_PAGEBIT(addr, PAGE_BIT_PS0);
   140 	} else {
   141 		MAP_CLR_PAGEBIT(addr, PAGE_BIT_PS0);
   142 	}
   144 #ifdef MAPRAM_DEBUG_MESSAGES
   145 	uint16_t new_pagebit2 = MAP_PAGEBITS(addr);
   146 	switch (addr) {
   147 		case 0x000000:
   148 		case 0x001000:
   149 		case 0x002000:
   150 		case 0x003000:
   151 		case 0x004000:
   152 		case 0x033000:
   153 		case 0x034000:
   154 		case 0x035000:
   155 			LOG("Addr %08X %s MapNew %04X Page %04X -- Pagebit update -- ps0 %d, old %s%s => %s%s => %s%s",
   156 					addr,
   157 					write ? "Wr" : "Rd",
   158 					MAPRAM_ADDR(addr),
   159 					MAP_ADDR_TO_PAGE(addr),
   160 					ps0_state,
   161 					old_pagebits & PAGE_BIT_PS0 ? "PS0" : "",
   162 					old_pagebits & PAGE_BIT_PS1 ? "PS1" : "",
   163 					new_pagebit1 & PAGE_BIT_PS0 ? "PS0" : "",
   164 					new_pagebit1 & PAGE_BIT_PS1 ? "PS1" : "",
   165 					new_pagebit2 & PAGE_BIT_PS0 ? "PS0" : "",
   166 					new_pagebit2 & PAGE_BIT_PS1 ? "PS1" : ""
   167 			   );
   168 		default:
   169 			break;
   170 	}
   171 #endif // MAPRAM_DEBUG_MESSAGES
   172 }
   174 bool access_check_dma(void)
   175 {
   176 	// TODO FIXME BUGBUG Sanity check - Make sure DMAC is only accessing RAM addresses
   178 	// DMA access check -- make sure the page is mapped in
   179 	if (!(MAP_PAGEBITS(state.dma_address) & PAGE_BIT_PS0) && !(MAP_PAGEBITS(state.dma_address) & PAGE_BIT_PS1)) {
   180 		// DMA access to page which is not mapped in.
   181 		// Level 7 interrupt, page fault, DMA invoked
   182 		state.genstat = 0xABFF
   183 			| (state.dma_reading ? 0x4000 : 0)
   184 			| (state.pie ? 0x0400 : 0);
   186 		// XXX: Check all this stuff.
   187 		state.bsr0 = 0x3C00;
   188 		state.bsr0 |= (state.dma_address >> 16);
   189 		state.bsr1 = state.dma_address & 0xffff;
   191 		// Update page bits for this transfer
   192 		update_page_bits(state.dma_address, true, !state.dma_reading);
   194 		// XXX: is this right?
   195 		// Fire a Level 7 interrupt
   196 		/*if (state.ee)*/ m68k_set_irq(7);
   198 		LOG("BUS ERROR FROM DMA: genstat=%04X, bsr0=%04X, bsr1=%04X\n", state.genstat, state.bsr0, state.bsr1);
   199 		return false;
   200 	} else {
   201 		// No errors. Just update the page bits.
   202 		update_page_bits(state.dma_address, false, !state.dma_reading);
   203 		return true;
   204 	}
   205 }
   207 /**
   208  * Check memory access permissions for a CPU memory access.
   209  *
   210  * @param	addr	Virtual memory address being accessed (from CPU address bus).
   211  * @param	bits	Word size of this transfer (8, 16 or 32 bits).
   212  * @param	write	<i>true</i> if this is a write operation, <i>false</i> if it is a read operation.
   213  * @return	<i>true</i> if the access was denied and a level-7 interrupt and/or bus error raised.
   214  * 			<i>false</i> if the access was allowed.
   215  */
   216 bool access_check_cpu(uint32_t addr, int bits, bool write)
   217 {
   218 	bool supervisor = (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000);
   219 	bool fault = false;
   221 	// TODO FIXME BUGBUG? Do we need to check for supervisor access here?
   222 	if ((addr >= 0x000000) && (addr <= 0x3FFFFF) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
   223 		// (A) Page Fault -- user access to page which is not mapped in
   224 		// Level 7 Interrupt, Bus Error, regs=PAGEFAULT
   225 		if (write) {
   226 			state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0);
   227 		} else {
   228 			state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0);
   229 		}
   230 		fault = true;
   231 	} else if (!supervisor && (addr >= 0x000000) && (addr <= 0x07FFFF)) {
   232 		// (B) User attempted to access the kernel
   233 		// Level 7 Interrupt, Bus Error, regs=KERNEL
   234 		if (write) {
   235 			// XXX: BUGBUG? Is this correct?
   236 			state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0);
   237 		} else {
   238 			state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0);
   239 		}
   240 		fault = true;
   241 	} else if (!supervisor && write && (addr >= 0x000000) && (addr <= 0x3FFFFF) && !(MAP_PAGEBITS(addr) & PAGE_BIT_WE)) {
   242 		// (C) User attempted to write to a page which is not write enabled
   243 		// Level 7 Interrupt, Bus Error, regs=WRITE_EN
   244 		if (write) {
   245 			// XXX: BUGBUG? Is this correct?
   246 			state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0);
   247 		} else {
   248 			state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0);
   249 		}
   250 		fault = true;
   251 	} else if (!supervisor && (addr >= 0x400000) && (addr <= 0xFFFFFF)) {
   252 		// (D) UIE - user I/O exception
   253 		// Bus Error only, regs=UIE
   254 		if (write) {
   255 			state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0);
   256 		} else {
   257 			state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0);
   258 		}
   259 		fault = true;
   260 	}
   262 	// Update the page bits first
   263 	update_page_bits(addr, fault, write);
   265 	if (fault) {
   266 		if (bits >= 16)
   267 			state.bsr0 = 0x7C00;
   268 		else
   269 			state.bsr0 = (addr & 1) ? 0x7E00 : 0x7D00;
   270 		// FIXME? Physical or virtual address here?
   271 		state.bsr0 |= (addr >> 16);
   272 		state.bsr1 = addr & 0xffff;
   274 		LOG("CPU Bus Error or L7Intr while %s, vaddr %08X, map %08X, pagebits 0x%02X bsr0=%04X bsr1=%04X genstat=%04X", 
   275 				write ? "writing" : "reading", addr,
   276 				MAPRAM_ADDR(addr & 0x3fffff),
   277 				MAP_PAGEBITS(addr & 0x3fffff),
   278 				state.bsr0, state.bsr1, state.genstat);
   280 		// FIXME? BUGBUG? Does EE disable one or both of these?
   281 		// /*if (state.ee)*/ m68k_set_irq(7);
   282 		/*if (state.ee)*/ m68k_pulse_bus_error();
   283 	}
   285 	return fault;
   286 }
   288 // Logging macros
   289 #define LOG_NOT_HANDLED_R(bits)															\
   290 	if (!handled) fprintf(stderr, "unhandled read%02d, addr=0x%08X\n", bits, address);
   292 #define LOG_NOT_HANDLED_W(bits)															\
   293 	if (!handled) fprintf(stderr, "unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
   295 /********************************************************
   296  * I/O read/write functions
   297  ********************************************************/
   299 /**
   300  * Issue a warning if a read operation is made with an invalid size
   301  */
   302 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
   303 {
   304 	assert((bits == 8) || (bits == 16) || (bits == 32));
   305 	if ((bits & allowed) == 0) {
   306 		LOG("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
   307 	}
   308 }
   310 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
   311 {
   312 	ENFORCE_SIZE(bits, address, true, allowed, regname);
   313 }
   315 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
   316 {
   317 	ENFORCE_SIZE(bits, address, false, allowed, regname);
   318 }
   320 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
   321 {
   322 	bool handled = false;
   324 	if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   325 		// I/O register space, zone A
   326 		switch (address & 0x0F0000) {
   327 			case 0x010000:				// General Status Register
   328 				if (bits == 16)
   329 					state.genstat = (data & 0xffff);
   330 				else if (bits == 8) {
   331 					if (address & 0)
   332 						state.genstat = data;
   333 					else
   334 						state.genstat = data << 8;
   335 				}
   336 				handled = true;
   337 				break;
   338 			case 0x030000:				// Bus Status Register 0
   339 				break;
   340 			case 0x040000:				// Bus Status Register 1
   341 				break;
   342 			case 0x050000:				// Phone status
   343 				break;
   344 			case 0x060000:				// DMA Count
   345 				ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
   346 				state.dma_count = (data & 0x3FFF);
   347 				state.idmarw = ((data & 0x4000) == 0x4000);
   348 				state.dmaen = ((data & 0x8000) == 0x8000);
   349 				// This handles the "dummy DMA transfer" mentioned in the docs
   350 				// disabled because it causes the floppy test to fail
   351 #if 0
   352 				if (!state.idmarw){
   353 					if (access_check_dma(true)){
   354 						uint32_t newAddr = mapAddr(state.dma_address, true);
   355 						// RAM access
   356 						if (newAddr <= 0x1fffff)
   357 							WR16(state.base_ram, newAddr, state.base_ram_size - 1, 0xFF);
   358 						else if (address <= 0x3FFFFF)
   359 							WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, 0xFF);
   360 					}
   361 				}
   362 #endif
   363 				state.dma_count++;
   364 				handled = true;
   365 				break;
   366 			case 0x070000:				// Line Printer Status Register
   367 				break;
   368 			case 0x080000:				// Real Time Clock
   369 				LOGS("REAL TIME CLOCK WRITE");
   370 				break;
   371 			case 0x090000:				// Phone registers
   372 				switch (address & 0x0FF000) {
   373 					case 0x090000:		// Handset relay
   374 					case 0x098000:
   375 						break;
   376 					case 0x091000:		// Line select 2
   377 					case 0x099000:
   378 						break;
   379 					case 0x092000:		// Hook relay 1
   380 					case 0x09A000:
   381 						break;
   382 					case 0x093000:		// Hook relay 2
   383 					case 0x09B000:
   384 						break;
   385 					case 0x094000:		// Line 1 hold
   386 					case 0x09C000:
   387 						break;
   388 					case 0x095000:		// Line 2 hold
   389 					case 0x09D000:
   390 						break;
   391 					case 0x096000:		// Line 1 A-lead
   392 					case 0x09E000:
   393 						break;
   394 					case 0x097000:		// Line 2 A-lead
   395 					case 0x09F000:
   396 						break;
   397 				}
   398 				break;
   399 			case 0x0A0000:				// Miscellaneous Control Register
   400 				ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
   401 				// TODO: handle the ctrl bits properly
   402 				if (data & 0x8000){
   403 					state.timer_enabled = 1;
   404 				}else{
   405 					state.timer_enabled = 0;
   406 					state.timer_asserted = 0;
   407 				}
   408 				state.dma_reading = (data & 0x4000);
   409 				if (state.leds != ((~data & 0xF00) >> 8)) {
   410 					state.leds = (~data & 0xF00) >> 8;
   411 #ifdef SHOW_LEDS
   412 					printf("LEDs: %s %s %s %s\n",
   413 							(state.leds & 8) ? "R" : "-",
   414 							(state.leds & 4) ? "G" : "-",
   415 							(state.leds & 2) ? "Y" : "-",
   416 							(state.leds & 1) ? "R" : "-");
   417 #endif
   418 				}
   419 				handled = true;
   420 				break;
   421 			case 0x0B0000:				// TM/DIALWR
   422 				break;
   423 			case 0x0C0000:				// Clear Status Register
   424 				state.genstat = 0xFFFF;
   425 				state.bsr0 = 0xFFFF;
   426 				state.bsr1 = 0xFFFF;
   427 				handled = true;
   428 				break;
   429 			case 0x0D0000:				// DMA Address Register
   430 				if (address & 0x004000) {
   431 					// A14 high -- set most significant bits
   432 					state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
   433 				} else {
   434 					// A14 low -- set least significant bits
   435 					state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
   436 				}
   437 				handled = true;
   438 				break;
   439 			case 0x0E0000:				// Disk Control Register
   440 				{
   441 					bool fd_selected;
   442 					bool hd_selected;
   443 					ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
   444 					// B7 = FDD controller reset
   445 					if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
   446 					// B6 = drive 0 select
   447 					fd_selected = (data & 0x40) != 0;
   448 					// B5 = motor enable -- TODO
   449 					// B4 = HDD controller reset
   450 					if ((data & 0x10) == 0) wd2010_reset(&state.hdc_ctx);
   451 					// B3 = HDD0 select
   452 					hd_selected = (data & 0x08) != 0;
   453 					// B2,1,0 = HDD0 head select -- TODO?
   454 					if (hd_selected && !state.hd_selected){
   455 						state.fd_selected = false;
   456 						state.hd_selected = true;
   457 					}else if (fd_selected && !state.fd_selected){
   458 						state.hd_selected = false;
   459 						state.fd_selected = true;
   460 					}
   461 					handled = true;
   462 					break;
   463 				}
   464 			case 0x0F0000:				// Line Printer Data Register
   465 				break;
   466 		}
   467 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   468 		// I/O register space, zone B
   469 		switch (address & 0xF00000) {
   470 			case 0xC00000:				// Expansion slots
   471 			case 0xD00000:
   472 				switch (address & 0xFC0000) {
   473 					case 0xC00000:		// Expansion slot 0
   474 					case 0xC40000:		// Expansion slot 1
   475 					case 0xC80000:		// Expansion slot 2
   476 					case 0xCC0000:		// Expansion slot 3
   477 					case 0xD00000:		// Expansion slot 4
   478 					case 0xD40000:		// Expansion slot 5
   479 					case 0xD80000:		// Expansion slot 6
   480 					case 0xDC0000:		// Expansion slot 7
   481 						fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
   482 						handled = true;
   483 						break;
   484 				}
   485 				break;
   486 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   487 			case 0xF00000:
   488 				switch (address & 0x070000) {
   489 					case 0x000000:		// [ef][08]xxxx ==> WD2010 hard disc controller
   490 						wd2010_write_reg(&state.hdc_ctx, (address >> 1) & 7, data);
   491 						handled = true;
   492 						break;
   493 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   494 						/*ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");*/
   495 						wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
   496 						handled = true;
   497 						break;
   498 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   499 						// MCR2 - UNIX PC Rev. P5.1 HDD head select b3 and potential HDD#2 select
   500 						wd2010_write_reg(&state.hdc_ctx, UNIXPC_REG_MCR2, data);
   501 						handled = true;
   502 						break;
   503 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   504 						LOGS("REAL TIME CLOCK DATA WRITE");
   505 						break;
   506 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   507 						switch (address & 0x077000) {
   508 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   509 								// Error Enable. If =0, Level7 intrs and bus errors are masked.
   510 								ENFORCE_SIZE_W(bits, address, 16, "EE");
   511 								state.ee = ((data & 0x8000) == 0x8000);
   512 								handled = true;
   513 								break;
   514 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   515 								ENFORCE_SIZE_W(bits, address, 16, "PIE");
   516 								state.pie = ((data & 0x8000) == 0x8000);
   517 								handled = true;
   518 								break;
   519 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   520 								break;
   521 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   522 								ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
   523 								state.romlmap = ((data & 0x8000) == 0x8000);
   524 								handled = true;
   525 								break;
   526 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   527 								ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
   528 								break;
   529 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   530 								ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
   531 								break;
   532 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   533 								ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
   534 								break;
   535 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   536 								ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
   537 								break;
   538 						}
   539 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   540 						break;
   541 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   542 						switch (address & 0x07F000) {
   543 							default:
   544 								break;
   545 						}
   546 						break;
   547 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   548 						// TODO: figure out which sizes are valid (probably just 8 and 16)
   549 						// ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER");
   550 						if (bits == 8) {
   551 #ifdef LOG_KEYBOARD_WRITES
   552 							LOG("KBD WR %02X => %02X\n", (address >> 1) & 3, data);
   553 #endif
   554 							keyboard_write(&state.kbd, (address >> 1) & 3, data);
   555 							handled = true;
   556 						} else if (bits == 16) {
   557 #ifdef LOG_KEYBOARD_WRITES
   558 							LOG("KBD WR %02X => %04X\n", (address >> 1) & 3, data);
   559 #endif
   560 							keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8);
   561 							handled = true;
   562 						}
   563 						break;
   564 				}
   565 		}
   566 	}
   568 	LOG_NOT_HANDLED_W(bits);
   569 }/*}}}*/
   571 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
   572 {
   573 	bool handled = false;
   574 	uint32_t data = EMPTY & 0xFFFFFFFF;
   576 	if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   577 		// I/O register space, zone A
   578 		switch (address & 0x0F0000) {
   579 			case 0x010000:				// General Status Register
   580 				/* ENFORCE_SIZE_R(bits, address, 16, "GENSTAT"); */
   581 				if (bits == 32) {
   582 					return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
   583 				} else if (bits == 16) {
   584 					return (uint16_t)state.genstat;
   585 				} else {
   586 					return (uint8_t)(state.genstat & 0xff);
   587 				}
   588 				break;
   589 			case 0x030000:				// Bus Status Register 0
   590 				ENFORCE_SIZE_R(bits, address, 16, "BSR0");
   591 				return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
   592 				break;
   593 			case 0x040000:				// Bus Status Register 1
   594 				ENFORCE_SIZE_R(bits, address, 16, "BSR1");
   595 				return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
   596 				break;
   597 			case 0x050000:				// Phone status
   598 				ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
   599 				break;
   600 			case 0x060000:				// DMA Count
   601 				// TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
   602 				// Bit 14 is always unused, so leave it set
   603 				ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
   604 				return (state.dma_count & 0x3fff) | 0xC000;
   605 				break;
   606 			case 0x070000:				// Line Printer Status Register
   607 				data = 0x00120012;	// no parity error, no line printer error, no irqs from FDD or HDD
   608 				data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0;
   609 				data |= wd2010_get_irq(&state.hdc_ctx) ? 0x00040004 : 0;
   610 				return data;
   611 				break;
   612 			case 0x080000:				// Real Time Clock
   613 				LOGS("REAL TIME CLOCK READ");
   614 				break;
   615 			case 0x090000:				// Phone registers
   616 				switch (address & 0x0FF000) {
   617 					case 0x090000:		// Handset relay
   618 					case 0x098000:
   619 						break;
   620 					case 0x091000:		// Line select 2
   621 					case 0x099000:
   622 						break;
   623 					case 0x092000:		// Hook relay 1
   624 					case 0x09A000:
   625 						break;
   626 					case 0x093000:		// Hook relay 2
   627 					case 0x09B000:
   628 						break;
   629 					case 0x094000:		// Line 1 hold
   630 					case 0x09C000:
   631 						break;
   632 					case 0x095000:		// Line 2 hold
   633 					case 0x09D000:
   634 						break;
   635 					case 0x096000:		// Line 1 A-lead
   636 					case 0x09E000:
   637 						break;
   638 					case 0x097000:		// Line 2 A-lead
   639 					case 0x09F000:
   640 						break;
   641 				}
   642 				break;
   643 			case 0x0A0000:				// Miscellaneous Control Register -- write only!
   644 				handled = true;
   645 				break;
   646 			case 0x0B0000:				// TM/DIALWR
   647 				break;
   648 			case 0x0C0000:				// Clear Status Register -- write only!
   649 				handled = true;
   650 				break;
   651 			case 0x0D0000:				// DMA Address Register
   652 				break;
   653 			case 0x0E0000:				// Disk Control Register
   654 				break;
   655 			case 0x0F0000:				// Line Printer Data Register
   656 				break;
   657 		}
   658 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   659 		// I/O register space, zone B
   660 		switch (address & 0xF00000) {
   661 			case 0xC00000:				// Expansion slots
   662 			case 0xD00000:
   663 				switch (address & 0xFC0000) {
   664 					case 0xC00000:		// Expansion slot 0
   665 					case 0xC40000:		// Expansion slot 1
   666 					case 0xC80000:		// Expansion slot 2
   667 					case 0xCC0000:		// Expansion slot 3
   668 					case 0xD00000:		// Expansion slot 4
   669 					case 0xD40000:		// Expansion slot 5
   670 					case 0xD80000:		// Expansion slot 6
   671 					case 0xDC0000:		// Expansion slot 7
   672 						fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
   673 						handled = true;
   674 						break;
   675 				}
   676 				break;
   677 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   678 			case 0xF00000:
   679 				switch (address & 0x070000) {
   680 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   681 						return (wd2010_read_reg(&state.hdc_ctx, (address >> 1) & 7));
   683 						break;
   684 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   685 						/*ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");*/
   686 						return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
   687 						break;
   688 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   689 						break;
   690 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   691 						LOGS("REAL TIME CLOCK DATA READ");
   692 						break;
   693 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   694 						switch (address & 0x077000) {
   695 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   696 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   697 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   698 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   699 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   700 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   701 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   702 								// All write-only registers... TODO: bus error?
   703 								handled = true;
   704 								break;
   705 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
   706 								break;
   707 						}
   708 						break;
   709 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   710 						break;
   711 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   712 						switch (address & 0x07F000) {
   713 							default:
   714 								break;
   715 						}
   716 						break;
   717 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   718 						// TODO: figure out which sizes are valid (probably just 8 and 16)
   719 						//ENFORCE_SIZE_R(bits, address, 16, "KEYBOARD CONTROLLER");
   720 						{
   721 							if (bits == 8) {
   722 								return keyboard_read(&state.kbd, (address >> 1) & 3);
   723 							} else {
   724 								return keyboard_read(&state.kbd, (address >> 1) & 3) << 8;
   725 							}
   726 							return data;
   727 						}
   728 						break;
   729 				}
   730 		}
   731 	}
   733 	LOG_NOT_HANDLED_R(bits);
   735 	return data;
   736 }/*}}}*/
   739 /********************************************************
   740  * m68k memory read/write support functions for Musashi
   741  ********************************************************/
   743 /**
   744  * @brief Read M68K memory, 32-bit
   745  */
   746 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
   747 {
   748 	uint32_t data = EMPTY & 0xFFFFFFFF;
   750 	// If ROMLMAP is set, force system to access ROM
   751 	if (!state.romlmap)
   752 		address |= 0x800000;
   754 	// Check access permissions
   755 	ACCESS_CHECK_RD(address, 32);
   757 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   758 		// ROM access
   759 		return RD32(state.rom, address, ROM_SIZE - 1);
   760 	} else if (address <= 0x3fffff) {
   761 		// RAM access
   762 		uint32_t newAddr = MAP_ADDR(address);
   764 		if (newAddr <= 0x1fffff) {
   765 			// Base memory wraps around
   766 			return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
   767 		} else {
   768 			if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
   769 				return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   770 			else
   771 				return EMPTY & 0xffffffff;
   772 		}
   773 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   774 		// I/O register space, zone A
   775 		switch (address & 0x0F0000) {
   776 			case 0x000000:				// Map RAM access
   777 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
   778 				return RD32(state.map, address, 0x7FF);
   779 				break;
   780 			case 0x020000:				// Video RAM
   781 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
   782 				return RD32(state.vram, address, 0x7FFF);
   783 				break;
   784 			default:
   785 				return IoRead(address, 32);
   786 		}
   787 	} else {
   788 		return IoRead(address, 32);
   789 	}
   791 	return data;
   792 }/*}}}*/
   794 /**
   795  * @brief Read M68K memory, 16-bit
   796  */
   797 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
   798 {
   799 	uint16_t data = EMPTY & 0xFFFF;
   801 	// If ROMLMAP is set, force system to access ROM
   802 	if (!state.romlmap)
   803 		address |= 0x800000;
   805 	// Check access permissions
   806 	ACCESS_CHECK_RD(address, 16);
   808 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   809 		// ROM access
   810 		data = RD16(state.rom, address, ROM_SIZE - 1);
   811 	} else if (address <= 0x3fffff) {
   812 		// RAM access
   813 		uint32_t newAddr = MAP_ADDR(address);
   815 		if (newAddr <= 0x1fffff) {
   816 			// Base memory wraps around
   817 			return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
   818 		} else {
   819 			if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
   820 				return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   821 			else
   822 				return EMPTY & 0xffff;
   823 		}
   824 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   825 		// I/O register space, zone A
   826 		switch (address & 0x0F0000) {
   827 			case 0x000000:				// Map RAM access
   828 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
   829 				data = RD16(state.map, address, 0x7FF);
   830 				break;
   831 			case 0x020000:				// Video RAM
   832 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
   833 				data = RD16(state.vram, address, 0x7FFF);
   834 				break;
   835 			default:
   836 				data = IoRead(address, 16);
   837 		}
   838 	} else {
   839 		data = IoRead(address, 16);
   840 	}
   842 	return data;
   843 }/*}}}*/
   845 /**
   846  * @brief Read M68K memory, 8-bit
   847  */
   848 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
   849 {
   850 	uint8_t data = EMPTY & 0xFF;
   852 	// If ROMLMAP is set, force system to access ROM
   853 	if (!state.romlmap)
   854 		address |= 0x800000;
   856 	// Check access permissions
   857 	ACCESS_CHECK_RD(address, 8);
   859 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   860 		// ROM access
   861 		data = RD8(state.rom, address, ROM_SIZE - 1);
   862 	} else if (address <= 0x3fffff) {
   863 		// RAM access
   864 		uint32_t newAddr = MAP_ADDR(address);
   866 		if (newAddr <= 0x1fffff) {
   867 			// Base memory wraps around
   868 			return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
   869 		} else {
   870 			if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
   871 				return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   872 			else
   873 				return EMPTY & 0xff;
   874 		}
   875 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   876 		// I/O register space, zone A
   877 		switch (address & 0x0F0000) {
   878 			case 0x000000:				// Map RAM access
   879 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
   880 				data = RD8(state.map, address, 0x7FF);
   881 				break;
   882 			case 0x020000:				// Video RAM
   883 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
   884 				data = RD8(state.vram, address, 0x7FFF);
   885 				break;
   886 			default:
   887 				data = IoRead(address, 8);
   888 		}
   889 	} else {
   890 		data = IoRead(address, 8);
   891 	}
   893 	return data;
   894 }/*}}}*/
   896 /**
   897  * @brief Write M68K memory, 32-bit
   898  */
   899 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
   900 {
   901 	// If ROMLMAP is set, force system to access ROM
   902 	if (!state.romlmap)
   903 		address |= 0x800000;
   905 	// Check access permissions
   906 	ACCESS_CHECK_WR(address, 32);
   908 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   909 		// ROM access
   910 	} else if (address <= 0x3FFFFF) {
   911 		// RAM access
   912 		uint32_t newAddr = MAP_ADDR(address);
   914 		if (newAddr <= 0x1fffff) {
   915 			if (newAddr < state.base_ram_size) {
   916 				WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
   917 			}
   918 		} else {
   919 			if ((newAddr - 0x200000) < state.exp_ram_size) {
   920 				WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   921 			}
   922 		}
   923 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   924 		// I/O register space, zone A
   925 		switch (address & 0x0F0000) {
   926 			case 0x000000:				// Map RAM access
   927 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X\n", address);
   928 				WR32(state.map, address, 0x7FF, value);
   929 				break;
   930 			case 0x020000:				// Video RAM
   931 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X\n", address);
   932 				WR32(state.vram, address, 0x7FFF, value);
   933 				break;
   934 			default:
   935 				IoWrite(address, value, 32);
   936 		}
   937 	} else {
   938 		IoWrite(address, value, 32);
   939 	}
   940 }/*}}}*/
   942 /**
   943  * @brief Write M68K memory, 16-bit
   944  */
   945 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
   946 {
   947 	// If ROMLMAP is set, force system to access ROM
   948 	if (!state.romlmap)
   949 		address |= 0x800000;
   951 	// Check access permissions
   952 	ACCESS_CHECK_WR(address, 16);
   954 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   955 		// ROM access
   956 	} else if (address <= 0x3FFFFF) {
   957 		// RAM access
   958 		uint32_t newAddr = MAP_ADDR(address);
   960 		if (newAddr <= 0x1fffff) {
   961 			if (newAddr < state.base_ram_size) {
   962 				WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
   963 			}
   964 		} else {
   965 			if ((newAddr - 0x200000) < state.exp_ram_size) {
   966 				WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   967 			}
   968 		}
   969 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   970 		// I/O register space, zone A
   971 		switch (address & 0x0F0000) {
   972 			case 0x000000:				// Map RAM access
   973 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   974 				WR16(state.map, address, 0x7FF, value);
   975 				break;
   976 			case 0x020000:				// Video RAM
   977 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   978 				WR16(state.vram, address, 0x7FFF, value);
   979 				break;
   980 			default:
   981 				IoWrite(address, value, 16);
   982 		}
   983 	} else {
   984 		IoWrite(address, value, 16);
   985 	}
   986 }/*}}}*/
   988 /**
   989  * @brief Write M68K memory, 8-bit
   990  */
   991 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
   992 {
   993 	// If ROMLMAP is set, force system to access ROM
   994 	if (!state.romlmap)
   995 		address |= 0x800000;
   997 	// Check access permissions
   998 	ACCESS_CHECK_WR(address, 8);
  1000 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
  1001 		// ROM access (read only!)
  1002 	} else if (address <= 0x3FFFFF) {
  1003 		// RAM access
  1004 		uint32_t newAddr = MAP_ADDR(address);
  1006 		if (newAddr <= 0x1fffff) {
  1007 			if (newAddr < state.base_ram_size) {
  1008 				WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
  1010 		} else {
  1011 			if ((newAddr - 0x200000) < state.exp_ram_size) {
  1012 				WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
  1015 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
  1016 		// I/O register space, zone A
  1017 		switch (address & 0x0F0000) {
  1018 			case 0x000000:				// Map RAM access
  1019 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
  1020 				WR8(state.map, address, 0x7FF, value);
  1021 				break;
  1022 			case 0x020000:				// Video RAM
  1023 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
  1024 				WR8(state.vram, address, 0x7FFF, value);
  1025 				break;
  1026 			default:
  1027 				IoWrite(address, value, 8);
  1029 	} else {
  1030 		IoWrite(address, value, 8);
  1032 }/*}}}*/
  1035 // for the disassembler
  1036 uint32_t m68k_read_disassembler_32(uint32_t addr)
  1038 	if (addr < 0x400000) {
  1039 		// XXX FIXME BUGBUG update this to use the new mapper macros!
  1040 		uint16_t page = (addr >> 12) & 0x3FF;
  1041 		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
  1042 		uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
  1043 		if (newAddr <= 0x1fffff) {
  1044 			if (newAddr >= state.base_ram_size)
  1045 				return EMPTY;
  1046 			else
  1047 				return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
  1048 		} else {
  1049 			if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
  1050 				return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
  1051 			else
  1052 				return EMPTY;
  1054 	} else {
  1055 		LOG("WARNING: Disassembler RD32 out of range 0x%08X\n", addr);
  1056 		return EMPTY;
  1060 uint32_t m68k_read_disassembler_16(uint32_t addr)
  1062 	if (addr < 0x400000) {
  1063 		uint16_t page = (addr >> 12) & 0x3FF;
  1064 		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
  1065 		uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
  1066 		if (newAddr <= 0x1fffff) {
  1067 			if (newAddr >= state.base_ram_size)
  1068 				return EMPTY & 0xffff;
  1069 			else
  1070 				return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
  1071 		} else {
  1072 			if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
  1073 				return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
  1074 			else
  1075 				return EMPTY & 0xffff;
  1077 	} else {
  1078 		LOG("WARNING: Disassembler RD16 out of range 0x%08X\n", addr);
  1079 		return EMPTY & 0xffff;
  1083 uint32_t m68k_read_disassembler_8 (uint32_t addr)
  1085 	if (addr < 0x400000) {
  1086 		uint16_t page = (addr >> 12) & 0x3FF;
  1087 		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
  1088 		uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
  1089 		if (newAddr <= 0x1fffff) {
  1090 			if (newAddr >= state.base_ram_size)
  1091 				return EMPTY & 0xff;
  1092 			else
  1093 				return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
  1094 		} else {
  1095 			if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
  1096 				return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
  1097 			else
  1098 				return EMPTY & 0xff;
  1100 	} else {
  1101 		LOG("WARNING: Disassembler RD8 out of range 0x%08X\n", addr);
  1102 		return EMPTY & 0xff;