src/memory.c

Fri, 18 Jan 2013 22:52:43 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Fri, 18 Jan 2013 22:52:43 +0000
branch
experimental_memory_mapper_v2
changeset 132
8a7dc9b5b1db
parent 128
3246b74d96bc
parent 129
8b24770dea79
child 133
84ed5ec1d1e0
permissions
-rw-r--r--

merge in changes from default branch

     1 #include <stdio.h>
     2 #include <stdlib.h>
     3 #include <stdint.h>
     4 #include <stdbool.h>
     5 #include <assert.h>
     6 #include "musashi/m68k.h"
     7 #include "state.h"
     8 #include "utils.h"
     9 #include "memory.h"
    11 // The value which will be returned if the CPU attempts to read from empty memory
    12 // TODO (FIXME?) - need to figure out if R/W ops wrap around. This seems to appease the UNIX kernel and P4TEST.
    13 #define EMPTY 0xFFFFFFFFUL
    14 //#define EMPTY 0x55555555UL
    15 //#define EMPTY 0x00000000UL
    17 /******************
    18  * Memory mapping
    19  ******************/
    21 /// Set a page bit
    22 #define MAP_SET_PAGEBIT(addr, bit) state.map[(((addr) >> 12) & 0x3FF)*2] |=  (bit << 2)
    23 /// Clear a page bit
    24 #define MAP_CLR_PAGEBIT(addr, bit) state.map[(((addr) >> 12) & 0x3FF)*2] &= ~(bit << 2)
    27 /********************************************************
    28  * m68k memory read/write support functions for Musashi
    29  ********************************************************/
    31 /**
    32  * @brief	Check memory access permissions for a write operation.
    33  * @note	This used to be a single macro (merged with ACCESS_CHECK_RD), but
    34  * 			gcc throws warnings when you have a return-with-value in a void
    35  * 			function, even if the return-with-value is completely unreachable.
    36  * 			Similarly it doesn't like it if you have a return without a value
    37  * 			in a non-void function, even if it's impossible to ever reach the
    38  * 			return-with-no-value. UGH!
    39  */
    40 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
    41 #define ACCESS_CHECK_WR(address, bits)								\
    42 	do {															\
    43 		if (access_check_cpu(address, bits, true)) {				\
    44 			return;													\
    45 		}															\
    46 	} while (0)
    47 /*}}}*/
    49 /**
    50  * @brief Check memory access permissions for a read operation.
    51  * @note	This used to be a single macro (merged with ACCESS_CHECK_WR), but
    52  * 			gcc throws warnings when you have a return-with-value in a void
    53  * 			function, even if the return-with-value is completely unreachable.
    54  * 			Similarly it doesn't like it if you have a return without a value
    55  * 			in a non-void function, even if it's impossible to ever reach the
    56  * 			return-with-no-value. UGH!
    57  */
    58 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
    59 #define ACCESS_CHECK_RD(address, bits)								\
    60 	do {															\
    61 		if (access_check_cpu(address, bits, false)) {				\
    62 			if (bits == 32)											\
    63 				return EMPTY & 0xFFFFFFFF;							\
    64 			else													\
    65 				return EMPTY & ((1UL << bits)-1);					\
    66 		}															\
    67 	} while (0)
    68 /*}}}*/
    71 /**
    72  * Update the page bits for a given memory address
    73  *
    74  * @param	addr	Memory address being accessed
    75  * @param	l7intr	Set to <i>true</i> if a level-seven interrupt has been
    76  * 					signalled (even if <b>ENABLE ERROR</b> isn't set).
    77  * @param	write	Set to <i>true</i> if the address is being written to.
    78  */
    79 static void update_page_bits(uint32_t addr, bool l7intr, bool write)
    80 {
    81 	bool ps0_state = false;
    83 	// Don't try and update pagebits for non-RAM addresses
    84 	if (addr > 0x3FFFFF)
    85 		return;
    87 	if (l7intr) {
    88 //		if (!(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
    89 			// FIXME FUCKUP The ruddy TRM is wrong AGAIN! If above line is uncommented, Really Bad Things Happen.
    90 		if ((MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
    91 			// Level 7 interrupt, PS0 clear, PS1 don't-care. Set PS0.
    92 			ps0_state = true;
    93 		}
    94 	} else {
    95 		// No L7 interrupt
    96 		if ((write && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS1) &&  (MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) ||
    97 			(write &&  (MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)))
    98 		{
    99 			// No L7 interrupt, PS[1:0] = 0b01, write
   100 			// No L7 interrupt, PS[1:0] = 0b10, write
   101 			ps0_state = true;
   102 		}
   103 	}
   105 #ifdef MAPRAM_BIT_TEST
   106 	LOG("Starting Mapram Bit Test");
   107 	state.map[0] = state.map[1] = 0;
   108 	LOG("Start   = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   109 	MAP_SET_PAGEBIT(0, PAGE_BIT_WE);
   110 	LOG("Set WE  = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   111 	MAP_SET_PAGEBIT(0, PAGE_BIT_PS1);
   112 	LOG("Set PS1 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   113 	MAP_SET_PAGEBIT(0, PAGE_BIT_PS0);
   114 	LOG("Set PS0 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   116 	MAP_CLR_PAGEBIT(0, PAGE_BIT_WE);
   117 	LOG("Clr WE  = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   118 	MAP_CLR_PAGEBIT(0, PAGE_BIT_PS1);
   119 	LOG("Clr PS1 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   120 	MAP_CLR_PAGEBIT(0, PAGE_BIT_PS0);
   121 	LOG("Clr PS0 = %04X %02X", MAPRAM_ADDR(0), MAP_PAGEBITS(0));
   122 	exit(-1);
   123 #endif
   125 	uint16_t old_pagebits = MAP_PAGEBITS(addr);
   127 	// PS1 is always set on access
   128 	MAP_SET_PAGEBIT(addr, PAGE_BIT_PS1);
   130 	uint16_t new_pagebit1 = MAP_PAGEBITS(addr);
   132 	// Update PS0
   133 	if (ps0_state) {
   134 		MAP_SET_PAGEBIT(addr, PAGE_BIT_PS0);
   135 	} else {
   136 		MAP_CLR_PAGEBIT(addr, PAGE_BIT_PS0);
   137 	}
   139 	uint16_t new_pagebit2 = MAP_PAGEBITS(addr);
   140 	switch (addr) {
   141 		case 0x000000:
   142 		case 0x001000:
   143 		case 0x002000:
   144 		case 0x003000:
   145 		case 0x004000:
   146 		case 0x033000:
   147 		case 0x034000:
   148 		case 0x035000:
   149 			LOG("Addr %08X MapNew %04X Pagebit update -- ps0 %d, %02X => %02X => %02X", addr, MAPRAM_ADDR(addr), ps0_state, old_pagebits, new_pagebit1, new_pagebit2);
   150 		default:
   151 			break;
   152 	}
   153 }
   155 bool access_check_dma(void)
   156 {
   157 	// TODO FIXME BUGBUG Sanity check - Make sure DMAC is only accessing RAM addresses
   159 	// DMA access check -- make sure the page is mapped in
   160 	if (!(MAP_PAGEBITS(state.dma_address) & PAGE_BIT_PS0) && !(MAP_PAGEBITS(state.dma_address) & PAGE_BIT_PS1)) {
   161 		// DMA access to page which is not mapped in.
   162 		// Level 7 interrupt, page fault, DMA invoked
   163 		state.genstat = 0xABFF
   164 			| (state.dma_reading ? 0x4000 : 0)
   165 			| (state.pie ? 0x0400 : 0);
   167 		// XXX: Check all this stuff.
   168 		state.bsr0 = 0x3C00;
   169 		state.bsr0 |= (state.dma_address >> 16);
   170 		state.bsr1 = state.dma_address & 0xffff;
   172 		// Update page bits for this transfer
   173 		update_page_bits(state.dma_address, true, !state.dma_reading);
   175 		// XXX: is this right?
   176 		// Fire a Level 7 interrupt
   177 		/*if (state.ee)*/ m68k_set_irq(7);
   179 		LOG("BUS ERROR FROM DMA: genstat=%04X, bsr0=%04X, bsr1=%04X\n", state.genstat, state.bsr0, state.bsr1);
   180 		return false;
   181 	} else {
   182 		// No errors. Just update the page bits.
   183 		update_page_bits(state.dma_address, false, !state.dma_reading);
   184 		return true;
   185 	}
   186 }
   188 /**
   189  * Check memory access permissions for a CPU memory access.
   190  *
   191  * @param	addr	Virtual memory address being accessed (from CPU address bus).
   192  * @param	bits	Word size of this transfer (8, 16 or 32 bits).
   193  * @param	write	<i>true</i> if this is a write operation, <i>false</i> if it is a read operation.
   194  * @return	<i>true</i> if the access was denied and a level-7 interrupt and/or bus error raised.
   195  * 			<i>false</i> if the access was allowed.
   196  */
   197 bool access_check_cpu(uint32_t addr, int bits, bool write)
   198 {
   199 	bool supervisor = (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000);
   200 	bool fault = false;
   202 	// TODO FIXME BUGBUG? Do we need to check for supervisor access here?
   203 	if ((addr >= 0x000000) && (addr <= 0x3FFFFF) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS1) && !(MAP_PAGEBITS(addr) & PAGE_BIT_PS0)) {
   204 		// (A) Page Fault -- user access to page which is not mapped in
   205 		// Level 7 Interrupt, Bus Error, regs=PAGEFAULT
   206 		if (write) {
   207 			state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0);
   208 		} else {
   209 			state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0);
   210 		}
   211 		fault = true;
   212 	} else if (!supervisor && (addr >= 0x000000) && (addr <= 0x07FFFF)) {
   213 		// (B) User attempted to access the kernel
   214 		// Level 7 Interrupt, Bus Error, regs=KERNEL
   215 		if (write) {
   216 			// XXX: BUGBUG? Is this correct?
   217 			state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0);
   218 		} else {
   219 			state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0);
   220 		}
   221 		fault = true;
   222 	} else if (!supervisor && write && (addr >= 0x000000) && (addr <= 0x3FFFFF) && !(MAP_PAGEBITS(addr) & PAGE_BIT_WE)) {
   223 		// (C) User attempted to write to a page which is not write enabled
   224 		// Level 7 Interrupt, Bus Error, regs=WRITE_EN
   225 		if (write) {
   226 			// XXX: BUGBUG? Is this correct?
   227 			state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0);
   228 		} else {
   229 			state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0);
   230 		}
   231 		fault = true;
   232 	} else if (!supervisor && (addr >= 0x400000) && (addr <= 0xFFFFFF)) {
   233 		// (D) UIE - user I/O exception
   234 		// Bus Error only, regs=UIE
   235 		if (write) {
   236 			state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0);
   237 		} else {
   238 			state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0);
   239 		}
   240 		fault = true;
   241 	}
   243 	// Update the page bits first
   244 	update_page_bits(addr, fault, write);
   246 	if (fault) {
   247 		if (bits >= 16)
   248 			state.bsr0 = 0x7C00;
   249 		else
   250 			state.bsr0 = (addr & 1) ? 0x7E00 : 0x7D00;
   251 		// FIXME? Physical or virtual address here?
   252 		state.bsr0 |= (addr >> 16);
   253 		state.bsr1 = addr & 0xffff;
   255 		LOG("CPU Bus Error or L7Intr while %s, vaddr %08X, map %08X, pagebits 0x%02X bsr0=%04X bsr1=%04X genstat=%04X", 
   256 				write ? "writing" : "reading", addr,
   257 				MAPRAM_ADDR(addr & 0x3fffff),
   258 				MAP_PAGEBITS(addr & 0x3fffff),
   259 				state.bsr0, state.bsr1, state.genstat);
   261 		// FIXME? BUGBUG? Does EE disable one or both of these?
   262 		// /*if (state.ee)*/ m68k_set_irq(7);
   263 		/*if (state.ee)*/ m68k_pulse_bus_error();
   264 	}
   266 	return fault;
   267 }
   269 // Logging macros
   270 #define LOG_NOT_HANDLED_R(bits)															\
   271 	if (!handled) fprintf(stderr, "unhandled read%02d, addr=0x%08X\n", bits, address);
   273 #define LOG_NOT_HANDLED_W(bits)															\
   274 	if (!handled) fprintf(stderr, "unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
   276 /********************************************************
   277  * I/O read/write functions
   278  ********************************************************/
   280 /**
   281  * Issue a warning if a read operation is made with an invalid size
   282  */
   283 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
   284 {
   285 	assert((bits == 8) || (bits == 16) || (bits == 32));
   286 	if ((bits & allowed) == 0) {
   287 		LOG("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
   288 	}
   289 }
   291 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
   292 {
   293 	ENFORCE_SIZE(bits, address, true, allowed, regname);
   294 }
   296 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
   297 {
   298 	ENFORCE_SIZE(bits, address, false, allowed, regname);
   299 }
   301 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
   302 {
   303 	bool handled = false;
   305 	if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   306 		// I/O register space, zone A
   307 		switch (address & 0x0F0000) {
   308 			case 0x010000:				// General Status Register
   309 				if (bits == 16)
   310 					state.genstat = (data & 0xffff);
   311 				else if (bits == 8) {
   312 					if (address & 0)
   313 						state.genstat = data;
   314 					else
   315 						state.genstat = data << 8;
   316 				}
   317 				handled = true;
   318 				break;
   319 			case 0x030000:				// Bus Status Register 0
   320 				break;
   321 			case 0x040000:				// Bus Status Register 1
   322 				break;
   323 			case 0x050000:				// Phone status
   324 				break;
   325 			case 0x060000:				// DMA Count
   326 				ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
   327 				state.dma_count = (data & 0x3FFF);
   328 				state.idmarw = ((data & 0x4000) == 0x4000);
   329 				state.dmaen = ((data & 0x8000) == 0x8000);
   330 				// This handles the "dummy DMA transfer" mentioned in the docs
   331 				// disabled because it causes the floppy test to fail
   332 #if 0
   333 				if (!state.idmarw){
   334 					if (access_check_dma(true)){
   335 						uint32_t newAddr = mapAddr(state.dma_address, true);
   336 						// RAM access
   337 						if (newAddr <= 0x1fffff)
   338 							WR16(state.base_ram, newAddr, state.base_ram_size - 1, 0xFF);
   339 						else if (address <= 0x3FFFFF)
   340 							WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, 0xFF);
   341 					}
   342 				}
   343 #endif
   344 				state.dma_count++;
   345 				handled = true;
   346 				break;
   347 			case 0x070000:				// Line Printer Status Register
   348 				break;
   349 			case 0x080000:				// Real Time Clock
   350 				LOGS("REAL TIME CLOCK WRITE");
   351 				break;
   352 			case 0x090000:				// Phone registers
   353 				switch (address & 0x0FF000) {
   354 					case 0x090000:		// Handset relay
   355 					case 0x098000:
   356 						break;
   357 					case 0x091000:		// Line select 2
   358 					case 0x099000:
   359 						break;
   360 					case 0x092000:		// Hook relay 1
   361 					case 0x09A000:
   362 						break;
   363 					case 0x093000:		// Hook relay 2
   364 					case 0x09B000:
   365 						break;
   366 					case 0x094000:		// Line 1 hold
   367 					case 0x09C000:
   368 						break;
   369 					case 0x095000:		// Line 2 hold
   370 					case 0x09D000:
   371 						break;
   372 					case 0x096000:		// Line 1 A-lead
   373 					case 0x09E000:
   374 						break;
   375 					case 0x097000:		// Line 2 A-lead
   376 					case 0x09F000:
   377 						break;
   378 				}
   379 				break;
   380 			case 0x0A0000:				// Miscellaneous Control Register
   381 				ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
   382 				// TODO: handle the ctrl bits properly
   383 				if (data & 0x8000){
   384 					state.timer_enabled = 1;
   385 				}else{
   386 					state.timer_enabled = 0;
   387 					state.timer_asserted = 0;
   388 				}
   389 				state.dma_reading = (data & 0x4000);
   390 				if (state.leds != ((~data & 0xF00) >> 8)) {
   391 					state.leds = (~data & 0xF00) >> 8;
   392 #ifdef SHOW_LEDS
   393 					printf("LEDs: %s %s %s %s\n",
   394 							(state.leds & 8) ? "R" : "-",
   395 							(state.leds & 4) ? "G" : "-",
   396 							(state.leds & 2) ? "Y" : "-",
   397 							(state.leds & 1) ? "R" : "-");
   398 #endif
   399 				}
   400 				handled = true;
   401 				break;
   402 			case 0x0B0000:				// TM/DIALWR
   403 				break;
   404 			case 0x0C0000:				// Clear Status Register
   405 				state.genstat = 0xFFFF;
   406 				state.bsr0 = 0xFFFF;
   407 				state.bsr1 = 0xFFFF;
   408 				handled = true;
   409 				break;
   410 			case 0x0D0000:				// DMA Address Register
   411 				if (address & 0x004000) {
   412 					// A14 high -- set most significant bits
   413 					state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
   414 				} else {
   415 					// A14 low -- set least significant bits
   416 					state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
   417 				}
   418 				handled = true;
   419 				break;
   420 			case 0x0E0000:				// Disk Control Register
   421 				{
   422 					bool fd_selected;
   423 					bool hd_selected;
   424 					ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
   425 					// B7 = FDD controller reset
   426 					if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
   427 					// B6 = drive 0 select
   428 					fd_selected = (data & 0x40) != 0;
   429 					// B5 = motor enable -- TODO
   430 					// B4 = HDD controller reset
   431 					if ((data & 0x10) == 0) wd2010_reset(&state.hdc_ctx);
   432 					// B3 = HDD0 select
   433 					hd_selected = (data & 0x08) != 0;
   434 					// B2,1,0 = HDD0 head select -- TODO?
   435 					if (hd_selected && !state.hd_selected){
   436 						state.fd_selected = false;
   437 						state.hd_selected = true;
   438 					}else if (fd_selected && !state.fd_selected){
   439 						state.hd_selected = false;
   440 						state.fd_selected = true;
   441 					}
   442 					handled = true;
   443 					break;
   444 				}
   445 			case 0x0F0000:				// Line Printer Data Register
   446 				break;
   447 		}
   448 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   449 		// I/O register space, zone B
   450 		switch (address & 0xF00000) {
   451 			case 0xC00000:				// Expansion slots
   452 			case 0xD00000:
   453 				switch (address & 0xFC0000) {
   454 					case 0xC00000:		// Expansion slot 0
   455 					case 0xC40000:		// Expansion slot 1
   456 					case 0xC80000:		// Expansion slot 2
   457 					case 0xCC0000:		// Expansion slot 3
   458 					case 0xD00000:		// Expansion slot 4
   459 					case 0xD40000:		// Expansion slot 5
   460 					case 0xD80000:		// Expansion slot 6
   461 					case 0xDC0000:		// Expansion slot 7
   462 						fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
   463 						handled = true;
   464 						break;
   465 				}
   466 				break;
   467 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   468 			case 0xF00000:
   469 				switch (address & 0x070000) {
   470 					case 0x000000:		// [ef][08]xxxx ==> WD2010 hard disc controller
   471 						wd2010_write_reg(&state.hdc_ctx, (address >> 1) & 7, data);
   472 						handled = true;
   473 						break;
   474 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   475 						/*ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");*/
   476 						wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
   477 						handled = true;
   478 						break;
   479 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   480 						// MCR2 - UNIX PC Rev. P5.1 HDD head select b3 and potential HDD#2 select
   481 						wd2010_write_reg(&state.hdc_ctx, UNIXPC_REG_MCR2, data);
   482 						handled = true;
   483 						break;
   484 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   485 						LOGS("REAL TIME CLOCK DATA WRITE");
   486 						break;
   487 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   488 						switch (address & 0x077000) {
   489 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   490 								// Error Enable. If =0, Level7 intrs and bus errors are masked.
   491 								ENFORCE_SIZE_W(bits, address, 16, "EE");
   492 								state.ee = ((data & 0x8000) == 0x8000);
   493 								handled = true;
   494 								break;
   495 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   496 								ENFORCE_SIZE_W(bits, address, 16, "PIE");
   497 								state.pie = ((data & 0x8000) == 0x8000);
   498 								handled = true;
   499 								break;
   500 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   501 								break;
   502 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   503 								ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
   504 								state.romlmap = ((data & 0x8000) == 0x8000);
   505 								handled = true;
   506 								break;
   507 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   508 								ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
   509 								break;
   510 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   511 								ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
   512 								break;
   513 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   514 								ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
   515 								break;
   516 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   517 								ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
   518 								break;
   519 						}
   520 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   521 						break;
   522 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   523 						switch (address & 0x07F000) {
   524 							default:
   525 								break;
   526 						}
   527 						break;
   528 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   529 						// TODO: figure out which sizes are valid (probably just 8 and 16)
   530 						// ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER");
   531 						if (bits == 8) {
   532 #ifdef LOG_KEYBOARD_WRITES
   533 							LOG("KBD WR %02X => %02X\n", (address >> 1) & 3, data);
   534 #endif
   535 							keyboard_write(&state.kbd, (address >> 1) & 3, data);
   536 							handled = true;
   537 						} else if (bits == 16) {
   538 #ifdef LOG_KEYBOARD_WRITES
   539 							LOG("KBD WR %02X => %04X\n", (address >> 1) & 3, data);
   540 #endif
   541 							keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8);
   542 							handled = true;
   543 						}
   544 						break;
   545 				}
   546 		}
   547 	}
   549 	LOG_NOT_HANDLED_W(bits);
   550 }/*}}}*/
   552 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
   553 {
   554 	bool handled = false;
   555 	uint32_t data = EMPTY & 0xFFFFFFFF;
   557 	if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   558 		// I/O register space, zone A
   559 		switch (address & 0x0F0000) {
   560 			case 0x010000:				// General Status Register
   561 				/* ENFORCE_SIZE_R(bits, address, 16, "GENSTAT"); */
   562 				if (bits == 32) {
   563 					return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
   564 				} else if (bits == 16) {
   565 					return (uint16_t)state.genstat;
   566 				} else {
   567 					return (uint8_t)(state.genstat & 0xff);
   568 				}
   569 				break;
   570 			case 0x030000:				// Bus Status Register 0
   571 				ENFORCE_SIZE_R(bits, address, 16, "BSR0");
   572 				return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
   573 				break;
   574 			case 0x040000:				// Bus Status Register 1
   575 				ENFORCE_SIZE_R(bits, address, 16, "BSR1");
   576 				return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
   577 				break;
   578 			case 0x050000:				// Phone status
   579 				ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
   580 				break;
   581 			case 0x060000:				// DMA Count
   582 				// TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
   583 				// Bit 14 is always unused, so leave it set
   584 				ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
   585 				return (state.dma_count & 0x3fff) | 0xC000;
   586 				break;
   587 			case 0x070000:				// Line Printer Status Register
   588 				data = 0x00120012;	// no parity error, no line printer error, no irqs from FDD or HDD
   589 				data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0;
   590 				data |= wd2010_get_irq(&state.hdc_ctx) ? 0x00040004 : 0;
   591 				return data;
   592 				break;
   593 			case 0x080000:				// Real Time Clock
   594 				LOGS("REAL TIME CLOCK READ");
   595 				break;
   596 			case 0x090000:				// Phone registers
   597 				switch (address & 0x0FF000) {
   598 					case 0x090000:		// Handset relay
   599 					case 0x098000:
   600 						break;
   601 					case 0x091000:		// Line select 2
   602 					case 0x099000:
   603 						break;
   604 					case 0x092000:		// Hook relay 1
   605 					case 0x09A000:
   606 						break;
   607 					case 0x093000:		// Hook relay 2
   608 					case 0x09B000:
   609 						break;
   610 					case 0x094000:		// Line 1 hold
   611 					case 0x09C000:
   612 						break;
   613 					case 0x095000:		// Line 2 hold
   614 					case 0x09D000:
   615 						break;
   616 					case 0x096000:		// Line 1 A-lead
   617 					case 0x09E000:
   618 						break;
   619 					case 0x097000:		// Line 2 A-lead
   620 					case 0x09F000:
   621 						break;
   622 				}
   623 				break;
   624 			case 0x0A0000:				// Miscellaneous Control Register -- write only!
   625 				handled = true;
   626 				break;
   627 			case 0x0B0000:				// TM/DIALWR
   628 				break;
   629 			case 0x0C0000:				// Clear Status Register -- write only!
   630 				handled = true;
   631 				break;
   632 			case 0x0D0000:				// DMA Address Register
   633 				break;
   634 			case 0x0E0000:				// Disk Control Register
   635 				break;
   636 			case 0x0F0000:				// Line Printer Data Register
   637 				break;
   638 		}
   639 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   640 		// I/O register space, zone B
   641 		switch (address & 0xF00000) {
   642 			case 0xC00000:				// Expansion slots
   643 			case 0xD00000:
   644 				switch (address & 0xFC0000) {
   645 					case 0xC00000:		// Expansion slot 0
   646 					case 0xC40000:		// Expansion slot 1
   647 					case 0xC80000:		// Expansion slot 2
   648 					case 0xCC0000:		// Expansion slot 3
   649 					case 0xD00000:		// Expansion slot 4
   650 					case 0xD40000:		// Expansion slot 5
   651 					case 0xD80000:		// Expansion slot 6
   652 					case 0xDC0000:		// Expansion slot 7
   653 						fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
   654 						handled = true;
   655 						break;
   656 				}
   657 				break;
   658 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   659 			case 0xF00000:
   660 				switch (address & 0x070000) {
   661 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   662 						return (wd2010_read_reg(&state.hdc_ctx, (address >> 1) & 7));
   664 						break;
   665 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   666 						/*ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");*/
   667 						return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
   668 						break;
   669 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   670 						break;
   671 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   672 						LOGS("REAL TIME CLOCK DATA READ");
   673 						break;
   674 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   675 						switch (address & 0x077000) {
   676 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   677 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   678 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   679 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   680 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   681 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   682 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   683 								// All write-only registers... TODO: bus error?
   684 								handled = true;
   685 								break;
   686 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
   687 								break;
   688 						}
   689 						break;
   690 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   691 						break;
   692 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   693 						switch (address & 0x07F000) {
   694 							default:
   695 								break;
   696 						}
   697 						break;
   698 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   699 						// TODO: figure out which sizes are valid (probably just 8 and 16)
   700 						//ENFORCE_SIZE_R(bits, address, 16, "KEYBOARD CONTROLLER");
   701 						{
   702 							if (bits == 8) {
   703 								return keyboard_read(&state.kbd, (address >> 1) & 3);
   704 							} else {
   705 								return keyboard_read(&state.kbd, (address >> 1) & 3) << 8;
   706 							}
   707 							return data;
   708 						}
   709 						break;
   710 				}
   711 		}
   712 	}
   714 	LOG_NOT_HANDLED_R(bits);
   716 	return data;
   717 }/*}}}*/
   720 /********************************************************
   721  * m68k memory read/write support functions for Musashi
   722  ********************************************************/
   724 /**
   725  * @brief Read M68K memory, 32-bit
   726  */
   727 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
   728 {
   729 	uint32_t data = EMPTY & 0xFFFFFFFF;
   731 	// If ROMLMAP is set, force system to access ROM
   732 	if (!state.romlmap)
   733 		address |= 0x800000;
   735 	// Check access permissions
   736 	ACCESS_CHECK_RD(address, 32);
   738 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   739 		// ROM access
   740 		return RD32(state.rom, address, ROM_SIZE - 1);
   741 	} else if (address <= 0x3fffff) {
   742 		// RAM access
   743 		uint32_t newAddr = MAP_ADDR(address);
   745 		if (newAddr <= 0x1fffff) {
   746 			// Base memory wraps around
   747 			return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
   748 		} else {
   749 			if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
   750 				return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   751 			else
   752 				return EMPTY & 0xffffffff;
   753 		}
   754 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   755 		// I/O register space, zone A
   756 		switch (address & 0x0F0000) {
   757 			case 0x000000:				// Map RAM access
   758 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
   759 				return RD32(state.map, address, 0x7FF);
   760 				break;
   761 			case 0x020000:				// Video RAM
   762 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
   763 				return RD32(state.vram, address, 0x7FFF);
   764 				break;
   765 			default:
   766 				return IoRead(address, 32);
   767 		}
   768 	} else {
   769 		return IoRead(address, 32);
   770 	}
   772 	return data;
   773 }/*}}}*/
   775 /**
   776  * @brief Read M68K memory, 16-bit
   777  */
   778 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
   779 {
   780 	uint16_t data = EMPTY & 0xFFFF;
   782 	// If ROMLMAP is set, force system to access ROM
   783 	if (!state.romlmap)
   784 		address |= 0x800000;
   786 	// Check access permissions
   787 	ACCESS_CHECK_RD(address, 16);
   789 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   790 		// ROM access
   791 		data = RD16(state.rom, address, ROM_SIZE - 1);
   792 	} else if (address <= 0x3fffff) {
   793 		// RAM access
   794 		uint32_t newAddr = MAP_ADDR(address);
   796 		if (newAddr <= 0x1fffff) {
   797 			// Base memory wraps around
   798 			return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
   799 		} else {
   800 			if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
   801 				return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   802 			else
   803 				return EMPTY & 0xffff;
   804 		}
   805 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   806 		// I/O register space, zone A
   807 		switch (address & 0x0F0000) {
   808 			case 0x000000:				// Map RAM access
   809 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
   810 				data = RD16(state.map, address, 0x7FF);
   811 				break;
   812 			case 0x020000:				// Video RAM
   813 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
   814 				data = RD16(state.vram, address, 0x7FFF);
   815 				break;
   816 			default:
   817 				data = IoRead(address, 16);
   818 		}
   819 	} else {
   820 		data = IoRead(address, 16);
   821 	}
   823 	return data;
   824 }/*}}}*/
   826 /**
   827  * @brief Read M68K memory, 8-bit
   828  */
   829 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
   830 {
   831 	uint8_t data = EMPTY & 0xFF;
   833 	// If ROMLMAP is set, force system to access ROM
   834 	if (!state.romlmap)
   835 		address |= 0x800000;
   837 	// Check access permissions
   838 	ACCESS_CHECK_RD(address, 8);
   840 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   841 		// ROM access
   842 		data = RD8(state.rom, address, ROM_SIZE - 1);
   843 	} else if (address <= 0x3fffff) {
   844 		// RAM access
   845 		uint32_t newAddr = MAP_ADDR(address);
   847 		if (newAddr <= 0x1fffff) {
   848 			// Base memory wraps around
   849 			return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
   850 		} else {
   851 			if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
   852 				return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   853 			else
   854 				return EMPTY & 0xff;
   855 		}
   856 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   857 		// I/O register space, zone A
   858 		switch (address & 0x0F0000) {
   859 			case 0x000000:				// Map RAM access
   860 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
   861 				data = RD8(state.map, address, 0x7FF);
   862 				break;
   863 			case 0x020000:				// Video RAM
   864 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
   865 				data = RD8(state.vram, address, 0x7FFF);
   866 				break;
   867 			default:
   868 				data = IoRead(address, 8);
   869 		}
   870 	} else {
   871 		data = IoRead(address, 8);
   872 	}
   874 	return data;
   875 }/*}}}*/
   877 /**
   878  * @brief Write M68K memory, 32-bit
   879  */
   880 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
   881 {
   882 	// If ROMLMAP is set, force system to access ROM
   883 	if (!state.romlmap)
   884 		address |= 0x800000;
   886 	// Check access permissions
   887 	ACCESS_CHECK_WR(address, 32);
   889 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   890 		// ROM access
   891 	} else if (address <= 0x3FFFFF) {
   892 		// RAM access
   893 		uint32_t newAddr = MAP_ADDR(address);
   895 		if (newAddr <= 0x1fffff) {
   896 			if (newAddr < state.base_ram_size) {
   897 				WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
   898 			}
   899 		} else {
   900 			if ((newAddr - 0x200000) < state.exp_ram_size) {
   901 				WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   902 			}
   903 		}
   904 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   905 		// I/O register space, zone A
   906 		switch (address & 0x0F0000) {
   907 			case 0x000000:				// Map RAM access
   908 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X\n", address);
   909 				WR32(state.map, address, 0x7FF, value);
   910 				break;
   911 			case 0x020000:				// Video RAM
   912 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X\n", address);
   913 				WR32(state.vram, address, 0x7FFF, value);
   914 				break;
   915 			default:
   916 				IoWrite(address, value, 32);
   917 		}
   918 	} else {
   919 		IoWrite(address, value, 32);
   920 	}
   921 }/*}}}*/
   923 /**
   924  * @brief Write M68K memory, 16-bit
   925  */
   926 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
   927 {
   928 	// If ROMLMAP is set, force system to access ROM
   929 	if (!state.romlmap)
   930 		address |= 0x800000;
   932 	// Check access permissions
   933 	ACCESS_CHECK_WR(address, 16);
   935 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   936 		// ROM access
   937 	} else if (address <= 0x3FFFFF) {
   938 		// RAM access
   939 		uint32_t newAddr = MAP_ADDR(address);
   941 		if (newAddr <= 0x1fffff) {
   942 			if (newAddr < state.base_ram_size) {
   943 				WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
   944 			}
   945 		} else {
   946 			if ((newAddr - 0x200000) < state.exp_ram_size) {
   947 				WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   948 			}
   949 		}
   950 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   951 		// I/O register space, zone A
   952 		switch (address & 0x0F0000) {
   953 			case 0x000000:				// Map RAM access
   954 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   955 				WR16(state.map, address, 0x7FF, value);
   956 				break;
   957 			case 0x020000:				// Video RAM
   958 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   959 				WR16(state.vram, address, 0x7FFF, value);
   960 				break;
   961 			default:
   962 				IoWrite(address, value, 16);
   963 		}
   964 	} else {
   965 		IoWrite(address, value, 16);
   966 	}
   967 }/*}}}*/
   969 /**
   970  * @brief Write M68K memory, 8-bit
   971  */
   972 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
   973 {
   974 	// If ROMLMAP is set, force system to access ROM
   975 	if (!state.romlmap)
   976 		address |= 0x800000;
   978 	// Check access permissions
   979 	ACCESS_CHECK_WR(address, 8);
   981 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   982 		// ROM access (read only!)
   983 	} else if (address <= 0x3FFFFF) {
   984 		// RAM access
   985 		uint32_t newAddr = MAP_ADDR(address);
   987 		if (newAddr <= 0x1fffff) {
   988 			if (newAddr < state.base_ram_size) {
   989 				WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
   990 			}
   991 		} else {
   992 			if ((newAddr - 0x200000) < state.exp_ram_size) {
   993 				WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   994 			}
   995 		}
   996 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   997 		// I/O register space, zone A
   998 		switch (address & 0x0F0000) {
   999 			case 0x000000:				// Map RAM access
  1000 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
  1001 				WR8(state.map, address, 0x7FF, value);
  1002 				break;
  1003 			case 0x020000:				// Video RAM
  1004 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
  1005 				WR8(state.vram, address, 0x7FFF, value);
  1006 				break;
  1007 			default:
  1008 				IoWrite(address, value, 8);
  1010 	} else {
  1011 		IoWrite(address, value, 8);
  1013 }/*}}}*/
  1016 // for the disassembler
  1017 uint32_t m68k_read_disassembler_32(uint32_t addr)
  1019 	if (addr < 0x400000) {
  1020 		// XXX FIXME BUGBUG update this to use the new mapper macros!
  1021 		uint16_t page = (addr >> 12) & 0x3FF;
  1022 		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
  1023 		uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
  1024 		if (newAddr <= 0x1fffff) {
  1025 			if (newAddr >= state.base_ram_size)
  1026 				return EMPTY;
  1027 			else
  1028 				return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
  1029 		} else {
  1030 			if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
  1031 				return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
  1032 			else
  1033 				return EMPTY;
  1035 	} else {
  1036 		LOG("WARNING: Disassembler RD32 out of range 0x%08X\n", addr);
  1037 		return EMPTY;
  1041 uint32_t m68k_read_disassembler_16(uint32_t addr)
  1043 	if (addr < 0x400000) {
  1044 		uint16_t page = (addr >> 12) & 0x3FF;
  1045 		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
  1046 		uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
  1047 		if (newAddr <= 0x1fffff) {
  1048 			if (newAddr >= state.base_ram_size)
  1049 				return EMPTY & 0xffff;
  1050 			else
  1051 				return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
  1052 		} else {
  1053 			if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
  1054 				return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
  1055 			else
  1056 				return EMPTY & 0xffff;
  1058 	} else {
  1059 		LOG("WARNING: Disassembler RD16 out of range 0x%08X\n", addr);
  1060 		return EMPTY & 0xffff;
  1064 uint32_t m68k_read_disassembler_8 (uint32_t addr)
  1066 	if (addr < 0x400000) {
  1067 		uint16_t page = (addr >> 12) & 0x3FF;
  1068 		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
  1069 		uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
  1070 		if (newAddr <= 0x1fffff) {
  1071 			if (newAddr >= state.base_ram_size)
  1072 				return EMPTY & 0xff;
  1073 			else
  1074 				return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
  1075 		} else {
  1076 			if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
  1077 				return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
  1078 			else
  1079 				return EMPTY & 0xff;
  1081 	} else {
  1082 		LOG("WARNING: Disassembler RD8 out of range 0x%08X\n", addr);
  1083 		return EMPTY & 0xff;