Sun, 05 Dec 2010 16:20:00 +0000
add preliminary WD279x emulation to core
1 #include <stdio.h>
2 #include <stdlib.h>
3 #include <stdint.h>
4 #include <stdbool.h>
5 #include "musashi/m68k.h"
6 #include "state.h"
7 #include "memory.h"
9 /******************
10 * Memory mapping
11 ******************/
13 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
15 uint32_t mapAddr(uint32_t addr, bool writing)
16 {
17 if (addr < 0x400000) {
18 // RAM access. Check against the Map RAM
19 // Start by getting the original page address
20 uint16_t page = (addr >> 12) & 0x3FF;
22 // Look it up in the map RAM and get the physical page address
23 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
25 // Update the Page Status bits
26 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
27 if (pagebits != 0) {
28 if (writing)
29 state.map[page*2] |= 0x60; // Page written to (dirty)
30 else
31 state.map[page*2] |= 0x40; // Page accessed but not written
32 }
34 // Return the address with the new physical page spliced in
35 return (new_page_addr << 12) + (addr & 0xFFF);
36 } else {
37 // I/O, VRAM or MapRAM space; no mapping is performed or required
38 // TODO: assert here?
39 return addr;
40 }
41 }
43 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)
44 {
45 // Are we in Supervisor mode?
46 if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
47 // Yes. We can do anything we like.
48 return MEM_ALLOWED;
50 // If we're here, then we must be in User mode.
51 // Check that the user didn't access memory outside of the RAM area
52 if (addr >= 0x400000)
53 return MEM_UIE;
55 // This leaves us with Page Fault checking. Get the page bits for this page.
56 uint16_t page = (addr >> 12) & 0x3FF;
57 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
59 // Check page is present
60 if ((pagebits & 0x03) == 0)
61 return MEM_PAGEFAULT;
63 // User attempt to access the kernel
64 // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
65 if (((addr >> 19) & 0x0F) == 0)
66 return MEM_KERNEL;
68 // Check page is write enabled
69 if ((pagebits & 0x04) == 0)
70 return MEM_PAGE_NO_WE;
72 // Page access allowed.
73 return MEM_ALLOWED;
74 }
76 #undef MAPRAM
79 /********************************************************
80 * m68k memory read/write support functions for Musashi
81 ********************************************************/
83 /**
84 * @brief Check memory access permissions for a write operation.
85 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
86 * gcc throws warnings when you have a return-with-value in a void
87 * function, even if the return-with-value is completely unreachable.
88 * Similarly it doesn't like it if you have a return without a value
89 * in a non-void function, even if it's impossible to ever reach the
90 * return-with-no-value. UGH!
91 */
92 #define ACCESS_CHECK_WR(address, bits) do { \
93 bool fault = false; \
94 /* MEM_STATUS st; */ \
95 switch (checkMemoryAccess(address, true)) { \
96 case MEM_ALLOWED: \
97 /* Access allowed */ \
98 break; \
99 case MEM_PAGEFAULT: \
100 /* Page fault */ \
101 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0); \
102 fault = true; \
103 break; \
104 case MEM_UIE: \
105 /* User access to memory above 4MB */ \
106 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0); \
107 fault = true; \
108 break; \
109 case MEM_KERNEL: \
110 case MEM_PAGE_NO_WE: \
111 /* kernel access or page not write enabled */ \
112 /* TODO: which regs need setting? */ \
113 fault = true; \
114 break; \
115 } \
116 \
117 if (fault) { \
118 if (bits >= 16) \
119 state.bsr0 = 0x7F00; \
120 else \
121 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
122 state.bsr0 |= (address >> 16); \
123 state.bsr1 = address & 0xffff; \
124 printf("ERR: BusError WR\n"); \
125 m68k_pulse_bus_error(); \
126 return; \
127 } \
128 } while (false)
130 /**
131 * @brief Check memory access permissions for a read operation.
132 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
133 * gcc throws warnings when you have a return-with-value in a void
134 * function, even if the return-with-value is completely unreachable.
135 * Similarly it doesn't like it if you have a return without a value
136 * in a non-void function, even if it's impossible to ever reach the
137 * return-with-no-value. UGH!
138 */
139 #define ACCESS_CHECK_RD(address, bits) do { \
140 bool fault = false; \
141 /* MEM_STATUS st; */ \
142 switch (checkMemoryAccess(address, false)) { \
143 case MEM_ALLOWED: \
144 /* Access allowed */ \
145 break; \
146 case MEM_PAGEFAULT: \
147 /* Page fault */ \
148 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0); \
149 fault = true; \
150 break; \
151 case MEM_UIE: \
152 /* User access to memory above 4MB */ \
153 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0); \
154 fault = true; \
155 break; \
156 case MEM_KERNEL: \
157 case MEM_PAGE_NO_WE: \
158 /* kernel access or page not write enabled */ \
159 /* TODO: which regs need setting? */ \
160 fault = true; \
161 break; \
162 } \
163 \
164 if (fault) { \
165 if (bits >= 16) \
166 state.bsr0 = 0x7F00; \
167 else \
168 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
169 state.bsr0 |= (address >> 16); \
170 state.bsr1 = address & 0xffff; \
171 printf("ERR: BusError RD\n"); \
172 m68k_pulse_bus_error(); \
173 return 0xFFFFFFFF; \
174 } \
175 } while (false)
177 // Logging macros
178 #define LOG_NOT_HANDLED_R(bits) \
179 do { \
180 if (!handled) \
181 printf("unhandled read%02d, addr=0x%08X\n", bits, address); \
182 } while (0);
184 #define LOG_NOT_HANDLED_W(bits) \
185 do { \
186 if (!handled) \
187 printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, value); \
188 } while (0);
190 /**
191 * @brief Read M68K memory, 32-bit
192 */
193 uint32_t m68k_read_memory_32(uint32_t address)
194 {
195 uint32_t data = 0xFFFFFFFF;
196 bool handled = false;
198 // If ROMLMAP is set, force system to access ROM
199 if (!state.romlmap)
200 address |= 0x800000;
202 // Check access permissions
203 ACCESS_CHECK_RD(address, 32);
205 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
206 // ROM access
207 data = RD32(state.rom, address, ROM_SIZE - 1);
208 handled = true;
209 } else if (address <= (state.ram_size - 1)) {
210 // RAM access
211 data = RD32(state.ram, mapAddr(address, false), state.ram_size - 1);
212 handled = true;
213 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
214 // I/O register space, zone A
215 switch (address & 0x0F0000) {
216 case 0x000000: // Map RAM access
217 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
218 data = RD32(state.map, address, 0x7FF);
219 handled = true;
220 break;
221 case 0x010000: // General Status Register
222 data = ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
223 handled = true;
224 break;
225 case 0x020000: // Video RAM
226 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
227 data = RD32(state.vram, address, 0x7FFF);
228 handled = true;
229 break;
230 case 0x030000: // Bus Status Register 0
231 data = ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
232 handled = true;
233 break;
234 case 0x040000: // Bus Status Register 1
235 data = ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
236 handled = true;
237 break;
238 case 0x050000: // Phone status
239 break;
240 case 0x060000: // DMA Count
241 break;
242 case 0x070000: // Line Printer Status Register
243 break;
244 case 0x080000: // Real Time Clock
245 break;
246 case 0x090000: // Phone registers
247 switch (address & 0x0FF000) {
248 case 0x090000: // Handset relay
249 case 0x098000:
250 break;
251 case 0x091000: // Line select 2
252 case 0x099000:
253 break;
254 case 0x092000: // Hook relay 1
255 case 0x09A000:
256 break;
257 case 0x093000: // Hook relay 2
258 case 0x09B000:
259 break;
260 case 0x094000: // Line 1 hold
261 case 0x09C000:
262 break;
263 case 0x095000: // Line 2 hold
264 case 0x09D000:
265 break;
266 case 0x096000: // Line 1 A-lead
267 case 0x09E000:
268 break;
269 case 0x097000: // Line 2 A-lead
270 case 0x09F000:
271 break;
272 }
273 break;
274 case 0x0A0000: // Miscellaneous Control Register -- write only!
275 handled = true;
276 break;
277 case 0x0B0000: // TM/DIALWR
278 break;
279 case 0x0C0000: // Clear Status Register -- write only!
280 handled = true;
281 break;
282 case 0x0D0000: // DMA Address Register
283 break;
284 case 0x0E0000: // Disk Control Register
285 break;
286 case 0x0F0000: // Line Printer Data Register
287 break;
288 }
289 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
290 // I/O register space, zone B
291 switch (address & 0xF00000) {
292 case 0xC00000: // Expansion slots
293 case 0xD00000:
294 switch (address & 0xFC0000) {
295 case 0xC00000: // Expansion slot 0
296 case 0xC40000: // Expansion slot 1
297 case 0xC80000: // Expansion slot 2
298 case 0xCC0000: // Expansion slot 3
299 case 0xD00000: // Expansion slot 4
300 case 0xD40000: // Expansion slot 5
301 case 0xD80000: // Expansion slot 6
302 case 0xDC0000: // Expansion slot 7
303 fprintf(stderr, "NOTE: RD32 from expansion card space, addr=0x%08X\n", address);
304 break;
305 }
306 break;
307 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
308 case 0xF00000:
309 switch (address & 0x070000) {
310 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
311 break;
312 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
313 data = wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
314 printf("WD279X: rd %02X ==> %02X\n", (address >> 1) & 3, data);
315 handled = true;
316 break;
317 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
318 break;
319 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
320 break;
321 case 0x040000: // [ef][4c]xxxx ==> General Control Register
322 switch (address & 0x077000) {
323 case 0x040000: // [ef][4c][08]xxx ==> EE
324 case 0x041000: // [ef][4c][19]xxx ==> PIE
325 case 0x042000: // [ef][4c][2A]xxx ==> BP
326 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
327 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
328 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
329 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
330 // All write-only registers... TODO: bus error?
331 handled = true;
332 break;
333 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
334 break;
335 }
336 break;
337 case 0x050000: // [ef][5d]xxxx ==> 8274
338 break;
339 case 0x060000: // [ef][6e]xxxx ==> Control regs
340 switch (address & 0x07F000) {
341 default:
342 break;
343 }
344 break;
345 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
346 break;
347 }
348 }
349 }
351 LOG_NOT_HANDLED_R(32);
352 return data;
353 }
355 /**
356 * @brief Read M68K memory, 16-bit
357 */
358 uint32_t m68k_read_memory_16(uint32_t address)
359 {
360 uint16_t data = 0xFFFF;
361 bool handled = false;
363 // If ROMLMAP is set, force system to access ROM
364 if (!state.romlmap)
365 address |= 0x800000;
367 // Check access permissions
368 ACCESS_CHECK_RD(address, 16);
370 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
371 // ROM access
372 data = RD16(state.rom, address, ROM_SIZE - 1);
373 handled = true;
374 } else if (address <= (state.ram_size - 1)) {
375 // RAM access
376 data = RD16(state.ram, mapAddr(address, false), state.ram_size - 1);
377 handled = true;
378 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
379 // I/O register space, zone A
380 switch (address & 0x0F0000) {
381 case 0x000000: // Map RAM access
382 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
383 data = RD16(state.map, address, 0x7FF);
384 handled = true;
385 break;
386 case 0x010000: // General Status Register
387 data = state.genstat;
388 handled = true;
389 break;
390 case 0x020000: // Video RAM
391 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
392 data = RD16(state.vram, address, 0x7FFF);
393 handled = true;
394 break;
395 case 0x030000: // Bus Status Register 0
396 data = state.bsr0;
397 handled = true;
398 break;
399 case 0x040000: // Bus Status Register 1
400 data = state.bsr1;
401 handled = true;
402 break;
403 case 0x050000: // Phone status
404 break;
405 case 0x060000: // DMA Count
406 break;
407 case 0x070000: // Line Printer Status Register
408 break;
409 case 0x080000: // Real Time Clock
410 break;
411 case 0x090000: // Phone registers
412 switch (address & 0x0FF000) {
413 case 0x090000: // Handset relay
414 case 0x098000:
415 break;
416 case 0x091000: // Line select 2
417 case 0x099000:
418 break;
419 case 0x092000: // Hook relay 1
420 case 0x09A000:
421 break;
422 case 0x093000: // Hook relay 2
423 case 0x09B000:
424 break;
425 case 0x094000: // Line 1 hold
426 case 0x09C000:
427 break;
428 case 0x095000: // Line 2 hold
429 case 0x09D000:
430 break;
431 case 0x096000: // Line 1 A-lead
432 case 0x09E000:
433 break;
434 case 0x097000: // Line 2 A-lead
435 case 0x09F000:
436 break;
437 }
438 break;
439 case 0x0A0000: // Miscellaneous Control Register -- write only!
440 handled = true;
441 break;
442 case 0x0B0000: // TM/DIALWR
443 break;
444 case 0x0C0000: // Clear Status Register -- write only!
445 handled = true;
446 break;
447 case 0x0D0000: // DMA Address Register
448 break;
449 case 0x0E0000: // Disk Control Register
450 break;
451 case 0x0F0000: // Line Printer Data Register
452 break;
453 }
454 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
455 // I/O register space, zone B
456 switch (address & 0xF00000) {
457 case 0xC00000: // Expansion slots
458 case 0xD00000:
459 switch (address & 0xFC0000) {
460 case 0xC00000: // Expansion slot 0
461 case 0xC40000: // Expansion slot 1
462 case 0xC80000: // Expansion slot 2
463 case 0xCC0000: // Expansion slot 3
464 case 0xD00000: // Expansion slot 4
465 case 0xD40000: // Expansion slot 5
466 case 0xD80000: // Expansion slot 6
467 case 0xDC0000: // Expansion slot 7
468 fprintf(stderr, "NOTE: RD16 from expansion card space, addr=0x%08X\n", address);
469 break;
470 }
471 break;
472 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
473 case 0xF00000:
474 switch (address & 0x070000) {
475 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
476 break;
477 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
478 data = wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
479 printf("WD279X: rd %02X ==> %02X\n", (address >> 1) & 3, data);
480 handled = true;
481 break;
482 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
483 break;
484 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
485 break;
486 case 0x040000: // [ef][4c]xxxx ==> General Control Register
487 switch (address & 0x077000) {
488 case 0x040000: // [ef][4c][08]xxx ==> EE
489 case 0x041000: // [ef][4c][19]xxx ==> PIE
490 case 0x042000: // [ef][4c][2A]xxx ==> BP
491 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
492 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
493 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
494 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
495 // All write-only registers... TODO: bus error?
496 handled = true;
497 break;
498 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
499 break;
500 }
501 break;
502 case 0x050000: // [ef][5d]xxxx ==> 8274
503 break;
504 case 0x060000: // [ef][6e]xxxx ==> Control regs
505 switch (address & 0x07F000) {
506 default:
507 break;
508 }
509 break;
510 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
511 break;
512 }
513 }
514 }
516 LOG_NOT_HANDLED_R(16);
517 return data;
518 }
520 /**
521 * @brief Read M68K memory, 8-bit
522 */
523 uint32_t m68k_read_memory_8(uint32_t address)
524 {
525 uint8_t data = 0xFF;
526 bool handled = false;
528 // If ROMLMAP is set, force system to access ROM
529 if (!state.romlmap)
530 address |= 0x800000;
532 // Check access permissions
533 ACCESS_CHECK_RD(address, 8);
535 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
536 // ROM access
537 data = RD8(state.rom, address, ROM_SIZE - 1);
538 handled = true;
539 } else if (address <= (state.ram_size - 1)) {
540 // RAM access
541 data = RD8(state.ram, mapAddr(address, false), state.ram_size - 1);
542 handled = true;
543 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
544 // I/O register space, zone A
545 switch (address & 0x0F0000) {
546 case 0x000000: // Map RAM access
547 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
548 data = RD8(state.map, address, 0x7FF);
549 handled = true;
550 break;
551 case 0x010000: // General Status Register
552 if ((address & 1) == 0)
553 data = (state.genstat >> 8) & 0xff;
554 else
555 data = (state.genstat) & 0xff;
556 handled = true;
557 break;
558 case 0x020000: // Video RAM
559 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
560 data = RD8(state.vram, address, 0x7FFF);
561 handled = true;
562 break;
563 case 0x030000: // Bus Status Register 0
564 if ((address & 1) == 0)
565 data = (state.bsr0 >> 8) & 0xff;
566 else
567 data = (state.bsr0) & 0xff;
568 handled = true;
569 break;
570 case 0x040000: // Bus Status Register 1
571 if ((address & 1) == 0)
572 data = (state.bsr1 >> 8) & 0xff;
573 else
574 data = (state.bsr1) & 0xff;
575 handled = true;
576 break;
577 case 0x050000: // Phone status
578 break;
579 case 0x060000: // DMA Count
580 break;
581 case 0x070000: // Line Printer Status Register
582 break;
583 case 0x080000: // Real Time Clock
584 break;
585 case 0x090000: // Phone registers
586 switch (address & 0x0FF000) {
587 case 0x090000: // Handset relay
588 case 0x098000:
589 break;
590 case 0x091000: // Line select 2
591 case 0x099000:
592 break;
593 case 0x092000: // Hook relay 1
594 case 0x09A000:
595 break;
596 case 0x093000: // Hook relay 2
597 case 0x09B000:
598 break;
599 case 0x094000: // Line 1 hold
600 case 0x09C000:
601 break;
602 case 0x095000: // Line 2 hold
603 case 0x09D000:
604 break;
605 case 0x096000: // Line 1 A-lead
606 case 0x09E000:
607 break;
608 case 0x097000: // Line 2 A-lead
609 case 0x09F000:
610 break;
611 }
612 break;
613 case 0x0A0000: // Miscellaneous Control Register -- write only!
614 handled = true;
615 break;
616 case 0x0B0000: // TM/DIALWR
617 break;
618 case 0x0C0000: // Clear Status Register -- write only!
619 handled = true;
620 break;
621 case 0x0D0000: // DMA Address Register
622 break;
623 case 0x0E0000: // Disk Control Register
624 break;
625 case 0x0F0000: // Line Printer Data Register
626 break;
627 }
628 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
629 // I/O register space, zone B
630 switch (address & 0xF00000) {
631 case 0xC00000: // Expansion slots
632 case 0xD00000:
633 switch (address & 0xFC0000) {
634 case 0xC00000: // Expansion slot 0
635 case 0xC40000: // Expansion slot 1
636 case 0xC80000: // Expansion slot 2
637 case 0xCC0000: // Expansion slot 3
638 case 0xD00000: // Expansion slot 4
639 case 0xD40000: // Expansion slot 5
640 case 0xD80000: // Expansion slot 6
641 case 0xDC0000: // Expansion slot 7
642 fprintf(stderr, "NOTE: RD8 from expansion card space, addr=0x%08X\n", address);
643 break;
644 }
645 break;
646 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
647 case 0xF00000:
648 switch (address & 0x070000) {
649 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
650 break;
651 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
652 data = wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
653 printf("WD279X: rd %02X ==> %02X\n", (address >> 1) & 3, data);
654 handled = true;
655 break;
656 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
657 break;
658 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
659 break;
660 case 0x040000: // [ef][4c]xxxx ==> General Control Register
661 switch (address & 0x077000) {
662 case 0x040000: // [ef][4c][08]xxx ==> EE
663 case 0x041000: // [ef][4c][19]xxx ==> PIE
664 case 0x042000: // [ef][4c][2A]xxx ==> BP
665 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
666 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
667 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
668 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
669 // All write-only registers... TODO: bus error?
670 handled = true;
671 break;
672 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
673 break;
674 }
675 case 0x050000: // [ef][5d]xxxx ==> 8274
676 break;
677 case 0x060000: // [ef][6e]xxxx ==> Control regs
678 switch (address & 0x07F000) {
679 default:
680 break;
681 }
682 break;
683 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
684 break;
685 }
686 }
687 }
689 LOG_NOT_HANDLED_R(8);
691 return data;
692 }
694 /**
695 * @brief Write M68K memory, 32-bit
696 */
697 void m68k_write_memory_32(uint32_t address, uint32_t value)
698 {
699 bool handled = false;
701 // If ROMLMAP is set, force system to access ROM
702 if (!state.romlmap)
703 address |= 0x800000;
705 // Check access permissions
706 ACCESS_CHECK_WR(address, 32);
708 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
709 // ROM access
710 handled = true;
711 } else if (address <= (state.ram_size - 1)) {
712 // RAM access
713 WR32(state.ram, mapAddr(address, false), state.ram_size - 1, value);
714 handled = true;
715 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
716 // I/O register space, zone A
717 switch (address & 0x0F0000) {
718 case 0x000000: // Map RAM access
719 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
720 WR32(state.map, address, 0x7FF, value);
721 handled = true;
722 break;
723 case 0x010000: // General Status Register
724 state.genstat = (value & 0xffff);
725 handled = true;
726 break;
727 case 0x020000: // Video RAM
728 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
729 WR32(state.vram, address, 0x7FFF, value);
730 handled = true;
731 break;
732 case 0x030000: // Bus Status Register 0
733 break;
734 case 0x040000: // Bus Status Register 1
735 break;
736 case 0x050000: // Phone status
737 break;
738 case 0x060000: // DMA Count
739 break;
740 case 0x070000: // Line Printer Status Register
741 break;
742 case 0x080000: // Real Time Clock
743 break;
744 case 0x090000: // Phone registers
745 switch (address & 0x0FF000) {
746 case 0x090000: // Handset relay
747 case 0x098000:
748 break;
749 case 0x091000: // Line select 2
750 case 0x099000:
751 break;
752 case 0x092000: // Hook relay 1
753 case 0x09A000:
754 break;
755 case 0x093000: // Hook relay 2
756 case 0x09B000:
757 break;
758 case 0x094000: // Line 1 hold
759 case 0x09C000:
760 break;
761 case 0x095000: // Line 2 hold
762 case 0x09D000:
763 break;
764 case 0x096000: // Line 1 A-lead
765 case 0x09E000:
766 break;
767 case 0x097000: // Line 2 A-lead
768 case 0x09F000:
769 break;
770 }
771 break;
772 case 0x0A0000: // Miscellaneous Control Register
773 // TODO: handle the ctrl bits properly
774 // TODO: &0x8000 --> dismiss 60hz intr
775 state.dma_reading = (value & 0x4000);
776 state.leds = (~value & 0xF00) >> 8;
777 printf("LEDs: %s %s %s %s\n",
778 (state.leds & 8) ? "R" : "-",
779 (state.leds & 4) ? "G" : "-",
780 (state.leds & 2) ? "Y" : "-",
781 (state.leds & 1) ? "R" : "-");
782 handled = true;
783 break;
784 case 0x0B0000: // TM/DIALWR
785 break;
786 case 0x0C0000: // Clear Status Register
787 state.genstat = 0xFFFF;
788 state.bsr0 = 0xFFFF;
789 state.bsr1 = 0xFFFF;
790 handled = true;
791 break;
792 case 0x0D0000: // DMA Address Register
793 if (address & 0x004000) {
794 // A14 high -- set most significant bits
795 state.dma_address = (state.dma_address & 0xff) | ((address & 0x3fff) << 7);
796 } else {
797 // A14 low -- set least significant bits
798 state.dma_address = (state.dma_address & 0x3fff00) | (address & 0xff);
799 }
800 break;
801 case 0x0E0000: // Disk Control Register
802 // B7 = FDD controller reset
803 if ((value & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
804 // B6 = drive 0 select -- TODO
805 // B5 = motor enable -- TODO
806 // B4 = HDD controller reset -- TODO
807 // B3 = HDD0 select -- TODO
808 // B2,1,0 = HDD0 head select
809 break;
810 case 0x0F0000: // Line Printer Data Register
811 break;
812 }
813 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
814 // I/O register space, zone B
815 switch (address & 0xF00000) {
816 case 0xC00000: // Expansion slots
817 case 0xD00000:
818 switch (address & 0xFC0000) {
819 case 0xC00000: // Expansion slot 0
820 case 0xC40000: // Expansion slot 1
821 case 0xC80000: // Expansion slot 2
822 case 0xCC0000: // Expansion slot 3
823 case 0xD00000: // Expansion slot 4
824 case 0xD40000: // Expansion slot 5
825 case 0xD80000: // Expansion slot 6
826 case 0xDC0000: // Expansion slot 7
827 fprintf(stderr, "NOTE: WR32 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
828 handled = true;
829 break;
830 }
831 break;
832 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
833 case 0xF00000:
834 switch (address & 0x070000) {
835 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
836 break;
837 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
838 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, value);
839 printf("WD279X: wr %02X ==> %02X\n\t", (address >> 1) & 3, value);
840 //handled = true;
841 break;
842 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
843 break;
844 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
845 break;
846 case 0x040000: // [ef][4c]xxxx ==> General Control Register
847 switch (address & 0x077000) {
848 case 0x040000: // [ef][4c][08]xxx ==> EE
849 break;
850 case 0x041000: // [ef][4c][19]xxx ==> PIE
851 state.pie = ((value & 0x8000) == 0x8000);
852 handled = true;
853 break;
854 case 0x042000: // [ef][4c][2A]xxx ==> BP
855 break;
856 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
857 state.romlmap = ((value & 0x8000) == 0x8000);
858 handled = true;
859 break;
860 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
861 break;
862 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
863 break;
864 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
865 break;
866 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
867 break;
868 }
869 case 0x050000: // [ef][5d]xxxx ==> 8274
870 break;
871 case 0x060000: // [ef][6e]xxxx ==> Control regs
872 switch (address & 0x07F000) {
873 default:
874 break;
875 }
876 break;
877 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
878 break;
879 }
880 }
881 }
883 LOG_NOT_HANDLED_W(32);
884 }
886 /**
887 * @brief Write M68K memory, 16-bit
888 */
889 void m68k_write_memory_16(uint32_t address, uint32_t value)
890 {
891 bool handled = false;
893 // If ROMLMAP is set, force system to access ROM
894 if (!state.romlmap)
895 address |= 0x800000;
897 // Check access permissions
898 ACCESS_CHECK_WR(address, 16);
900 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
901 // ROM access
902 handled = true;
903 } else if (address <= (state.ram_size - 1)) {
904 // RAM access
905 WR16(state.ram, mapAddr(address, false), state.ram_size - 1, value);
906 handled = true;
907 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
908 // I/O register space, zone A
909 switch (address & 0x0F0000) {
910 case 0x000000: // Map RAM access
911 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
912 WR16(state.map, address, 0x7FF, value);
913 handled = true;
914 break;
915 case 0x010000: // General Status Register (read only)
916 handled = true;
917 break;
918 case 0x020000: // Video RAM
919 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
920 WR16(state.vram, address, 0x7FFF, value);
921 handled = true;
922 break;
923 case 0x030000: // Bus Status Register 0 (read only)
924 handled = true;
925 break;
926 case 0x040000: // Bus Status Register 1 (read only)
927 handled = true;
928 break;
929 case 0x050000: // Phone status
930 break;
931 case 0x060000: // DMA Count
932 break;
933 case 0x070000: // Line Printer Status Register
934 break;
935 case 0x080000: // Real Time Clock
936 break;
937 case 0x090000: // Phone registers
938 switch (address & 0x0FF000) {
939 case 0x090000: // Handset relay
940 case 0x098000:
941 break;
942 case 0x091000: // Line select 2
943 case 0x099000:
944 break;
945 case 0x092000: // Hook relay 1
946 case 0x09A000:
947 break;
948 case 0x093000: // Hook relay 2
949 case 0x09B000:
950 break;
951 case 0x094000: // Line 1 hold
952 case 0x09C000:
953 break;
954 case 0x095000: // Line 2 hold
955 case 0x09D000:
956 break;
957 case 0x096000: // Line 1 A-lead
958 case 0x09E000:
959 break;
960 case 0x097000: // Line 2 A-lead
961 case 0x09F000:
962 break;
963 }
964 break;
965 case 0x0A0000: // Miscellaneous Control Register
966 // TODO: handle the ctrl bits properly
967 // TODO: &0x8000 --> dismiss 60hz intr
968 state.dma_reading = (value & 0x4000);
969 state.leds = (~value & 0xF00) >> 8;
970 printf("LEDs: %s %s %s %s\n",
971 (state.leds & 8) ? "R" : "-",
972 (state.leds & 4) ? "G" : "-",
973 (state.leds & 2) ? "Y" : "-",
974 (state.leds & 1) ? "R" : "-");
975 handled = true;
976 break;
977 case 0x0B0000: // TM/DIALWR
978 break;
979 case 0x0C0000: // Clear Status Register
980 state.genstat = 0xFFFF;
981 state.bsr0 = 0xFFFF;
982 state.bsr1 = 0xFFFF;
983 handled = true;
984 break;
985 case 0x0D0000: // DMA Address Register
986 if (address & 0x004000) {
987 // A14 high -- set most significant bits
988 state.dma_address = (state.dma_address & 0xff) | ((address & 0x3fff) << 7);
989 } else {
990 // A14 low -- set least significant bits
991 state.dma_address = (state.dma_address & 0x3fff00) | (address & 0xff);
992 }
993 break;
994 case 0x0E0000: // Disk Control Register
995 // B7 = FDD controller reset
996 if ((value & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
997 // B6 = drive 0 select -- TODO
998 // B5 = motor enable -- TODO
999 // B4 = HDD controller reset -- TODO
1000 // B3 = HDD0 select -- TODO
1001 // B2,1,0 = HDD0 head select
1002 break;
1003 case 0x0F0000: // Line Printer Data Register
1004 break;
1005 }
1006 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
1007 // I/O register space, zone B
1008 switch (address & 0xF00000) {
1009 case 0xC00000: // Expansion slots
1010 case 0xD00000:
1011 switch (address & 0xFC0000) {
1012 case 0xC00000: // Expansion slot 0
1013 case 0xC40000: // Expansion slot 1
1014 case 0xC80000: // Expansion slot 2
1015 case 0xCC0000: // Expansion slot 3
1016 case 0xD00000: // Expansion slot 4
1017 case 0xD40000: // Expansion slot 5
1018 case 0xD80000: // Expansion slot 6
1019 case 0xDC0000: // Expansion slot 7
1020 fprintf(stderr, "NOTE: WR16 to expansion card space, addr=0x%08X, data=0x%04X\n", address, value);
1021 break;
1022 }
1023 break;
1024 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
1025 case 0xF00000:
1026 switch (address & 0x070000) {
1027 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
1028 break;
1029 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
1030 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, value);
1031 printf("WD279X: wr %02X ==> %02X\n\t", (address >> 1) & 3, value);
1032 //handled = true;
1033 break;
1034 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
1035 break;
1036 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
1037 break;
1038 case 0x040000: // [ef][4c]xxxx ==> General Control Register
1039 switch (address & 0x077000) {
1040 case 0x040000: // [ef][4c][08]xxx ==> EE
1041 break;
1042 case 0x041000: // [ef][4c][19]xxx ==> PIE
1043 state.pie = ((value & 0x8000) == 0x8000);
1044 handled = true;
1045 break;
1046 case 0x042000: // [ef][4c][2A]xxx ==> BP
1047 break;
1048 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
1049 state.romlmap = ((value & 0x8000) == 0x8000);
1050 handled = true;
1051 break;
1052 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
1053 break;
1054 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
1055 break;
1056 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
1057 break;
1058 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
1059 break;
1060 }
1061 case 0x050000: // [ef][5d]xxxx ==> 8274
1062 break;
1063 case 0x060000: // [ef][6e]xxxx ==> Control regs
1064 switch (address & 0x07F000) {
1065 default:
1066 break;
1067 }
1068 break;
1069 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
1070 break;
1071 }
1072 }
1073 }
1075 LOG_NOT_HANDLED_W(16);
1076 }
1078 /**
1079 * @brief Write M68K memory, 8-bit
1080 */
1081 void m68k_write_memory_8(uint32_t address, uint32_t value)
1082 {
1083 bool handled = false;
1085 // If ROMLMAP is set, force system to access ROM
1086 if (!state.romlmap)
1087 address |= 0x800000;
1089 // Check access permissions
1090 ACCESS_CHECK_WR(address, 8);
1092 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
1093 // ROM access (read only!)
1094 handled = true;
1095 } else if (address <= (state.ram_size - 1)) {
1096 // RAM access
1097 WR8(state.ram, mapAddr(address, false), state.ram_size - 1, value);
1098 handled = true;
1099 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
1100 // I/O register space, zone A
1101 switch (address & 0x0F0000) {
1102 case 0x000000: // Map RAM access
1103 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=%08X, data=%02X\n", address, value);
1104 WR8(state.map, address, 0x7FF, value);
1105 handled = true;
1106 break;
1107 case 0x010000: // General Status Register
1108 handled = true;
1109 break;
1110 case 0x020000: // Video RAM
1111 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=%08X, data=0x%02X\n", address, value);
1112 WR8(state.vram, address, 0x7FFF, value);
1113 handled = true;
1114 break;
1115 case 0x030000: // Bus Status Register 0
1116 handled = true;
1117 break;
1118 case 0x040000: // Bus Status Register 1
1119 handled = true;
1120 break;
1121 case 0x050000: // Phone status
1122 break;
1123 case 0x060000: // DMA Count
1124 break;
1125 case 0x070000: // Line Printer Status Register
1126 break;
1127 case 0x080000: // Real Time Clock
1128 break;
1129 case 0x090000: // Phone registers
1130 switch (address & 0x0FF000) {
1131 case 0x090000: // Handset relay
1132 case 0x098000:
1133 break;
1134 case 0x091000: // Line select 2
1135 case 0x099000:
1136 break;
1137 case 0x092000: // Hook relay 1
1138 case 0x09A000:
1139 break;
1140 case 0x093000: // Hook relay 2
1141 case 0x09B000:
1142 break;
1143 case 0x094000: // Line 1 hold
1144 case 0x09C000:
1145 break;
1146 case 0x095000: // Line 2 hold
1147 case 0x09D000:
1148 break;
1149 case 0x096000: // Line 1 A-lead
1150 case 0x09E000:
1151 break;
1152 case 0x097000: // Line 2 A-lead
1153 case 0x09F000:
1154 break;
1155 }
1156 break;
1157 case 0x0A0000: // Miscellaneous Control Register
1158 // TODO: handle the ctrl bits properly
1159 if ((address & 1) == 0) {
1160 // low byte
1161 } else {
1162 // hight byte
1163 // TODO: &0x8000 --> dismiss 60hz intr
1164 state.dma_reading = (value & 0x40);
1165 state.leds = (~value & 0xF);
1166 }
1167 printf("LEDs: %s %s %s %s\n",
1168 (state.leds & 8) ? "R" : "-",
1169 (state.leds & 4) ? "G" : "-",
1170 (state.leds & 2) ? "Y" : "-",
1171 (state.leds & 1) ? "R" : "-");
1172 handled = true;
1173 break;
1174 case 0x0B0000: // TM/DIALWR
1175 break;
1176 case 0x0C0000: // Clear Status Register
1177 state.genstat = 0xFFFF;
1178 state.bsr0 = 0xFFFF;
1179 state.bsr1 = 0xFFFF;
1180 handled = true;
1181 break;
1182 case 0x0D0000: // DMA Address Register
1183 if (address & 0x004000) {
1184 // A14 high -- set most significant bits
1185 state.dma_address = (state.dma_address & 0xff) | ((address & 0x3fff) << 7);
1186 } else {
1187 // A14 low -- set least significant bits
1188 state.dma_address = (state.dma_address & 0x3fff00) | (address & 0xff);
1189 }
1190 break;
1191 case 0x0E0000: // Disk Control Register
1192 // B7 = FDD controller reset
1193 if ((value & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
1194 // B6 = drive 0 select -- TODO
1195 // B5 = motor enable -- TODO
1196 // B4 = HDD controller reset -- TODO
1197 // B3 = HDD0 select -- TODO
1198 // B2,1,0 = HDD0 head select
1199 break;
1200 case 0x0F0000: // Line Printer Data Register
1201 break;
1202 }
1203 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
1204 // I/O register space, zone B
1205 switch (address & 0xF00000) {
1206 case 0xC00000: // Expansion slots
1207 case 0xD00000:
1208 switch (address & 0xFC0000) {
1209 case 0xC00000: // Expansion slot 0
1210 case 0xC40000: // Expansion slot 1
1211 case 0xC80000: // Expansion slot 2
1212 case 0xCC0000: // Expansion slot 3
1213 case 0xD00000: // Expansion slot 4
1214 case 0xD40000: // Expansion slot 5
1215 case 0xD80000: // Expansion slot 6
1216 case 0xDC0000: // Expansion slot 7
1217 fprintf(stderr, "NOTE: WR8 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
1218 break;
1219 }
1220 break;
1221 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
1222 case 0xF00000:
1223 switch (address & 0x070000) {
1224 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
1225 break;
1226 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
1227 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, value);
1228 printf("WD279X: wr %02X ==> %02X\n\t", (address >> 1) & 3, value);
1229 //handled = true;
1230 break;
1231 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
1232 break;
1233 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
1234 break;
1235 case 0x040000: // [ef][4c]xxxx ==> General Control Register
1236 switch (address & 0x077000) {
1237 case 0x040000: // [ef][4c][08]xxx ==> EE
1238 break;
1239 case 0x041000: // [ef][4c][19]xxx ==> PIE
1240 if ((address & 1) == 0)
1241 state.pie = ((value & 0x80) == 0x80);
1242 handled = true;
1243 break;
1244 case 0x042000: // [ef][4c][2A]xxx ==> BP
1245 break;
1246 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
1247 if ((address & 1) == 0)
1248 state.romlmap = ((value & 0x80) == 0x80);
1249 handled = true;
1250 break;
1251 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
1252 break;
1253 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
1254 break;
1255 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
1256 break;
1257 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
1258 break;
1259 }
1260 case 0x050000: // [ef][5d]xxxx ==> 8274
1261 break;
1262 case 0x060000: // [ef][6e]xxxx ==> Control regs
1263 switch (address & 0x07F000) {
1264 default:
1265 break;
1266 }
1267 break;
1268 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
1269 break;
1270 default:
1271 fprintf(stderr, "NOTE: WR8 to undefined E/F-block space, addr=0x%08X, data=0x%08X\n", address, value);
1272 break;
1273 }
1274 }
1275 }
1277 LOG_NOT_HANDLED_W(8);
1278 }
1281 // for the disassembler
1282 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
1283 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
1284 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }