src/memory.c

Fri, 04 Mar 2011 01:36:30 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Fri, 04 Mar 2011 01:36:30 +0000
changeset 104
b12651d8a0ab
parent 103
b749a3356e8d
child 105
343250338d23
permissions
-rw-r--r--

fix issue with WE+ bit becoming unset, fix pagefault:not-mapped-in logic

- The WE+ (page write enable) bit was becoming unset when the Page Status bits were being set.
A stupid mistake in an AND expression was unsetting the write-enable, thus making S4TEST 12,2 and 12,3 fail spectacularly.

- Pagefaults were not being generated correctly for pages which were not mapped in. Even Supervisor code accessing unmapped pages should get a PF.

     1 #include <stdio.h>
     2 #include <stdlib.h>
     3 #include <stdint.h>
     4 #include <stdbool.h>
     5 #include <assert.h>
     6 #include "musashi/m68k.h"
     7 #include "state.h"
     8 #include "utils.h"
     9 #include "memory.h"
    11 /******************
    12  * Memory mapping
    13  ******************/
    15 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
    17 uint32_t mapAddr(uint32_t addr, bool writing)/*{{{*/
    18 {
    19 	if (addr < 0x400000) {
    20 		// RAM access. Check against the Map RAM
    21 		// Start by getting the original page address
    22 		uint16_t page = (addr >> 12) & 0x3FF;
    24 		// Look it up in the map RAM and get the physical page address
    25 		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
    27 		// Update the Page Status bits
    28 		uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
    29 		// Pagebits --
    30 		//   0 = not present
    31 		//   1 = present but not accessed
    32 		//   2 = present, accessed (read from)
    33 		//   3 = present, dirty (written to)
    34 		switch (pagebits) {
    35 			case 0:
    36 				// Page not present
    37 				// This should cause a page fault
    38 				LOGS("Whoa! Pagebit update, when the page is not present!");
    39 				break;
    41 			case 1:
    42 				// Page present -- first access
    43 				state.map[page*2] &= 0x9F;	// turn off "present" bit (but not write enable!)
    44 				if (writing)
    45 					state.map[page*2] |= 0x60;		// Page written to (dirty)
    46 				else
    47 					state.map[page*2] |= 0x40;		// Page accessed but not written
    48 				break;
    50 			case 2:
    51 			case 3:
    52 				// Page present, 2nd or later access
    53 				if (writing)
    54 					state.map[page*2] |= 0x60;		// Page written to (dirty)
    55 				break;
    56 		}
    58 		// Return the address with the new physical page spliced in
    59 		return (new_page_addr << 12) + (addr & 0xFFF);
    60 	} else {
    61 		// I/O, VRAM or MapRAM space; no mapping is performed or required
    62 		// TODO: assert here?
    63 		return addr;
    64 	}
    65 }/*}}}*/
    67 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)/*{{{*/
    68 {
    69 	// Get the page bits for this page.
    70 	uint16_t page = (addr >> 12) & 0x3FF;
    71 	uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
    73 	// Check page is present (but only for RAM zone)
    74 	if ((addr < 0x400000) && ((pagebits & 0x03) == 0)) {
    75 		LOG("Page not mapped in: addr %08X, page %04X, mapbits %04X", addr, page, MAPRAM(page));
    76 		return MEM_PAGEFAULT;
    77 	}
    79 	// Are we in Supervisor mode?
    80 	if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
    81 		// Yes. We can do anything we like.
    82 		return MEM_ALLOWED;
    84 	// If we're here, then we must be in User mode.
    85 	// Check that the user didn't access memory outside of the RAM area
    86 	if (addr >= 0x400000)
    87 		return MEM_UIE;
    89 	// User attempt to access the kernel
    90 	// A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
    91 	if (((addr >> 19) & 0x0F) == 0)
    92 		return MEM_KERNEL;
    94 	// Check page is write enabled
    95 	if (writing && ((pagebits & 0x04) == 0))
    96 		return MEM_PAGE_NO_WE;
    98 	// Page access allowed.
    99 	return MEM_ALLOWED;
   100 }/*}}}*/
   102 #undef MAPRAM
   105 /********************************************************
   106  * m68k memory read/write support functions for Musashi
   107  ********************************************************/
   109 /**
   110  * @brief	Check memory access permissions for a write operation.
   111  * @note	This used to be a single macro (merged with ACCESS_CHECK_RD), but
   112  * 			gcc throws warnings when you have a return-with-value in a void
   113  * 			function, even if the return-with-value is completely unreachable.
   114  * 			Similarly it doesn't like it if you have a return without a value
   115  * 			in a non-void function, even if it's impossible to ever reach the
   116  * 			return-with-no-value. UGH!
   117  */
   118 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
   119 #define ACCESS_CHECK_WR(address, bits)								\
   120 	do {															\
   121 		bool fault = false;											\
   122 		MEM_STATUS st;												\
   123 		switch (st = checkMemoryAccess(address, true)) {			\
   124 			case MEM_ALLOWED:										\
   125 				/* Access allowed */								\
   126 				break;												\
   127 			case MEM_PAGEFAULT:										\
   128 				/* Page fault */									\
   129 				state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0);	\
   130 				fault = true;										\
   131 				break;												\
   132 			case MEM_UIE:											\
   133 				/* User access to memory above 4MB */				\
   134 				state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0);	\
   135 				fault = true;										\
   136 				break;												\
   137 			case MEM_KERNEL:										\
   138 			case MEM_PAGE_NO_WE:									\
   139 				/* kernel access or page not write enabled */		\
   140 				/* FIXME: which regs need setting? */				\
   141 				fault = true;										\
   142 				break;												\
   143 		}															\
   144 																	\
   145 		if (fault) {												\
   146 			if (bits >= 16)											\
   147 				state.bsr0 = 0x7C00;								\
   148 			else													\
   149 				state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00;		\
   150 			state.bsr0 |= (address >> 16);							\
   151 			state.bsr1 = address & 0xffff;							\
   152 			LOG("Bus Error while writing, addr %08X, statcode %d", address, st);		\
   153 			if (state.ee) m68k_pulse_bus_error();					\
   154 			return;													\
   155 		}															\
   156 	} while (0)
   157 /*}}}*/
   159 /**
   160  * @brief Check memory access permissions for a read operation.
   161  * @note	This used to be a single macro (merged with ACCESS_CHECK_WR), but
   162  * 			gcc throws warnings when you have a return-with-value in a void
   163  * 			function, even if the return-with-value is completely unreachable.
   164  * 			Similarly it doesn't like it if you have a return without a value
   165  * 			in a non-void function, even if it's impossible to ever reach the
   166  * 			return-with-no-value. UGH!
   167  */
   168 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
   169 #define ACCESS_CHECK_RD(address, bits)								\
   170 	do {															\
   171 		bool fault = false;											\
   172 		MEM_STATUS st;												\
   173 		switch (st = checkMemoryAccess(address, false)) {			\
   174 			case MEM_ALLOWED:										\
   175 				/* Access allowed */								\
   176 				break;												\
   177 			case MEM_PAGEFAULT:										\
   178 				/* Page fault */									\
   179 				state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0);	\
   180 				fault = true;										\
   181 				break;												\
   182 			case MEM_UIE:											\
   183 				/* User access to memory above 4MB */				\
   184 				state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0);	\
   185 				fault = true;										\
   186 				break;												\
   187 			case MEM_KERNEL:										\
   188 			case MEM_PAGE_NO_WE:									\
   189 				/* kernel access or page not write enabled */		\
   190 				/* FIXME: which regs need setting? */				\
   191 				fault = true;										\
   192 				break;												\
   193 		}															\
   194 																	\
   195 		if (fault) {												\
   196 			if (bits >= 16)											\
   197 				state.bsr0 = 0x7C00;								\
   198 			else													\
   199 				state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00;		\
   200 			state.bsr0 |= (address >> 16);							\
   201 			state.bsr1 = address & 0xffff;							\
   202 			LOG("Bus Error while reading, addr %08X, statcode %d", address, st);		\
   203 			if (state.ee) m68k_pulse_bus_error();					\
   204 			return 0xFFFFFFFF;										\
   205 		}															\
   206 	} while (0)
   207 /*}}}*/
   209 // Logging macros
   210 #define LOG_NOT_HANDLED_R(bits)															\
   211 	if (!handled) printf("unhandled read%02d, addr=0x%08X\n", bits, address);
   213 #define LOG_NOT_HANDLED_W(bits)															\
   214 	if (!handled) printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
   216 /********************************************************
   217  * I/O read/write functions
   218  ********************************************************/
   220 /**
   221  * Issue a warning if a read operation is made with an invalid size
   222  */
   223 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
   224 {
   225 	assert((bits == 8) || (bits == 16) || (bits == 32));
   226 	if ((bits & allowed) == 0) {
   227 		printf("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
   228 	}
   229 }
   231 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
   232 {
   233 	ENFORCE_SIZE(bits, address, true, allowed, regname);
   234 }
   236 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
   237 {
   238 	ENFORCE_SIZE(bits, address, false, allowed, regname);
   239 }
   241 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
   242 {
   243 	bool handled = false;
   245 	if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   246 		// I/O register space, zone A
   247 		switch (address & 0x0F0000) {
   248 			case 0x010000:				// General Status Register
   249 				if (bits == 16)
   250 					state.genstat = (data & 0xffff);
   251 				else if (bits == 8) {
   252 					if (address & 0)
   253 						state.genstat = data;
   254 					else
   255 						state.genstat = data << 8;
   256 				}
   257 				handled = true;
   258 				break;
   259 			case 0x030000:				// Bus Status Register 0
   260 				break;
   261 			case 0x040000:				// Bus Status Register 1
   262 				break;
   263 			case 0x050000:				// Phone status
   264 				break;
   265 			case 0x060000:				// DMA Count
   266 				ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
   267 				state.dma_count = (data & 0x3FFF);
   268 				state.idmarw = ((data & 0x4000) == 0x4000);
   269 				state.dmaen = ((data & 0x8000) == 0x8000);
   270 				// This handles the "dummy DMA transfer" mentioned in the docs
   271 				// TODO: access check, peripheral access
   272 				if (!state.idmarw)
   273 					WR32(state.base_ram, mapAddr(address, true), state.base_ram_size - 1, 0xDEAD);
   274 				state.dma_count++;
   275 				handled = true;
   276 				break;
   277 			case 0x070000:				// Line Printer Status Register
   278 				break;
   279 			case 0x080000:				// Real Time Clock
   280 				break;
   281 			case 0x090000:				// Phone registers
   282 				switch (address & 0x0FF000) {
   283 					case 0x090000:		// Handset relay
   284 					case 0x098000:
   285 						break;
   286 					case 0x091000:		// Line select 2
   287 					case 0x099000:
   288 						break;
   289 					case 0x092000:		// Hook relay 1
   290 					case 0x09A000:
   291 						break;
   292 					case 0x093000:		// Hook relay 2
   293 					case 0x09B000:
   294 						break;
   295 					case 0x094000:		// Line 1 hold
   296 					case 0x09C000:
   297 						break;
   298 					case 0x095000:		// Line 2 hold
   299 					case 0x09D000:
   300 						break;
   301 					case 0x096000:		// Line 1 A-lead
   302 					case 0x09E000:
   303 						break;
   304 					case 0x097000:		// Line 2 A-lead
   305 					case 0x09F000:
   306 						break;
   307 				}
   308 				break;
   309 			case 0x0A0000:				// Miscellaneous Control Register
   310 				ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
   311 				// TODO: handle the ctrl bits properly
   312 				// TODO: &0x8000 --> dismiss 60hz intr
   313 				if (data & 0x8000){
   314 					state.timer_enabled = 1;
   315 				}else{
   316 					state.timer_enabled = 0;
   317 					state.timer_asserted = 0;
   318 				}
   319 				state.dma_reading = (data & 0x4000);
   320 				if (state.leds != ((~data & 0xF00) >> 8)) {
   321 					state.leds = (~data & 0xF00) >> 8;
   322 					printf("LEDs: %s %s %s %s\n",
   323 							(state.leds & 8) ? "R" : "-",
   324 							(state.leds & 4) ? "G" : "-",
   325 							(state.leds & 2) ? "Y" : "-",
   326 							(state.leds & 1) ? "R" : "-");
   327 				}
   328 				handled = true;
   329 				break;
   330 			case 0x0B0000:				// TM/DIALWR
   331 				break;
   332 			case 0x0C0000:				// Clear Status Register
   333 				state.genstat = 0xFFFF;
   334 				state.bsr0 = 0xFFFF;
   335 				state.bsr1 = 0xFFFF;
   336 				handled = true;
   337 				break;
   338 			case 0x0D0000:				// DMA Address Register
   339 				if (address & 0x004000) {
   340 					// A14 high -- set most significant bits
   341 					state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
   342 				} else {
   343 					// A14 low -- set least significant bits
   344 					state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
   345 				}
   346 				handled = true;
   347 				break;
   348 			case 0x0E0000:				// Disk Control Register
   349 				ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
   350 				// B7 = FDD controller reset
   351 				if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
   352 				// B6 = drive 0 select -- TODO
   353 				// B5 = motor enable -- TODO
   354 				// B4 = HDD controller reset -- TODO
   355 				// B3 = HDD0 select -- TODO
   356 				// B2,1,0 = HDD0 head select
   357 				handled = true;
   358 				break;
   359 			case 0x0F0000:				// Line Printer Data Register
   360 				break;
   361 		}
   362 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   363 		// I/O register space, zone B
   364 		switch (address & 0xF00000) {
   365 			case 0xC00000:				// Expansion slots
   366 			case 0xD00000:
   367 				switch (address & 0xFC0000) {
   368 					case 0xC00000:		// Expansion slot 0
   369 					case 0xC40000:		// Expansion slot 1
   370 					case 0xC80000:		// Expansion slot 2
   371 					case 0xCC0000:		// Expansion slot 3
   372 					case 0xD00000:		// Expansion slot 4
   373 					case 0xD40000:		// Expansion slot 5
   374 					case 0xD80000:		// Expansion slot 6
   375 					case 0xDC0000:		// Expansion slot 7
   376 						fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
   377 						handled = true;
   378 						break;
   379 				}
   380 				break;
   381 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   382 			case 0xF00000:
   383 				switch (address & 0x070000) {
   384 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   385 						break;
   386 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   387 						ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");
   388 						wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
   389 						handled = true;
   390 						break;
   391 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   392 						break;
   393 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   394 						break;
   395 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   396 						switch (address & 0x077000) {
   397 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   398 								// Error Enable. If =0, Level7 intrs and bus errors are masked.
   399 								ENFORCE_SIZE_W(bits, address, 16, "EE");
   400 								state.ee = ((data & 0x8000) == 0x8000);
   401 								handled = true;
   402 								break;
   403 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   404 								ENFORCE_SIZE_W(bits, address, 16, "PIE");
   405 								state.pie = ((data & 0x8000) == 0x8000);
   406 								handled = true;
   407 								break;
   408 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   409 								break;
   410 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   411 								ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
   412 								state.romlmap = ((data & 0x8000) == 0x8000);
   413 								handled = true;
   414 								break;
   415 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   416 								ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
   417 								break;
   418 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   419 								ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
   420 								break;
   421 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   422 								ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
   423 								break;
   424 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   425 								ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
   426 								break;
   427 						}
   428 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   429 						break;
   430 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   431 						switch (address & 0x07F000) {
   432 							default:
   433 								break;
   434 						}
   435 						break;
   436 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   437 						// TODO: figure out which sizes are valid (probably just 8 and 16)
   438 						// ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER");
   439 						if (bits == 8) {
   440 							printf("KBD WR %02X => %02X\n", (address >> 1) & 3, data);
   441 							keyboard_write(&state.kbd, (address >> 1) & 3, data);
   442 							handled = true;
   443 						} else if (bits == 16) {
   444 							printf("KBD WR %02X => %04X\n", (address >> 1) & 3, data);
   445 							keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8);
   446 							handled = true;
   447 						}
   448 						break;
   449 				}
   450 		}
   451 	}
   453 	LOG_NOT_HANDLED_W(bits);
   454 }/*}}}*/
   456 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
   457 {
   458 	bool handled = false;
   459 	uint32_t data = 0xFFFFFFFF;
   461 	if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   462 		// I/O register space, zone A
   463 		switch (address & 0x0F0000) {
   464 			case 0x010000:				// General Status Register
   465 				ENFORCE_SIZE_R(bits, address, 16, "GENSTAT");
   466 				return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
   467 				break;
   468 			case 0x030000:				// Bus Status Register 0
   469 				ENFORCE_SIZE_R(bits, address, 16, "BSR0");
   470 				return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
   471 				break;
   472 			case 0x040000:				// Bus Status Register 1
   473 				ENFORCE_SIZE_R(bits, address, 16, "BSR1");
   474 				return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
   475 				break;
   476 			case 0x050000:				// Phone status
   477 				ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
   478 				break;
   479 			case 0x060000:				// DMA Count
   480 				// TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
   481 				// Bit 14 is always unused, so leave it set
   482 				ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
   483 				return (state.dma_count & 0x3fff) | 0xC000;
   484 				break;
   485 			case 0x070000:				// Line Printer Status Register
   486 				data = 0x00120012;	// no parity error, no line printer error, no irqs from FDD or HDD
   487 				data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0;
   488 				return data;
   489 				break;
   490 			case 0x080000:				// Real Time Clock
   491 				printf("READ NOTIMP: Realtime Clock\n");
   492 				break;
   493 			case 0x090000:				// Phone registers
   494 				switch (address & 0x0FF000) {
   495 					case 0x090000:		// Handset relay
   496 					case 0x098000:
   497 						break;
   498 					case 0x091000:		// Line select 2
   499 					case 0x099000:
   500 						break;
   501 					case 0x092000:		// Hook relay 1
   502 					case 0x09A000:
   503 						break;
   504 					case 0x093000:		// Hook relay 2
   505 					case 0x09B000:
   506 						break;
   507 					case 0x094000:		// Line 1 hold
   508 					case 0x09C000:
   509 						break;
   510 					case 0x095000:		// Line 2 hold
   511 					case 0x09D000:
   512 						break;
   513 					case 0x096000:		// Line 1 A-lead
   514 					case 0x09E000:
   515 						break;
   516 					case 0x097000:		// Line 2 A-lead
   517 					case 0x09F000:
   518 						break;
   519 				}
   520 				break;
   521 			case 0x0A0000:				// Miscellaneous Control Register -- write only!
   522 				handled = true;
   523 				break;
   524 			case 0x0B0000:				// TM/DIALWR
   525 				break;
   526 			case 0x0C0000:				// Clear Status Register -- write only!
   527 				handled = true;
   528 				break;
   529 			case 0x0D0000:				// DMA Address Register
   530 				break;
   531 			case 0x0E0000:				// Disk Control Register
   532 				break;
   533 			case 0x0F0000:				// Line Printer Data Register
   534 				break;
   535 		}
   536 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   537 		// I/O register space, zone B
   538 		switch (address & 0xF00000) {
   539 			case 0xC00000:				// Expansion slots
   540 			case 0xD00000:
   541 				switch (address & 0xFC0000) {
   542 					case 0xC00000:		// Expansion slot 0
   543 					case 0xC40000:		// Expansion slot 1
   544 					case 0xC80000:		// Expansion slot 2
   545 					case 0xCC0000:		// Expansion slot 3
   546 					case 0xD00000:		// Expansion slot 4
   547 					case 0xD40000:		// Expansion slot 5
   548 					case 0xD80000:		// Expansion slot 6
   549 					case 0xDC0000:		// Expansion slot 7
   550 						fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
   551 						handled = true;
   552 						break;
   553 				}
   554 				break;
   555 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   556 			case 0xF00000:
   557 				switch (address & 0x070000) {
   558 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   559 						break;
   560 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   561 						ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");
   562 						return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
   563 						break;
   564 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   565 						break;
   566 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   567 						break;
   568 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   569 						switch (address & 0x077000) {
   570 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   571 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   572 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   573 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   574 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   575 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   576 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   577 								// All write-only registers... TODO: bus error?
   578 								handled = true;
   579 								break;
   580 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
   581 								break;
   582 						}
   583 						break;
   584 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   585 						break;
   586 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   587 						switch (address & 0x07F000) {
   588 							default:
   589 								break;
   590 						}
   591 						break;
   592 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   593 						// TODO: figure out which sizes are valid (probably just 8 and 16)
   594 						//ENFORCE_SIZE_R(bits, address, 16, "KEYBOARD CONTROLLER");
   595 						{
   596 							if (bits == 8) {
   597 								return keyboard_read(&state.kbd, (address >> 1) & 3);
   598 							} else {
   599 								return keyboard_read(&state.kbd, (address >> 1) & 3) << 8;
   600 							}
   601 							return data;
   602 						}
   603 						break;
   604 				}
   605 		}
   606 	}
   608 	LOG_NOT_HANDLED_R(bits);
   610 	return data;
   611 }/*}}}*/
   614 /********************************************************
   615  * m68k memory read/write support functions for Musashi
   616  ********************************************************/
   618 /**
   619  * @brief Read M68K memory, 32-bit
   620  */
   621 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
   622 {
   623 	uint32_t data = 0xFFFFFFFF;
   625 	// If ROMLMAP is set, force system to access ROM
   626 	if (!state.romlmap)
   627 		address |= 0x800000;
   629 	// Check access permissions
   630 	ACCESS_CHECK_RD(address, 32);
   632 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   633 		// ROM access
   634 		return RD32(state.rom, address, ROM_SIZE - 1);
   635 	} else if (address <= 0x3fffff) {
   636 		// RAM access
   637 		uint32_t newAddr = mapAddr(address, false);
   638 		if (newAddr <= 0x1fffff) {
   639 			return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
   640 		} else {
   641 			if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
   642 				return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   643 			else
   644 				return 0xffffffff;
   645 		}
   646 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   647 		// I/O register space, zone A
   648 		switch (address & 0x0F0000) {
   649 			case 0x000000:				// Map RAM access
   650 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
   651 				return RD32(state.map, address, 0x7FF);
   652 				break;
   653 			case 0x020000:				// Video RAM
   654 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
   655 				return RD32(state.vram, address, 0x7FFF);
   656 				break;
   657 			default:
   658 				return IoRead(address, 32);
   659 		}
   660 	} else {
   661 		return IoRead(address, 32);
   662 	}
   664 	return data;
   665 }/*}}}*/
   667 /**
   668  * @brief Read M68K memory, 16-bit
   669  */
   670 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
   671 {
   672 	uint16_t data = 0xFFFF;
   674 	// If ROMLMAP is set, force system to access ROM
   675 	if (!state.romlmap)
   676 		address |= 0x800000;
   678 	// Check access permissions
   679 	ACCESS_CHECK_RD(address, 16);
   681 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   682 		// ROM access
   683 		data = RD16(state.rom, address, ROM_SIZE - 1);
   684 	} else if (address <= 0x3fffff) {
   685 		// RAM access
   686 		uint32_t newAddr = mapAddr(address, false);
   687 		if (newAddr <= 0x1fffff) {
   688 			return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
   689 		} else {
   690 			if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
   691 				return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   692 			else
   693 				return 0xffff;
   694 		}
   695 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   696 		// I/O register space, zone A
   697 		switch (address & 0x0F0000) {
   698 			case 0x000000:				// Map RAM access
   699 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
   700 				data = RD16(state.map, address, 0x7FF);
   701 				break;
   702 			case 0x020000:				// Video RAM
   703 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
   704 				data = RD16(state.vram, address, 0x7FFF);
   705 				break;
   706 			default:
   707 				data = IoRead(address, 16);
   708 		}
   709 	} else {
   710 		data = IoRead(address, 16);
   711 	}
   713 	return data;
   714 }/*}}}*/
   716 /**
   717  * @brief Read M68K memory, 8-bit
   718  */
   719 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
   720 {
   721 	uint8_t data = 0xFF;
   723 	// If ROMLMAP is set, force system to access ROM
   724 	if (!state.romlmap)
   725 		address |= 0x800000;
   727 	// Check access permissions
   728 	ACCESS_CHECK_RD(address, 8);
   730 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   731 		// ROM access
   732 		data = RD8(state.rom, address, ROM_SIZE - 1);
   733 	} else if (address <= 0x3fffff) {
   734 		// RAM access
   735 		uint32_t newAddr = mapAddr(address, false);
   736 		if (newAddr <= 0x1fffff) {
   737 			return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
   738 		} else {
   739 			if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
   740 				return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   741 			else
   742 				return 0xff;
   743 		}
   744 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   745 		// I/O register space, zone A
   746 		switch (address & 0x0F0000) {
   747 			case 0x000000:				// Map RAM access
   748 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
   749 				data = RD8(state.map, address, 0x7FF);
   750 				break;
   751 			case 0x020000:				// Video RAM
   752 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
   753 				data = RD8(state.vram, address, 0x7FFF);
   754 				break;
   755 			default:
   756 				data = IoRead(address, 8);
   757 		}
   758 	} else {
   759 		data = IoRead(address, 8);
   760 	}
   762 	return data;
   763 }/*}}}*/
   765 /**
   766  * @brief Write M68K memory, 32-bit
   767  */
   768 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
   769 {
   770 	// If ROMLMAP is set, force system to access ROM
   771 	if (!state.romlmap)
   772 		address |= 0x800000;
   774 	// Check access permissions
   775 	ACCESS_CHECK_WR(address, 32);
   777 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   778 		// ROM access
   779 	} else if (address <= 0x3FFFFF) {
   780 		// RAM access
   781 		uint32_t newAddr = mapAddr(address, true);
   782 		if (newAddr <= 0x1fffff)
   783 			WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
   784 		else
   785 			WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   786 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   787 		// I/O register space, zone A
   788 		switch (address & 0x0F0000) {
   789 			case 0x000000:				// Map RAM access
   790 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
   791 				WR32(state.map, address, 0x7FF, value);
   792 				break;
   793 			case 0x020000:				// Video RAM
   794 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
   795 				WR32(state.vram, address, 0x7FFF, value);
   796 				break;
   797 			default:
   798 				IoWrite(address, value, 32);
   799 		}
   800 	} else {
   801 		IoWrite(address, value, 32);
   802 	}
   803 }/*}}}*/
   805 /**
   806  * @brief Write M68K memory, 16-bit
   807  */
   808 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
   809 {
   810 	// If ROMLMAP is set, force system to access ROM
   811 	if (!state.romlmap)
   812 		address |= 0x800000;
   814 	// Check access permissions
   815 	ACCESS_CHECK_WR(address, 16);
   817 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   818 		// ROM access
   819 	} else if (address <= 0x3FFFFF) {
   820 		// RAM access
   821 		uint32_t newAddr = mapAddr(address, true);
   822 		if (newAddr <= 0x1fffff)
   823 			WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
   824 		else
   825 			WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   826 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   827 		// I/O register space, zone A
   828 		switch (address & 0x0F0000) {
   829 			case 0x000000:				// Map RAM access
   830 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   831 				WR16(state.map, address, 0x7FF, value);
   832 				break;
   833 			case 0x020000:				// Video RAM
   834 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   835 				WR16(state.vram, address, 0x7FFF, value);
   836 				break;
   837 			default:
   838 				IoWrite(address, value, 16);
   839 		}
   840 	} else {
   841 		IoWrite(address, value, 16);
   842 	}
   843 }/*}}}*/
   845 /**
   846  * @brief Write M68K memory, 8-bit
   847  */
   848 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
   849 {
   850 	// If ROMLMAP is set, force system to access ROM
   851 	if (!state.romlmap)
   852 		address |= 0x800000;
   854 	// Check access permissions
   855 	ACCESS_CHECK_WR(address, 8);
   857 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   858 		// ROM access (read only!)
   859 	} else if (address <= 0x3FFFFF) {
   860 		// RAM access
   861 		uint32_t newAddr = mapAddr(address, true);
   862 		if (newAddr <= 0x1fffff)
   863 			WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
   864 		else
   865 			WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   866 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   867 		// I/O register space, zone A
   868 		switch (address & 0x0F0000) {
   869 			case 0x000000:				// Map RAM access
   870 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   871 				WR8(state.map, address, 0x7FF, value);
   872 				break;
   873 			case 0x020000:				// Video RAM
   874 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   875 				WR8(state.vram, address, 0x7FFF, value);
   876 				break;
   877 			default:
   878 				IoWrite(address, value, 8);
   879 		}
   880 	} else {
   881 		IoWrite(address, value, 8);
   882 	}
   883 }/*}}}*/
   886 // for the disassembler
   887 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
   888 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
   889 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }