Mon, 13 Dec 2010 03:00:43 +0000
disable floppy interrupts (to CPU), force HDD int flag on (i.e. command always complete)
1 #include <stdio.h>
2 #include <stdlib.h>
3 #include <stdint.h>
4 #include <stdbool.h>
5 #include "musashi/m68k.h"
6 #include "state.h"
7 #include "memory.h"
9 /******************
10 * Memory mapping
11 ******************/
13 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
15 uint32_t mapAddr(uint32_t addr, bool writing)
16 {
17 if (addr < 0x400000) {
18 // RAM access. Check against the Map RAM
19 // Start by getting the original page address
20 uint16_t page = (addr >> 12) & 0x3FF;
22 // Look it up in the map RAM and get the physical page address
23 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
25 // Update the Page Status bits
26 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
27 if (pagebits != 0) {
28 if (writing)
29 state.map[page*2] |= 0x60; // Page written to (dirty)
30 else
31 state.map[page*2] |= 0x40; // Page accessed but not written
32 }
34 // Return the address with the new physical page spliced in
35 return (new_page_addr << 12) + (addr & 0xFFF);
36 } else {
37 // I/O, VRAM or MapRAM space; no mapping is performed or required
38 // TODO: assert here?
39 return addr;
40 }
41 }
43 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)
44 {
45 // Are we in Supervisor mode?
46 if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
47 // Yes. We can do anything we like.
48 return MEM_ALLOWED;
50 // If we're here, then we must be in User mode.
51 // Check that the user didn't access memory outside of the RAM area
52 if (addr >= 0x400000)
53 return MEM_UIE;
55 // This leaves us with Page Fault checking. Get the page bits for this page.
56 uint16_t page = (addr >> 12) & 0x3FF;
57 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
59 // Check page is present
60 if ((pagebits & 0x03) == 0)
61 return MEM_PAGEFAULT;
63 // User attempt to access the kernel
64 // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
65 if (((addr >> 19) & 0x0F) == 0)
66 return MEM_KERNEL;
68 // Check page is write enabled
69 if ((pagebits & 0x04) == 0)
70 return MEM_PAGE_NO_WE;
72 // Page access allowed.
73 return MEM_ALLOWED;
74 }
76 #undef MAPRAM
79 /********************************************************
80 * m68k memory read/write support functions for Musashi
81 ********************************************************/
83 /**
84 * @brief Check memory access permissions for a write operation.
85 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
86 * gcc throws warnings when you have a return-with-value in a void
87 * function, even if the return-with-value is completely unreachable.
88 * Similarly it doesn't like it if you have a return without a value
89 * in a non-void function, even if it's impossible to ever reach the
90 * return-with-no-value. UGH!
91 */
92 #define ACCESS_CHECK_WR(address, bits) do { \
93 bool fault = false; \
94 /* MEM_STATUS st; */ \
95 switch (checkMemoryAccess(address, true)) { \
96 case MEM_ALLOWED: \
97 /* Access allowed */ \
98 break; \
99 case MEM_PAGEFAULT: \
100 /* Page fault */ \
101 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0); \
102 fault = true; \
103 break; \
104 case MEM_UIE: \
105 /* User access to memory above 4MB */ \
106 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0); \
107 fault = true; \
108 break; \
109 case MEM_KERNEL: \
110 case MEM_PAGE_NO_WE: \
111 /* kernel access or page not write enabled */ \
112 /* TODO: which regs need setting? */ \
113 fault = true; \
114 break; \
115 } \
116 \
117 if (fault) { \
118 if (bits >= 16) \
119 state.bsr0 = 0x7F00; \
120 else \
121 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
122 state.bsr0 |= (address >> 16); \
123 state.bsr1 = address & 0xffff; \
124 printf("ERR: BusError WR\n"); \
125 m68k_pulse_bus_error(); \
126 return; \
127 } \
128 } while (false)
130 /**
131 * @brief Check memory access permissions for a read operation.
132 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
133 * gcc throws warnings when you have a return-with-value in a void
134 * function, even if the return-with-value is completely unreachable.
135 * Similarly it doesn't like it if you have a return without a value
136 * in a non-void function, even if it's impossible to ever reach the
137 * return-with-no-value. UGH!
138 */
139 #define ACCESS_CHECK_RD(address, bits) do { \
140 bool fault = false; \
141 /* MEM_STATUS st; */ \
142 switch (checkMemoryAccess(address, false)) { \
143 case MEM_ALLOWED: \
144 /* Access allowed */ \
145 break; \
146 case MEM_PAGEFAULT: \
147 /* Page fault */ \
148 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0); \
149 fault = true; \
150 break; \
151 case MEM_UIE: \
152 /* User access to memory above 4MB */ \
153 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0); \
154 fault = true; \
155 break; \
156 case MEM_KERNEL: \
157 case MEM_PAGE_NO_WE: \
158 /* kernel access or page not write enabled */ \
159 /* TODO: which regs need setting? */ \
160 fault = true; \
161 break; \
162 } \
163 \
164 if (fault) { \
165 if (bits >= 16) \
166 state.bsr0 = 0x7F00; \
167 else \
168 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
169 state.bsr0 |= (address >> 16); \
170 state.bsr1 = address & 0xffff; \
171 printf("ERR: BusError RD\n"); \
172 m68k_pulse_bus_error(); \
173 return 0xFFFFFFFF; \
174 } \
175 } while (false)
177 // Logging macros
178 #define LOG_NOT_HANDLED_R(bits) \
179 do { \
180 if (!handled) \
181 printf("unhandled read%02d, addr=0x%08X\n", bits, address); \
182 } while (0);
184 #define LOG_NOT_HANDLED_W(bits) \
185 do { \
186 if (!handled) \
187 printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, value); \
188 } while (0);
190 /**
191 * @brief Read M68K memory, 32-bit
192 */
193 uint32_t m68k_read_memory_32(uint32_t address)
194 {
195 uint32_t data = 0xFFFFFFFF;
196 bool handled = false;
198 // If ROMLMAP is set, force system to access ROM
199 if (!state.romlmap)
200 address |= 0x800000;
202 // Check access permissions
203 ACCESS_CHECK_RD(address, 32);
205 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
206 // ROM access
207 data = RD32(state.rom, address, ROM_SIZE - 1);
208 handled = true;
209 } else if (address <= (state.ram_size - 1)) {
210 // RAM access
211 data = RD32(state.ram, mapAddr(address, false), state.ram_size - 1);
212 handled = true;
213 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
214 // I/O register space, zone A
215 switch (address & 0x0F0000) {
216 case 0x000000: // Map RAM access
217 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
218 data = RD32(state.map, address, 0x7FF);
219 handled = true;
220 break;
221 case 0x010000: // General Status Register
222 data = ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
223 handled = true;
224 break;
225 case 0x020000: // Video RAM
226 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
227 data = RD32(state.vram, address, 0x7FFF);
228 handled = true;
229 break;
230 case 0x030000: // Bus Status Register 0
231 data = ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
232 handled = true;
233 break;
234 case 0x040000: // Bus Status Register 1
235 data = ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
236 handled = true;
237 break;
238 case 0x050000: // Phone status
239 break;
240 case 0x060000: // DMA Count
241 // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
242 // Bit 14 is always unused, so leave it set
243 data = (state.dma_count & 0x3fff) | 0xC000;
244 handled = true;
245 break;
246 case 0x070000: // Line Printer Status Register
247 data = 0x00120012; // no parity error, no line printer error, no irqs from FDD or HDD
248 data |= (state.fdc_ctx.irql) ? 0x00080008 : 0; // FIXME! HACKHACKHACK! shouldn't peek inside FDC structs like this
249 break;
250 case 0x080000: // Real Time Clock
251 break;
252 case 0x090000: // Phone registers
253 switch (address & 0x0FF000) {
254 case 0x090000: // Handset relay
255 case 0x098000:
256 break;
257 case 0x091000: // Line select 2
258 case 0x099000:
259 break;
260 case 0x092000: // Hook relay 1
261 case 0x09A000:
262 break;
263 case 0x093000: // Hook relay 2
264 case 0x09B000:
265 break;
266 case 0x094000: // Line 1 hold
267 case 0x09C000:
268 break;
269 case 0x095000: // Line 2 hold
270 case 0x09D000:
271 break;
272 case 0x096000: // Line 1 A-lead
273 case 0x09E000:
274 break;
275 case 0x097000: // Line 2 A-lead
276 case 0x09F000:
277 break;
278 }
279 break;
280 case 0x0A0000: // Miscellaneous Control Register -- write only!
281 handled = true;
282 break;
283 case 0x0B0000: // TM/DIALWR
284 break;
285 case 0x0C0000: // Clear Status Register -- write only!
286 handled = true;
287 break;
288 case 0x0D0000: // DMA Address Register
289 break;
290 case 0x0E0000: // Disk Control Register
291 break;
292 case 0x0F0000: // Line Printer Data Register
293 break;
294 }
295 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
296 // I/O register space, zone B
297 switch (address & 0xF00000) {
298 case 0xC00000: // Expansion slots
299 case 0xD00000:
300 switch (address & 0xFC0000) {
301 case 0xC00000: // Expansion slot 0
302 case 0xC40000: // Expansion slot 1
303 case 0xC80000: // Expansion slot 2
304 case 0xCC0000: // Expansion slot 3
305 case 0xD00000: // Expansion slot 4
306 case 0xD40000: // Expansion slot 5
307 case 0xD80000: // Expansion slot 6
308 case 0xDC0000: // Expansion slot 7
309 fprintf(stderr, "NOTE: RD32 from expansion card space, addr=0x%08X\n", address);
310 break;
311 }
312 break;
313 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
314 case 0xF00000:
315 switch (address & 0x070000) {
316 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
317 break;
318 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
319 data = wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
320 printf("WD279X: rd32 %02X ==> %02X\n", (address >> 1) & 3, data);
321 handled = true;
322 break;
323 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
324 break;
325 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
326 break;
327 case 0x040000: // [ef][4c]xxxx ==> General Control Register
328 switch (address & 0x077000) {
329 case 0x040000: // [ef][4c][08]xxx ==> EE
330 case 0x041000: // [ef][4c][19]xxx ==> PIE
331 case 0x042000: // [ef][4c][2A]xxx ==> BP
332 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
333 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
334 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
335 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
336 // All write-only registers... TODO: bus error?
337 handled = true;
338 break;
339 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
340 break;
341 }
342 break;
343 case 0x050000: // [ef][5d]xxxx ==> 8274
344 break;
345 case 0x060000: // [ef][6e]xxxx ==> Control regs
346 switch (address & 0x07F000) {
347 default:
348 break;
349 }
350 break;
351 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
352 break;
353 }
354 }
355 }
357 LOG_NOT_HANDLED_R(32);
358 return data;
359 }
361 /**
362 * @brief Read M68K memory, 16-bit
363 */
364 uint32_t m68k_read_memory_16(uint32_t address)
365 {
366 uint16_t data = 0xFFFF;
367 bool handled = false;
369 // If ROMLMAP is set, force system to access ROM
370 if (!state.romlmap)
371 address |= 0x800000;
373 // Check access permissions
374 ACCESS_CHECK_RD(address, 16);
376 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
377 // ROM access
378 data = RD16(state.rom, address, ROM_SIZE - 1);
379 handled = true;
380 } else if (address <= (state.ram_size - 1)) {
381 // RAM access
382 data = RD16(state.ram, mapAddr(address, false), state.ram_size - 1);
383 handled = true;
384 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
385 // I/O register space, zone A
386 switch (address & 0x0F0000) {
387 case 0x000000: // Map RAM access
388 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
389 data = RD16(state.map, address, 0x7FF);
390 handled = true;
391 break;
392 case 0x010000: // General Status Register
393 data = state.genstat;
394 handled = true;
395 break;
396 case 0x020000: // Video RAM
397 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
398 data = RD16(state.vram, address, 0x7FFF);
399 handled = true;
400 break;
401 case 0x030000: // Bus Status Register 0
402 data = state.bsr0;
403 handled = true;
404 break;
405 case 0x040000: // Bus Status Register 1
406 data = state.bsr1;
407 handled = true;
408 break;
409 case 0x050000: // Phone status
410 break;
411 case 0x060000: // DMA Count
412 // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
413 // Bit 14 is always unused, so leave it set
414 data = (state.dma_count & 0x3fff) | 0xC000;
415 handled = true;
416 break;
417 case 0x070000: // Line Printer Status Register
418 data = 0x0012; // no parity error, no line printer error, no irqs from FDD or HDD
419 data |= (state.fdc_ctx.irql) ? 0x0008 : 0; // FIXME! HACKHACKHACK! shouldn't peek inside FDC structs like this
420 break;
421 case 0x080000: // Real Time Clock
422 break;
423 case 0x090000: // Phone registers
424 switch (address & 0x0FF000) {
425 case 0x090000: // Handset relay
426 case 0x098000:
427 break;
428 case 0x091000: // Line select 2
429 case 0x099000:
430 break;
431 case 0x092000: // Hook relay 1
432 case 0x09A000:
433 break;
434 case 0x093000: // Hook relay 2
435 case 0x09B000:
436 break;
437 case 0x094000: // Line 1 hold
438 case 0x09C000:
439 break;
440 case 0x095000: // Line 2 hold
441 case 0x09D000:
442 break;
443 case 0x096000: // Line 1 A-lead
444 case 0x09E000:
445 break;
446 case 0x097000: // Line 2 A-lead
447 case 0x09F000:
448 break;
449 }
450 break;
451 case 0x0A0000: // Miscellaneous Control Register -- write only!
452 handled = true;
453 break;
454 case 0x0B0000: // TM/DIALWR
455 break;
456 case 0x0C0000: // Clear Status Register -- write only!
457 handled = true;
458 break;
459 case 0x0D0000: // DMA Address Register
460 break;
461 case 0x0E0000: // Disk Control Register
462 break;
463 case 0x0F0000: // Line Printer Data Register
464 break;
465 }
466 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
467 // I/O register space, zone B
468 switch (address & 0xF00000) {
469 case 0xC00000: // Expansion slots
470 case 0xD00000:
471 switch (address & 0xFC0000) {
472 case 0xC00000: // Expansion slot 0
473 case 0xC40000: // Expansion slot 1
474 case 0xC80000: // Expansion slot 2
475 case 0xCC0000: // Expansion slot 3
476 case 0xD00000: // Expansion slot 4
477 case 0xD40000: // Expansion slot 5
478 case 0xD80000: // Expansion slot 6
479 case 0xDC0000: // Expansion slot 7
480 fprintf(stderr, "NOTE: RD16 from expansion card space, addr=0x%08X\n", address);
481 break;
482 }
483 break;
484 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
485 case 0xF00000:
486 switch (address & 0x070000) {
487 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
488 break;
489 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
490 data = wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
491 printf("WD279X: rd16 %02X ==> %02X\n", (address >> 1) & 3, data);
492 handled = true;
493 break;
494 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
495 break;
496 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
497 break;
498 case 0x040000: // [ef][4c]xxxx ==> General Control Register
499 switch (address & 0x077000) {
500 case 0x040000: // [ef][4c][08]xxx ==> EE
501 case 0x041000: // [ef][4c][19]xxx ==> PIE
502 case 0x042000: // [ef][4c][2A]xxx ==> BP
503 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
504 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
505 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
506 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
507 // All write-only registers... TODO: bus error?
508 handled = true;
509 break;
510 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
511 break;
512 }
513 break;
514 case 0x050000: // [ef][5d]xxxx ==> 8274
515 break;
516 case 0x060000: // [ef][6e]xxxx ==> Control regs
517 switch (address & 0x07F000) {
518 default:
519 break;
520 }
521 break;
522 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
523 break;
524 }
525 }
526 }
528 LOG_NOT_HANDLED_R(16);
529 return data;
530 }
532 /**
533 * @brief Read M68K memory, 8-bit
534 */
535 uint32_t m68k_read_memory_8(uint32_t address)
536 {
537 uint8_t data = 0xFF;
538 bool handled = false;
540 // If ROMLMAP is set, force system to access ROM
541 if (!state.romlmap)
542 address |= 0x800000;
544 // Check access permissions
545 ACCESS_CHECK_RD(address, 8);
547 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
548 // ROM access
549 data = RD8(state.rom, address, ROM_SIZE - 1);
550 handled = true;
551 } else if (address <= (state.ram_size - 1)) {
552 // RAM access
553 data = RD8(state.ram, mapAddr(address, false), state.ram_size - 1);
554 handled = true;
555 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
556 // I/O register space, zone A
557 switch (address & 0x0F0000) {
558 case 0x000000: // Map RAM access
559 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
560 data = RD8(state.map, address, 0x7FF);
561 handled = true;
562 break;
563 case 0x010000: // General Status Register
564 if ((address & 1) == 0)
565 data = (state.genstat >> 8) & 0xff;
566 else
567 data = (state.genstat) & 0xff;
568 handled = true;
569 break;
570 case 0x020000: // Video RAM
571 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
572 data = RD8(state.vram, address, 0x7FFF);
573 handled = true;
574 break;
575 case 0x030000: // Bus Status Register 0
576 if ((address & 1) == 0)
577 data = (state.bsr0 >> 8) & 0xff;
578 else
579 data = (state.bsr0) & 0xff;
580 handled = true;
581 break;
582 case 0x040000: // Bus Status Register 1
583 if ((address & 1) == 0)
584 data = (state.bsr1 >> 8) & 0xff;
585 else
586 data = (state.bsr1) & 0xff;
587 handled = true;
588 break;
589 case 0x050000: // Phone status
590 break;
591 case 0x060000: // DMA Count
592 // TODO: how to handle this in 8bit mode?
593 break;
594 case 0x070000: // Line Printer Status Register
595 printf("\tLPSR RD8 fdc irql=%d, irqe=%d\n", state.fdc_ctx.irql, state.fdc_ctx.irqe);
596 if (address & 1) {
597 data = 0x12; // no parity error, no line printer error, no irqs from FDD or HDD
598 data |= (state.fdc_ctx.irql) ? 0x08 : 0; // FIXME! HACKHACKHACK! shouldn't peek inside FDC structs like this
599 data |= 0x04; // HDD interrupt, i.e. command complete -- HACKHACKHACK!
600 } else {
601 data = 0;
602 }
603 break;
604 case 0x080000: // Real Time Clock
605 break;
606 case 0x090000: // Phone registers
607 switch (address & 0x0FF000) {
608 case 0x090000: // Handset relay
609 case 0x098000:
610 break;
611 case 0x091000: // Line select 2
612 case 0x099000:
613 break;
614 case 0x092000: // Hook relay 1
615 case 0x09A000:
616 break;
617 case 0x093000: // Hook relay 2
618 case 0x09B000:
619 break;
620 case 0x094000: // Line 1 hold
621 case 0x09C000:
622 break;
623 case 0x095000: // Line 2 hold
624 case 0x09D000:
625 break;
626 case 0x096000: // Line 1 A-lead
627 case 0x09E000:
628 break;
629 case 0x097000: // Line 2 A-lead
630 case 0x09F000:
631 break;
632 }
633 break;
634 case 0x0A0000: // Miscellaneous Control Register -- write only!
635 handled = true;
636 break;
637 case 0x0B0000: // TM/DIALWR
638 break;
639 case 0x0C0000: // Clear Status Register -- write only!
640 handled = true;
641 break;
642 case 0x0D0000: // DMA Address Register
643 break;
644 case 0x0E0000: // Disk Control Register
645 break;
646 case 0x0F0000: // Line Printer Data Register
647 break;
648 }
649 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
650 // I/O register space, zone B
651 switch (address & 0xF00000) {
652 case 0xC00000: // Expansion slots
653 case 0xD00000:
654 switch (address & 0xFC0000) {
655 case 0xC00000: // Expansion slot 0
656 case 0xC40000: // Expansion slot 1
657 case 0xC80000: // Expansion slot 2
658 case 0xCC0000: // Expansion slot 3
659 case 0xD00000: // Expansion slot 4
660 case 0xD40000: // Expansion slot 5
661 case 0xD80000: // Expansion slot 6
662 case 0xDC0000: // Expansion slot 7
663 fprintf(stderr, "NOTE: RD8 from expansion card space, addr=0x%08X\n", address);
664 break;
665 }
666 break;
667 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
668 case 0xF00000:
669 switch (address & 0x070000) {
670 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
671 break;
672 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
673 data = wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
674 printf("WD279X: rd8 %02X ==> %02X\n", (address >> 1) & 3, data);
675 handled = true;
676 break;
677 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
678 break;
679 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
680 break;
681 case 0x040000: // [ef][4c]xxxx ==> General Control Register
682 switch (address & 0x077000) {
683 case 0x040000: // [ef][4c][08]xxx ==> EE
684 case 0x041000: // [ef][4c][19]xxx ==> PIE
685 case 0x042000: // [ef][4c][2A]xxx ==> BP
686 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
687 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
688 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
689 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
690 // All write-only registers... TODO: bus error?
691 handled = true;
692 break;
693 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
694 break;
695 }
696 case 0x050000: // [ef][5d]xxxx ==> 8274
697 break;
698 case 0x060000: // [ef][6e]xxxx ==> Control regs
699 switch (address & 0x07F000) {
700 default:
701 break;
702 }
703 break;
704 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
705 break;
706 }
707 }
708 }
710 LOG_NOT_HANDLED_R(8);
712 return data;
713 }
715 /**
716 * @brief Write M68K memory, 32-bit
717 */
718 void m68k_write_memory_32(uint32_t address, uint32_t value)
719 {
720 bool handled = false;
722 // If ROMLMAP is set, force system to access ROM
723 if (!state.romlmap)
724 address |= 0x800000;
726 // Check access permissions
727 ACCESS_CHECK_WR(address, 32);
729 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
730 // ROM access
731 handled = true;
732 } else if (address <= (state.ram_size - 1)) {
733 // RAM access
734 WR32(state.ram, mapAddr(address, false), state.ram_size - 1, value);
735 handled = true;
736 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
737 // I/O register space, zone A
738 switch (address & 0x0F0000) {
739 case 0x000000: // Map RAM access
740 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
741 WR32(state.map, address, 0x7FF, value);
742 handled = true;
743 break;
744 case 0x010000: // General Status Register
745 state.genstat = (value & 0xffff);
746 handled = true;
747 break;
748 case 0x020000: // Video RAM
749 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
750 WR32(state.vram, address, 0x7FFF, value);
751 handled = true;
752 break;
753 case 0x030000: // Bus Status Register 0
754 break;
755 case 0x040000: // Bus Status Register 1
756 break;
757 case 0x050000: // Phone status
758 break;
759 case 0x060000: // DMA Count
760 printf("WR32 dmacount %08X\n", value);
761 state.dma_count = (value & 0x3FFF);
762 state.idmarw = ((value & 0x4000) == 0x4000);
763 state.dmaen = ((value & 0x8000) == 0x8000);
764 printf("\tcount %04X, idmarw %d, dmaen %d\n", state.dma_count, state.idmarw, state.dmaen);
765 // This handles the "dummy DMA transfer" mentioned in the docs
766 // TODO: access check, peripheral access
767 if (!state.idmarw)
768 WR32(state.ram, mapAddr(address, false), state.ram_size - 1, 0xDEAD);
769 state.dma_count++;
770 handled = true;
771 break;
772 case 0x070000: // Line Printer Status Register
773 break;
774 case 0x080000: // Real Time Clock
775 break;
776 case 0x090000: // Phone registers
777 switch (address & 0x0FF000) {
778 case 0x090000: // Handset relay
779 case 0x098000:
780 break;
781 case 0x091000: // Line select 2
782 case 0x099000:
783 break;
784 case 0x092000: // Hook relay 1
785 case 0x09A000:
786 break;
787 case 0x093000: // Hook relay 2
788 case 0x09B000:
789 break;
790 case 0x094000: // Line 1 hold
791 case 0x09C000:
792 break;
793 case 0x095000: // Line 2 hold
794 case 0x09D000:
795 break;
796 case 0x096000: // Line 1 A-lead
797 case 0x09E000:
798 break;
799 case 0x097000: // Line 2 A-lead
800 case 0x09F000:
801 break;
802 }
803 break;
804 case 0x0A0000: // Miscellaneous Control Register
805 // TODO: handle the ctrl bits properly
806 // TODO: &0x8000 --> dismiss 60hz intr
807 state.dma_reading = (value & 0x4000);
808 state.leds = (~value & 0xF00) >> 8;
809 printf("LEDs: %s %s %s %s\n",
810 (state.leds & 8) ? "R" : "-",
811 (state.leds & 4) ? "G" : "-",
812 (state.leds & 2) ? "Y" : "-",
813 (state.leds & 1) ? "R" : "-");
814 handled = true;
815 break;
816 case 0x0B0000: // TM/DIALWR
817 break;
818 case 0x0C0000: // Clear Status Register
819 state.genstat = 0xFFFF;
820 state.bsr0 = 0xFFFF;
821 state.bsr1 = 0xFFFF;
822 handled = true;
823 break;
824 case 0x0D0000: // DMA Address Register
825 if (address & 0x004000) {
826 // A14 high -- set most significant bits
827 state.dma_address = (state.dma_address & 0xff) | ((address & 0x3fff) << 7);
828 } else {
829 // A14 low -- set least significant bits
830 state.dma_address = (state.dma_address & 0x3fff00) | (address & 0xff);
831 }
832 printf("WR DMA_ADDR, now %08X\n", state.dma_address);
833 handled = true;
834 break;
835 case 0x0E0000: // Disk Control Register
836 // B7 = FDD controller reset
837 if ((value & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
838 // B6 = drive 0 select -- TODO
839 // B5 = motor enable -- TODO
840 // B4 = HDD controller reset -- TODO
841 // B3 = HDD0 select -- TODO
842 // B2,1,0 = HDD0 head select
843 handled = true;
844 break;
845 case 0x0F0000: // Line Printer Data Register
846 break;
847 }
848 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
849 // I/O register space, zone B
850 switch (address & 0xF00000) {
851 case 0xC00000: // Expansion slots
852 case 0xD00000:
853 switch (address & 0xFC0000) {
854 case 0xC00000: // Expansion slot 0
855 case 0xC40000: // Expansion slot 1
856 case 0xC80000: // Expansion slot 2
857 case 0xCC0000: // Expansion slot 3
858 case 0xD00000: // Expansion slot 4
859 case 0xD40000: // Expansion slot 5
860 case 0xD80000: // Expansion slot 6
861 case 0xDC0000: // Expansion slot 7
862 fprintf(stderr, "NOTE: WR32 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
863 handled = true;
864 break;
865 }
866 break;
867 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
868 case 0xF00000:
869 switch (address & 0x070000) {
870 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
871 break;
872 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
873 printf("WD279X: wr32 %02X ==> %02X\n", (address >> 1) & 3, value);
874 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, value);
875 handled = true;
876 break;
877 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
878 break;
879 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
880 break;
881 case 0x040000: // [ef][4c]xxxx ==> General Control Register
882 switch (address & 0x077000) {
883 case 0x040000: // [ef][4c][08]xxx ==> EE
884 break;
885 case 0x041000: // [ef][4c][19]xxx ==> PIE
886 state.pie = ((value & 0x8000) == 0x8000);
887 handled = true;
888 break;
889 case 0x042000: // [ef][4c][2A]xxx ==> BP
890 break;
891 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
892 state.romlmap = ((value & 0x8000) == 0x8000);
893 handled = true;
894 break;
895 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
896 break;
897 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
898 break;
899 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
900 break;
901 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
902 break;
903 }
904 case 0x050000: // [ef][5d]xxxx ==> 8274
905 break;
906 case 0x060000: // [ef][6e]xxxx ==> Control regs
907 switch (address & 0x07F000) {
908 default:
909 break;
910 }
911 break;
912 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
913 break;
914 }
915 }
916 }
918 LOG_NOT_HANDLED_W(32);
919 }
921 /**
922 * @brief Write M68K memory, 16-bit
923 */
924 void m68k_write_memory_16(uint32_t address, uint32_t value)
925 {
926 bool handled = false;
928 // If ROMLMAP is set, force system to access ROM
929 if (!state.romlmap)
930 address |= 0x800000;
932 // Check access permissions
933 ACCESS_CHECK_WR(address, 16);
935 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
936 // ROM access
937 handled = true;
938 } else if (address <= (state.ram_size - 1)) {
939 // RAM access
940 WR16(state.ram, mapAddr(address, false), state.ram_size - 1, value);
941 handled = true;
942 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
943 // I/O register space, zone A
944 switch (address & 0x0F0000) {
945 case 0x000000: // Map RAM access
946 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
947 WR16(state.map, address, 0x7FF, value);
948 handled = true;
949 break;
950 case 0x010000: // General Status Register (read only)
951 handled = true;
952 break;
953 case 0x020000: // Video RAM
954 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
955 WR16(state.vram, address, 0x7FFF, value);
956 handled = true;
957 break;
958 case 0x030000: // Bus Status Register 0 (read only)
959 handled = true;
960 break;
961 case 0x040000: // Bus Status Register 1 (read only)
962 handled = true;
963 break;
964 case 0x050000: // Phone status
965 break;
966 case 0x060000: // DMA Count
967 printf("WR16 dmacount %08X\n", value);
968 state.dma_count = (value & 0x3FFF);
969 state.idmarw = ((value & 0x4000) == 0x4000);
970 state.dmaen = ((value & 0x8000) == 0x8000);
971 printf("\tcount %04X, idmarw %d, dmaen %d\n", state.dma_count, state.idmarw, state.dmaen);
972 // This handles the "dummy DMA transfer" mentioned in the docs
973 // TODO: access check, peripheral access
974 if (!state.idmarw)
975 WR32(state.ram, mapAddr(address, false), state.ram_size - 1, 0xDEAD);
976 state.dma_count++;
977 handled = true;
978 break;
979 case 0x070000: // Line Printer Status Register
980 break;
981 case 0x080000: // Real Time Clock
982 break;
983 case 0x090000: // Phone registers
984 switch (address & 0x0FF000) {
985 case 0x090000: // Handset relay
986 case 0x098000:
987 break;
988 case 0x091000: // Line select 2
989 case 0x099000:
990 break;
991 case 0x092000: // Hook relay 1
992 case 0x09A000:
993 break;
994 case 0x093000: // Hook relay 2
995 case 0x09B000:
996 break;
997 case 0x094000: // Line 1 hold
998 case 0x09C000:
999 break;
1000 case 0x095000: // Line 2 hold
1001 case 0x09D000:
1002 break;
1003 case 0x096000: // Line 1 A-lead
1004 case 0x09E000:
1005 break;
1006 case 0x097000: // Line 2 A-lead
1007 case 0x09F000:
1008 break;
1009 }
1010 break;
1011 case 0x0A0000: // Miscellaneous Control Register
1012 // TODO: handle the ctrl bits properly
1013 // TODO: &0x8000 --> dismiss 60hz intr
1014 state.dma_reading = (value & 0x4000);
1015 state.leds = (~value & 0xF00) >> 8;
1016 printf("LEDs: %s %s %s %s\n",
1017 (state.leds & 8) ? "R" : "-",
1018 (state.leds & 4) ? "G" : "-",
1019 (state.leds & 2) ? "Y" : "-",
1020 (state.leds & 1) ? "R" : "-");
1021 handled = true;
1022 break;
1023 case 0x0B0000: // TM/DIALWR
1024 break;
1025 case 0x0C0000: // Clear Status Register
1026 state.genstat = 0xFFFF;
1027 state.bsr0 = 0xFFFF;
1028 state.bsr1 = 0xFFFF;
1029 handled = true;
1030 break;
1031 case 0x0D0000: // DMA Address Register
1032 if (address & 0x004000) {
1033 // A14 high -- set most significant bits
1034 state.dma_address = (state.dma_address & 0xff) | ((address & 0x3fff) << 7);
1035 } else {
1036 // A14 low -- set least significant bits
1037 state.dma_address = (state.dma_address & 0x3fff00) | (address & 0xff);
1038 }
1039 printf("WR DMA_ADDR, now %08X\n", state.dma_address);
1040 handled = true;
1041 break;
1042 case 0x0E0000: // Disk Control Register
1043 // B7 = FDD controller reset
1044 if ((value & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
1045 // B6 = drive 0 select -- TODO
1046 // B5 = motor enable -- TODO
1047 // B4 = HDD controller reset -- TODO
1048 // B3 = HDD0 select -- TODO
1049 // B2,1,0 = HDD0 head select
1050 handled = true;
1051 break;
1052 case 0x0F0000: // Line Printer Data Register
1053 break;
1054 }
1055 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
1056 // I/O register space, zone B
1057 switch (address & 0xF00000) {
1058 case 0xC00000: // Expansion slots
1059 case 0xD00000:
1060 switch (address & 0xFC0000) {
1061 case 0xC00000: // Expansion slot 0
1062 case 0xC40000: // Expansion slot 1
1063 case 0xC80000: // Expansion slot 2
1064 case 0xCC0000: // Expansion slot 3
1065 case 0xD00000: // Expansion slot 4
1066 case 0xD40000: // Expansion slot 5
1067 case 0xD80000: // Expansion slot 6
1068 case 0xDC0000: // Expansion slot 7
1069 fprintf(stderr, "NOTE: WR16 to expansion card space, addr=0x%08X, data=0x%04X\n", address, value);
1070 break;
1071 }
1072 break;
1073 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
1074 case 0xF00000:
1075 switch (address & 0x070000) {
1076 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
1077 break;
1078 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
1079 printf("WD279X: wr16 %02X ==> %02X\n", (address >> 1) & 3, value);
1080 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, value);
1081 handled = true;
1082 break;
1083 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
1084 break;
1085 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
1086 break;
1087 case 0x040000: // [ef][4c]xxxx ==> General Control Register
1088 switch (address & 0x077000) {
1089 case 0x040000: // [ef][4c][08]xxx ==> EE
1090 break;
1091 case 0x041000: // [ef][4c][19]xxx ==> PIE
1092 state.pie = ((value & 0x8000) == 0x8000);
1093 handled = true;
1094 break;
1095 case 0x042000: // [ef][4c][2A]xxx ==> BP
1096 break;
1097 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
1098 state.romlmap = ((value & 0x8000) == 0x8000);
1099 handled = true;
1100 break;
1101 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
1102 break;
1103 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
1104 break;
1105 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
1106 break;
1107 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
1108 break;
1109 }
1110 case 0x050000: // [ef][5d]xxxx ==> 8274
1111 break;
1112 case 0x060000: // [ef][6e]xxxx ==> Control regs
1113 switch (address & 0x07F000) {
1114 default:
1115 break;
1116 }
1117 break;
1118 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
1119 break;
1120 }
1121 }
1122 }
1124 LOG_NOT_HANDLED_W(16);
1125 }
1127 /**
1128 * @brief Write M68K memory, 8-bit
1129 */
1130 void m68k_write_memory_8(uint32_t address, uint32_t value)
1131 {
1132 bool handled = false;
1134 // If ROMLMAP is set, force system to access ROM
1135 if (!state.romlmap)
1136 address |= 0x800000;
1138 // Check access permissions
1139 ACCESS_CHECK_WR(address, 8);
1141 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
1142 // ROM access (read only!)
1143 handled = true;
1144 } else if (address <= (state.ram_size - 1)) {
1145 // RAM access
1146 WR8(state.ram, mapAddr(address, false), state.ram_size - 1, value);
1147 handled = true;
1148 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
1149 // I/O register space, zone A
1150 switch (address & 0x0F0000) {
1151 case 0x000000: // Map RAM access
1152 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=%08X, data=%02X\n", address, value);
1153 WR8(state.map, address, 0x7FF, value);
1154 handled = true;
1155 break;
1156 case 0x010000: // General Status Register
1157 handled = true;
1158 break;
1159 case 0x020000: // Video RAM
1160 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=%08X, data=0x%02X\n", address, value);
1161 WR8(state.vram, address, 0x7FFF, value);
1162 handled = true;
1163 break;
1164 case 0x030000: // Bus Status Register 0
1165 handled = true;
1166 break;
1167 case 0x040000: // Bus Status Register 1
1168 handled = true;
1169 break;
1170 case 0x050000: // Phone status
1171 break;
1172 case 0x060000: // DMA Count
1173 // TODO: how to handle this in 8bit mode?
1174 break;
1175 case 0x070000: // Line Printer Status Register
1176 break;
1177 case 0x080000: // Real Time Clock
1178 break;
1179 case 0x090000: // Phone registers
1180 switch (address & 0x0FF000) {
1181 case 0x090000: // Handset relay
1182 case 0x098000:
1183 break;
1184 case 0x091000: // Line select 2
1185 case 0x099000:
1186 break;
1187 case 0x092000: // Hook relay 1
1188 case 0x09A000:
1189 break;
1190 case 0x093000: // Hook relay 2
1191 case 0x09B000:
1192 break;
1193 case 0x094000: // Line 1 hold
1194 case 0x09C000:
1195 break;
1196 case 0x095000: // Line 2 hold
1197 case 0x09D000:
1198 break;
1199 case 0x096000: // Line 1 A-lead
1200 case 0x09E000:
1201 break;
1202 case 0x097000: // Line 2 A-lead
1203 case 0x09F000:
1204 break;
1205 }
1206 break;
1207 case 0x0A0000: // Miscellaneous Control Register
1208 // TODO: how to handle this in 8bit mode?
1209 /*
1210 // TODO: handle the ctrl bits properly
1211 if ((address & 1) == 0) {
1212 // low byte
1213 } else {
1214 // hight byte
1215 // TODO: &0x8000 --> dismiss 60hz intr
1216 state.dma_reading = (value & 0x40);
1217 state.leds = (~value & 0xF);
1218 }
1219 printf("LEDs: %s %s %s %s\n",
1220 (state.leds & 8) ? "R" : "-",
1221 (state.leds & 4) ? "G" : "-",
1222 (state.leds & 2) ? "Y" : "-",
1223 (state.leds & 1) ? "R" : "-");
1224 handled = true;
1225 */
1226 break;
1227 case 0x0B0000: // TM/DIALWR
1228 break;
1229 case 0x0C0000: // Clear Status Register
1230 state.genstat = 0xFFFF;
1231 state.bsr0 = 0xFFFF;
1232 state.bsr1 = 0xFFFF;
1233 handled = true;
1234 break;
1235 case 0x0D0000: // DMA Address Register
1236 if (address & 0x004000) {
1237 // A14 high -- set most significant bits
1238 state.dma_address = (state.dma_address & 0xff) | ((address & 0x3fff) << 7);
1239 } else {
1240 // A14 low -- set least significant bits
1241 state.dma_address = (state.dma_address & 0x3fff00) | (address & 0xff);
1242 }
1243 printf("WR DMA_ADDR, now %08X\n", state.dma_address);
1244 handled = true;
1245 break;
1246 case 0x0E0000: // Disk Control Register
1247 // B7 = FDD controller reset
1248 if ((value & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
1249 // B6 = drive 0 select -- TODO
1250 // B5 = motor enable -- TODO
1251 // B4 = HDD controller reset -- TODO
1252 // B3 = HDD0 select -- TODO
1253 // B2,1,0 = HDD0 head select
1254 handled = true;
1255 break;
1256 case 0x0F0000: // Line Printer Data Register
1257 break;
1258 }
1259 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
1260 // I/O register space, zone B
1261 switch (address & 0xF00000) {
1262 case 0xC00000: // Expansion slots
1263 case 0xD00000:
1264 switch (address & 0xFC0000) {
1265 case 0xC00000: // Expansion slot 0
1266 case 0xC40000: // Expansion slot 1
1267 case 0xC80000: // Expansion slot 2
1268 case 0xCC0000: // Expansion slot 3
1269 case 0xD00000: // Expansion slot 4
1270 case 0xD40000: // Expansion slot 5
1271 case 0xD80000: // Expansion slot 6
1272 case 0xDC0000: // Expansion slot 7
1273 fprintf(stderr, "NOTE: WR8 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
1274 break;
1275 }
1276 break;
1277 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
1278 case 0xF00000:
1279 switch (address & 0x070000) {
1280 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
1281 break;
1282 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
1283 printf("WD279X: wr8 %02X ==> %02X\n", (address >> 1) & 3, value);
1284 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, value);
1285 handled = true;
1286 break;
1287 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
1288 break;
1289 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
1290 break;
1291 case 0x040000: // [ef][4c]xxxx ==> General Control Register
1292 switch (address & 0x077000) {
1293 case 0x040000: // [ef][4c][08]xxx ==> EE
1294 break;
1295 case 0x041000: // [ef][4c][19]xxx ==> PIE
1296 if ((address & 1) == 0)
1297 state.pie = ((value & 0x80) == 0x80);
1298 handled = true;
1299 break;
1300 case 0x042000: // [ef][4c][2A]xxx ==> BP
1301 break;
1302 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
1303 if ((address & 1) == 0)
1304 state.romlmap = ((value & 0x80) == 0x80);
1305 handled = true;
1306 break;
1307 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
1308 break;
1309 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
1310 break;
1311 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
1312 break;
1313 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
1314 break;
1315 }
1316 case 0x050000: // [ef][5d]xxxx ==> 8274
1317 break;
1318 case 0x060000: // [ef][6e]xxxx ==> Control regs
1319 switch (address & 0x07F000) {
1320 default:
1321 break;
1322 }
1323 break;
1324 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
1325 break;
1326 default:
1327 fprintf(stderr, "NOTE: WR8 to undefined E/F-block space, addr=0x%08X, data=0x%08X\n", address, value);
1328 break;
1329 }
1330 }
1331 }
1333 LOG_NOT_HANDLED_W(8);
1334 }
1337 // for the disassembler
1338 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
1339 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
1340 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }