src/memory.c

Sun, 12 Dec 2010 23:47:35 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 12 Dec 2010 23:47:35 +0000
changeset 55
ba6b8e570062
parent 53
e1693c4b8a0c
child 56
b3f309d46e97
permissions
-rw-r--r--

improve error and DMA handling

     1 #include <stdio.h>
     2 #include <stdlib.h>
     3 #include <stdint.h>
     4 #include <stdbool.h>
     5 #include "musashi/m68k.h"
     6 #include "state.h"
     7 #include "memory.h"
     9 /******************
    10  * Memory mapping
    11  ******************/
    13 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
    15 uint32_t mapAddr(uint32_t addr, bool writing)
    16 {
    17 	if (addr < 0x400000) {
    18 		// RAM access. Check against the Map RAM
    19 		// Start by getting the original page address
    20 		uint16_t page = (addr >> 12) & 0x3FF;
    22 		// Look it up in the map RAM and get the physical page address
    23 		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
    25 		// Update the Page Status bits
    26 		uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
    27 		if (pagebits != 0) {
    28 			if (writing)
    29 				state.map[page*2] |= 0x60;		// Page written to (dirty)
    30 			else
    31 				state.map[page*2] |= 0x40;		// Page accessed but not written
    32 		}
    34 		// Return the address with the new physical page spliced in
    35 		return (new_page_addr << 12) + (addr & 0xFFF);
    36 	} else {
    37 		// I/O, VRAM or MapRAM space; no mapping is performed or required
    38 		// TODO: assert here?
    39 		return addr;
    40 	}
    41 }
    43 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)
    44 {
    45 	// Are we in Supervisor mode?
    46 	if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
    47 		// Yes. We can do anything we like.
    48 		return MEM_ALLOWED;
    50 	// If we're here, then we must be in User mode.
    51 	// Check that the user didn't access memory outside of the RAM area
    52 	if (addr >= 0x400000)
    53 		return MEM_UIE;
    55 	// This leaves us with Page Fault checking. Get the page bits for this page.
    56 	uint16_t page = (addr >> 12) & 0x3FF;
    57 	uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
    59 	// Check page is present
    60 	if ((pagebits & 0x03) == 0)
    61 		return MEM_PAGEFAULT;
    63 	// User attempt to access the kernel
    64 	// A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
    65 	if (((addr >> 19) & 0x0F) == 0)
    66 		return MEM_KERNEL;
    68 	// Check page is write enabled
    69 	if ((pagebits & 0x04) == 0)
    70 		return MEM_PAGE_NO_WE;
    72 	// Page access allowed.
    73 	return MEM_ALLOWED;
    74 }
    76 #undef MAPRAM
    79 /********************************************************
    80  * m68k memory read/write support functions for Musashi
    81  ********************************************************/
    83 /**
    84  * @brief	Check memory access permissions for a write operation.
    85  * @note	This used to be a single macro (merged with ACCESS_CHECK_RD), but
    86  * 			gcc throws warnings when you have a return-with-value in a void
    87  * 			function, even if the return-with-value is completely unreachable.
    88  * 			Similarly it doesn't like it if you have a return without a value
    89  * 			in a non-void function, even if it's impossible to ever reach the
    90  * 			return-with-no-value. UGH!
    91  */
    92 #define ACCESS_CHECK_WR(address, bits) do {							\
    93 		bool fault = false;											\
    94 		/* MEM_STATUS st; */										\
    95 		switch (checkMemoryAccess(address, true)) {					\
    96 			case MEM_ALLOWED:										\
    97 				/* Access allowed */								\
    98 				break;												\
    99 			case MEM_PAGEFAULT:										\
   100 				/* Page fault */									\
   101 				state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0);	\
   102 				fault = true;										\
   103 				break;												\
   104 			case MEM_UIE:											\
   105 				/* User access to memory above 4MB */				\
   106 				state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0);	\
   107 				fault = true;										\
   108 				break;												\
   109 			case MEM_KERNEL:										\
   110 			case MEM_PAGE_NO_WE:									\
   111 				/* kernel access or page not write enabled */		\
   112 				/* TODO: which regs need setting? */				\
   113 				fault = true;										\
   114 				break;												\
   115 		}															\
   116 																	\
   117 		if (fault) {												\
   118 			if (bits >= 16)											\
   119 				state.bsr0 = 0x7F00;								\
   120 			else													\
   121 				state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00;		\
   122 			state.bsr0 |= (address >> 16);							\
   123 			state.bsr1 = address & 0xffff;							\
   124 			printf("ERR: BusError WR\n");							\
   125 			m68k_pulse_bus_error();									\
   126 			return;													\
   127 		}															\
   128 	} while (false)
   130 /**
   131  * @brief Check memory access permissions for a read operation.
   132  * @note	This used to be a single macro (merged with ACCESS_CHECK_WR), but
   133  * 			gcc throws warnings when you have a return-with-value in a void
   134  * 			function, even if the return-with-value is completely unreachable.
   135  * 			Similarly it doesn't like it if you have a return without a value
   136  * 			in a non-void function, even if it's impossible to ever reach the
   137  * 			return-with-no-value. UGH!
   138  */
   139 #define ACCESS_CHECK_RD(address, bits) do {							\
   140 		bool fault = false;											\
   141 		/* MEM_STATUS st; */										\
   142 		switch (checkMemoryAccess(address, false)) {				\
   143 			case MEM_ALLOWED:										\
   144 				/* Access allowed */								\
   145 				break;												\
   146 			case MEM_PAGEFAULT:										\
   147 				/* Page fault */									\
   148 				state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0);	\
   149 				fault = true;										\
   150 				break;												\
   151 			case MEM_UIE:											\
   152 				/* User access to memory above 4MB */				\
   153 				state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0);	\
   154 				fault = true;										\
   155 				break;												\
   156 			case MEM_KERNEL:										\
   157 			case MEM_PAGE_NO_WE:									\
   158 				/* kernel access or page not write enabled */		\
   159 				/* TODO: which regs need setting? */				\
   160 				fault = true;										\
   161 				break;												\
   162 		}															\
   163 																	\
   164 		if (fault) {												\
   165 			if (bits >= 16)											\
   166 				state.bsr0 = 0x7F00;								\
   167 			else													\
   168 				state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00;		\
   169 			state.bsr0 |= (address >> 16);							\
   170 			state.bsr1 = address & 0xffff;							\
   171 			printf("ERR: BusError RD\n");							\
   172 			m68k_pulse_bus_error();									\
   173 			return 0xFFFFFFFF;										\
   174 		}															\
   175 	} while (false)
   177 // Logging macros
   178 #define LOG_NOT_HANDLED_R(bits)																	\
   179 	do {																						\
   180 		if (!handled)																			\
   181 			printf("unhandled read%02d, addr=0x%08X\n", bits, address);							\
   182 	} while (0);
   184 #define LOG_NOT_HANDLED_W(bits)																	\
   185 	do {																						\
   186 		if (!handled)																			\
   187 			printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, value);	\
   188 	} while (0);
   190 /**
   191  * @brief Read M68K memory, 32-bit
   192  */
   193 uint32_t m68k_read_memory_32(uint32_t address)
   194 {
   195 	uint32_t data = 0xFFFFFFFF;
   196 	bool handled = false;
   198 	// If ROMLMAP is set, force system to access ROM
   199 	if (!state.romlmap)
   200 		address |= 0x800000;
   202 	// Check access permissions
   203 	ACCESS_CHECK_RD(address, 32);
   205 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   206 		// ROM access
   207 		data = RD32(state.rom, address, ROM_SIZE - 1);
   208 		handled = true;
   209 	} else if (address <= (state.ram_size - 1)) {
   210 		// RAM access
   211 		data = RD32(state.ram, mapAddr(address, false), state.ram_size - 1);
   212 		handled = true;
   213 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   214 		// I/O register space, zone A
   215 		switch (address & 0x0F0000) {
   216 			case 0x000000:				// Map RAM access
   217 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
   218 				data = RD32(state.map, address, 0x7FF);
   219 				handled = true;
   220 				break;
   221 			case 0x010000:				// General Status Register
   222 				data = ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
   223 				handled = true;
   224 				break;
   225 			case 0x020000:				// Video RAM
   226 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
   227 				data = RD32(state.vram, address, 0x7FFF);
   228 				handled = true;
   229 				break;
   230 			case 0x030000:				// Bus Status Register 0
   231 				data = ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
   232 				handled = true;
   233 				break;
   234 			case 0x040000:				// Bus Status Register 1
   235 				data = ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
   236 				handled = true;
   237 				break;
   238 			case 0x050000:				// Phone status
   239 				break;
   240 			case 0x060000:				// DMA Count
   241 				// TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
   242 				// Bit 14 is always unused, so leave it set
   243 				data = (state.dma_count & 0x3fff) | 0xC000;
   244 				handled = true;
   245 				break;
   246 			case 0x070000:				// Line Printer Status Register
   247 				data = 0x00120012;	// no parity error, no line printer error, no irqs from FDD or HDD
   248 				data |= (state.fdc_ctx.irql) ? 0x00080008 : 0;	// FIXME! HACKHACKHACK! shouldn't peek inside FDC structs like this
   249 				break;
   250 			case 0x080000:				// Real Time Clock
   251 				break;
   252 			case 0x090000:				// Phone registers
   253 				switch (address & 0x0FF000) {
   254 					case 0x090000:		// Handset relay
   255 					case 0x098000:
   256 						break;
   257 					case 0x091000:		// Line select 2
   258 					case 0x099000:
   259 						break;
   260 					case 0x092000:		// Hook relay 1
   261 					case 0x09A000:
   262 						break;
   263 					case 0x093000:		// Hook relay 2
   264 					case 0x09B000:
   265 						break;
   266 					case 0x094000:		// Line 1 hold
   267 					case 0x09C000:
   268 						break;
   269 					case 0x095000:		// Line 2 hold
   270 					case 0x09D000:
   271 						break;
   272 					case 0x096000:		// Line 1 A-lead
   273 					case 0x09E000:
   274 						break;
   275 					case 0x097000:		// Line 2 A-lead
   276 					case 0x09F000:
   277 						break;
   278 				}
   279 				break;
   280 			case 0x0A0000:				// Miscellaneous Control Register -- write only!
   281 				handled = true;
   282 				break;
   283 			case 0x0B0000:				// TM/DIALWR
   284 				break;
   285 			case 0x0C0000:				// Clear Status Register -- write only!
   286 				handled = true;
   287 				break;
   288 			case 0x0D0000:				// DMA Address Register
   289 				break;
   290 			case 0x0E0000:				// Disk Control Register
   291 				break;
   292 			case 0x0F0000:				// Line Printer Data Register
   293 				break;
   294 		}
   295 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   296 		// I/O register space, zone B
   297 		switch (address & 0xF00000) {
   298 			case 0xC00000:				// Expansion slots
   299 			case 0xD00000:
   300 				switch (address & 0xFC0000) {
   301 					case 0xC00000:		// Expansion slot 0
   302 					case 0xC40000:		// Expansion slot 1
   303 					case 0xC80000:		// Expansion slot 2
   304 					case 0xCC0000:		// Expansion slot 3
   305 					case 0xD00000:		// Expansion slot 4
   306 					case 0xD40000:		// Expansion slot 5
   307 					case 0xD80000:		// Expansion slot 6
   308 					case 0xDC0000:		// Expansion slot 7
   309 						fprintf(stderr, "NOTE: RD32 from expansion card space, addr=0x%08X\n", address);
   310 						break;
   311 				}
   312 				break;
   313 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   314 			case 0xF00000:
   315 				switch (address & 0x070000) {
   316 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   317 						break;
   318 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   319 						data = wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
   320 						printf("WD279X: rd32 %02X ==> %02X\n", (address >> 1) & 3, data);
   321 						handled = true;
   322 						break;
   323 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   324 						break;
   325 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   326 						break;
   327 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   328 						switch (address & 0x077000) {
   329 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   330 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   331 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   332 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   333 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   334 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   335 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   336 								// All write-only registers... TODO: bus error?
   337 								handled = true;
   338 								break;
   339 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
   340 								break;
   341 						}
   342 						break;
   343 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   344 						break;
   345 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   346 						switch (address & 0x07F000) {
   347 							default:
   348 								break;
   349 						}
   350 						break;
   351 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   352 						break;
   353 				}
   354 		}
   355 	}
   357 	LOG_NOT_HANDLED_R(32);
   358 	return data;
   359 }
   361 /**
   362  * @brief Read M68K memory, 16-bit
   363  */
   364 uint32_t m68k_read_memory_16(uint32_t address)
   365 {
   366 	uint16_t data = 0xFFFF;
   367 	bool handled = false;
   369 	// If ROMLMAP is set, force system to access ROM
   370 	if (!state.romlmap)
   371 		address |= 0x800000;
   373 	// Check access permissions
   374 	ACCESS_CHECK_RD(address, 16);
   376 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   377 		// ROM access
   378 		data = RD16(state.rom, address, ROM_SIZE - 1);
   379 		handled = true;
   380 	} else if (address <= (state.ram_size - 1)) {
   381 		// RAM access
   382 		data = RD16(state.ram, mapAddr(address, false), state.ram_size - 1);
   383 		handled = true;
   384 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   385 		// I/O register space, zone A
   386 		switch (address & 0x0F0000) {
   387 			case 0x000000:				// Map RAM access
   388 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
   389 				data = RD16(state.map, address, 0x7FF);
   390 				handled = true;
   391 				break;
   392 			case 0x010000:				// General Status Register
   393 				data = state.genstat;
   394 				handled = true;
   395 				break;
   396 			case 0x020000:				// Video RAM
   397 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
   398 				data = RD16(state.vram, address, 0x7FFF);
   399 				handled = true;
   400 				break;
   401 			case 0x030000:				// Bus Status Register 0
   402 				data = state.bsr0;
   403 				handled = true;
   404 				break;
   405 			case 0x040000:				// Bus Status Register 1
   406 				data = state.bsr1;
   407 				handled = true;
   408 				break;
   409 			case 0x050000:				// Phone status
   410 				break;
   411 			case 0x060000:				// DMA Count
   412 				// TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
   413 				// Bit 14 is always unused, so leave it set
   414 				data = (state.dma_count & 0x3fff) | 0xC000;
   415 				handled = true;
   416 				break;
   417 			case 0x070000:				// Line Printer Status Register
   418 				data = 0x0012;	// no parity error, no line printer error, no irqs from FDD or HDD
   419 				data |= (state.fdc_ctx.irql) ? 0x0008 : 0;	// FIXME! HACKHACKHACK! shouldn't peek inside FDC structs like this
   420 				break;
   421 			case 0x080000:				// Real Time Clock
   422 				break;
   423 			case 0x090000:				// Phone registers
   424 				switch (address & 0x0FF000) {
   425 					case 0x090000:		// Handset relay
   426 					case 0x098000:
   427 						break;
   428 					case 0x091000:		// Line select 2
   429 					case 0x099000:
   430 						break;
   431 					case 0x092000:		// Hook relay 1
   432 					case 0x09A000:
   433 						break;
   434 					case 0x093000:		// Hook relay 2
   435 					case 0x09B000:
   436 						break;
   437 					case 0x094000:		// Line 1 hold
   438 					case 0x09C000:
   439 						break;
   440 					case 0x095000:		// Line 2 hold
   441 					case 0x09D000:
   442 						break;
   443 					case 0x096000:		// Line 1 A-lead
   444 					case 0x09E000:
   445 						break;
   446 					case 0x097000:		// Line 2 A-lead
   447 					case 0x09F000:
   448 						break;
   449 				}
   450 				break;
   451 			case 0x0A0000:				// Miscellaneous Control Register -- write only!
   452 				handled = true;
   453 				break;
   454 			case 0x0B0000:				// TM/DIALWR
   455 				break;
   456 			case 0x0C0000:				// Clear Status Register -- write only!
   457 				handled = true;
   458 				break;
   459 			case 0x0D0000:				// DMA Address Register
   460 				break;
   461 			case 0x0E0000:				// Disk Control Register
   462 				break;
   463 			case 0x0F0000:				// Line Printer Data Register
   464 				break;
   465 		}
   466 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   467 		// I/O register space, zone B
   468 		switch (address & 0xF00000) {
   469 			case 0xC00000:				// Expansion slots
   470 			case 0xD00000:
   471 				switch (address & 0xFC0000) {
   472 					case 0xC00000:		// Expansion slot 0
   473 					case 0xC40000:		// Expansion slot 1
   474 					case 0xC80000:		// Expansion slot 2
   475 					case 0xCC0000:		// Expansion slot 3
   476 					case 0xD00000:		// Expansion slot 4
   477 					case 0xD40000:		// Expansion slot 5
   478 					case 0xD80000:		// Expansion slot 6
   479 					case 0xDC0000:		// Expansion slot 7
   480 						fprintf(stderr, "NOTE: RD16 from expansion card space, addr=0x%08X\n", address);
   481 						break;
   482 				}
   483 				break;
   484 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   485 			case 0xF00000:
   486 				switch (address & 0x070000) {
   487 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   488 						break;
   489 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   490 						data = wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
   491 						printf("WD279X: rd16 %02X ==> %02X\n", (address >> 1) & 3, data);
   492 						handled = true;
   493 						break;
   494 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   495 						break;
   496 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   497 						break;
   498 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   499 						switch (address & 0x077000) {
   500 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   501 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   502 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   503 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   504 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   505 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   506 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   507 								// All write-only registers... TODO: bus error?
   508 								handled = true;
   509 								break;
   510 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   511 								break;
   512 						}
   513 						break;
   514 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   515 						break;
   516 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   517 						switch (address & 0x07F000) {
   518 							default:
   519 								break;
   520 						}
   521 						break;
   522 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   523 						break;
   524 				}
   525 		}
   526 	}
   528 	LOG_NOT_HANDLED_R(16);
   529 	return data;
   530 }
   532 /**
   533  * @brief Read M68K memory, 8-bit
   534  */
   535 uint32_t m68k_read_memory_8(uint32_t address)
   536 {
   537 	uint8_t data = 0xFF;
   538 	bool handled = false;
   540 	// If ROMLMAP is set, force system to access ROM
   541 	if (!state.romlmap)
   542 		address |= 0x800000;
   544 	// Check access permissions
   545 	ACCESS_CHECK_RD(address, 8);
   547 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   548 		// ROM access
   549 		data = RD8(state.rom, address, ROM_SIZE - 1);
   550 		handled = true;
   551 	} else if (address <= (state.ram_size - 1)) {
   552 		// RAM access
   553 		data = RD8(state.ram, mapAddr(address, false), state.ram_size - 1);
   554 		handled = true;
   555 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   556 		// I/O register space, zone A
   557 		switch (address & 0x0F0000) {
   558 			case 0x000000:				// Map RAM access
   559 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
   560 				data = RD8(state.map, address, 0x7FF);
   561 				handled = true;
   562 				break;
   563 			case 0x010000:				// General Status Register
   564 				if ((address & 1) == 0)
   565 					data = (state.genstat >> 8) & 0xff;
   566 				else
   567 					data = (state.genstat)      & 0xff;
   568 				handled = true;
   569 				break;
   570 			case 0x020000:				// Video RAM
   571 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
   572 				data = RD8(state.vram, address, 0x7FFF);
   573 				handled = true;
   574 				break;
   575 			case 0x030000:				// Bus Status Register 0
   576 				if ((address & 1) == 0)
   577 					data = (state.bsr0 >> 8) & 0xff;
   578 				else
   579 					data = (state.bsr0)      & 0xff;
   580 				handled = true;
   581 				break;
   582 			case 0x040000:				// Bus Status Register 1
   583 				if ((address & 1) == 0)
   584 					data = (state.bsr1 >> 8) & 0xff;
   585 				else
   586 					data = (state.bsr1)      & 0xff;
   587 				handled = true;
   588 				break;
   589 			case 0x050000:				// Phone status
   590 				break;
   591 			case 0x060000:				// DMA Count
   592 				// TODO: how to handle this in 8bit mode?
   593 				break;
   594 			case 0x070000:				// Line Printer Status Register
   595 				printf("\tLPSR RD8 fdc irql=%d, irqe=%d\n", state.fdc_ctx.irql, state.fdc_ctx.irqe);
   596 				if (address & 1) {
   597 					data = 0x12;	// no parity error, no line printer error, no irqs from FDD or HDD
   598 					data |= (state.fdc_ctx.irql) ? 0x08 : 0;	// FIXME! HACKHACKHACK! shouldn't peek inside FDC structs like this
   599 				} else {
   600 					data = 0;
   601 				}
   602 				break;
   603 			case 0x080000:				// Real Time Clock
   604 				break;
   605 			case 0x090000:				// Phone registers
   606 				switch (address & 0x0FF000) {
   607 					case 0x090000:		// Handset relay
   608 					case 0x098000:
   609 						break;
   610 					case 0x091000:		// Line select 2
   611 					case 0x099000:
   612 						break;
   613 					case 0x092000:		// Hook relay 1
   614 					case 0x09A000:
   615 						break;
   616 					case 0x093000:		// Hook relay 2
   617 					case 0x09B000:
   618 						break;
   619 					case 0x094000:		// Line 1 hold
   620 					case 0x09C000:
   621 						break;
   622 					case 0x095000:		// Line 2 hold
   623 					case 0x09D000:
   624 						break;
   625 					case 0x096000:		// Line 1 A-lead
   626 					case 0x09E000:
   627 						break;
   628 					case 0x097000:		// Line 2 A-lead
   629 					case 0x09F000:
   630 						break;
   631 				}
   632 				break;
   633 			case 0x0A0000:				// Miscellaneous Control Register -- write only!
   634 				handled = true;
   635 				break;
   636 			case 0x0B0000:				// TM/DIALWR
   637 				break;
   638 			case 0x0C0000:				// Clear Status Register -- write only!
   639 				handled = true;
   640 				break;
   641 			case 0x0D0000:				// DMA Address Register
   642 				break;
   643 			case 0x0E0000:				// Disk Control Register
   644 				break;
   645 			case 0x0F0000:				// Line Printer Data Register
   646 				break;
   647 		}
   648 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   649 		// I/O register space, zone B
   650 		switch (address & 0xF00000) {
   651 			case 0xC00000:				// Expansion slots
   652 			case 0xD00000:
   653 				switch (address & 0xFC0000) {
   654 					case 0xC00000:		// Expansion slot 0
   655 					case 0xC40000:		// Expansion slot 1
   656 					case 0xC80000:		// Expansion slot 2
   657 					case 0xCC0000:		// Expansion slot 3
   658 					case 0xD00000:		// Expansion slot 4
   659 					case 0xD40000:		// Expansion slot 5
   660 					case 0xD80000:		// Expansion slot 6
   661 					case 0xDC0000:		// Expansion slot 7
   662 						fprintf(stderr, "NOTE: RD8 from expansion card space, addr=0x%08X\n", address);
   663 						break;
   664 				}
   665 				break;
   666 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   667 			case 0xF00000:
   668 				switch (address & 0x070000) {
   669 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   670 						break;
   671 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   672 						data = wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
   673 						printf("WD279X: rd8 %02X ==> %02X\n", (address >> 1) & 3, data);
   674 						handled = true;
   675 						break;
   676 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   677 						break;
   678 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   679 						break;
   680 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   681 						switch (address & 0x077000) {
   682 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   683 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   684 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   685 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   686 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   687 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   688 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   689 								// All write-only registers... TODO: bus error?
   690 								handled = true;
   691 								break;
   692 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   693 								break;
   694 						}
   695 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   696 						break;
   697 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   698 						switch (address & 0x07F000) {
   699 							default:
   700 								break;
   701 						}
   702 						break;
   703 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   704 						break;
   705 				}
   706 		}
   707 	}
   709 	LOG_NOT_HANDLED_R(8);
   711 	return data;
   712 }
   714 /**
   715  * @brief Write M68K memory, 32-bit
   716  */
   717 void m68k_write_memory_32(uint32_t address, uint32_t value)
   718 {
   719 	bool handled = false;
   721 	// If ROMLMAP is set, force system to access ROM
   722 	if (!state.romlmap)
   723 		address |= 0x800000;
   725 	// Check access permissions
   726 	ACCESS_CHECK_WR(address, 32);
   728 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   729 		// ROM access
   730 		handled = true;
   731 	} else if (address <= (state.ram_size - 1)) {
   732 		// RAM access
   733 		WR32(state.ram, mapAddr(address, false), state.ram_size - 1, value);
   734 		handled = true;
   735 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   736 		// I/O register space, zone A
   737 		switch (address & 0x0F0000) {
   738 			case 0x000000:				// Map RAM access
   739 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
   740 				WR32(state.map, address, 0x7FF, value);
   741 				handled = true;
   742 				break;
   743 			case 0x010000:				// General Status Register
   744 				state.genstat = (value & 0xffff);
   745 				handled = true;
   746 				break;
   747 			case 0x020000:				// Video RAM
   748 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
   749 				WR32(state.vram, address, 0x7FFF, value);
   750 				handled = true;
   751 				break;
   752 			case 0x030000:				// Bus Status Register 0
   753 				break;
   754 			case 0x040000:				// Bus Status Register 1
   755 				break;
   756 			case 0x050000:				// Phone status
   757 				break;
   758 			case 0x060000:				// DMA Count
   759 				printf("WR32 dmacount %08X\n", value);
   760 				state.dma_count = (value & 0x3FFF);
   761 				state.idmarw = ((value & 0x4000) == 0x4000);
   762 				state.dmaen = ((value & 0x8000) == 0x8000);
   763 				printf("\tcount %04X, idmarw %d, dmaen %d\n", state.dma_count, state.idmarw, state.dmaen);
   764 				// This handles the "dummy DMA transfer" mentioned in the docs
   765 				// TODO: access check, peripheral access
   766 				if (!state.idmarw)
   767 					WR32(state.ram, mapAddr(address, false), state.ram_size - 1, 0xDEAD);
   768 				state.dma_count++;
   769 				handled = true;
   770 				break;
   771 			case 0x070000:				// Line Printer Status Register
   772 				break;
   773 			case 0x080000:				// Real Time Clock
   774 				break;
   775 			case 0x090000:				// Phone registers
   776 				switch (address & 0x0FF000) {
   777 					case 0x090000:		// Handset relay
   778 					case 0x098000:
   779 						break;
   780 					case 0x091000:		// Line select 2
   781 					case 0x099000:
   782 						break;
   783 					case 0x092000:		// Hook relay 1
   784 					case 0x09A000:
   785 						break;
   786 					case 0x093000:		// Hook relay 2
   787 					case 0x09B000:
   788 						break;
   789 					case 0x094000:		// Line 1 hold
   790 					case 0x09C000:
   791 						break;
   792 					case 0x095000:		// Line 2 hold
   793 					case 0x09D000:
   794 						break;
   795 					case 0x096000:		// Line 1 A-lead
   796 					case 0x09E000:
   797 						break;
   798 					case 0x097000:		// Line 2 A-lead
   799 					case 0x09F000:
   800 						break;
   801 				}
   802 				break;
   803 			case 0x0A0000:				// Miscellaneous Control Register
   804 				// TODO: handle the ctrl bits properly
   805 				// TODO: &0x8000 --> dismiss 60hz intr
   806 				state.dma_reading = (value & 0x4000);
   807 				state.leds = (~value & 0xF00) >> 8;
   808 				printf("LEDs: %s %s %s %s\n",
   809 						(state.leds & 8) ? "R" : "-",
   810 						(state.leds & 4) ? "G" : "-",
   811 						(state.leds & 2) ? "Y" : "-",
   812 						(state.leds & 1) ? "R" : "-");
   813 				handled = true;
   814 				break;
   815 			case 0x0B0000:				// TM/DIALWR
   816 				break;
   817 			case 0x0C0000:				// Clear Status Register
   818 				state.genstat = 0xFFFF;
   819 				state.bsr0 = 0xFFFF;
   820 				state.bsr1 = 0xFFFF;
   821 				handled = true;
   822 				break;
   823 			case 0x0D0000:				// DMA Address Register
   824 				if (address & 0x004000) {
   825 					// A14 high -- set most significant bits
   826 					state.dma_address = (state.dma_address & 0xff) | ((address & 0x3fff) << 7);
   827 				} else {
   828 					// A14 low -- set least significant bits
   829 					state.dma_address = (state.dma_address & 0x3fff00) | (address & 0xff);
   830 				}
   831 				printf("WR DMA_ADDR, now %08X\n", state.dma_address);
   832 				handled = true;
   833 				break;
   834 			case 0x0E0000:				// Disk Control Register
   835 				// B7 = FDD controller reset
   836 				if ((value & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
   837 				// B6 = drive 0 select -- TODO
   838 				// B5 = motor enable -- TODO
   839 				// B4 = HDD controller reset -- TODO
   840 				// B3 = HDD0 select -- TODO
   841 				// B2,1,0 = HDD0 head select
   842 				handled = true;
   843 				break;
   844 			case 0x0F0000:				// Line Printer Data Register
   845 				break;
   846 		}
   847 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   848 		// I/O register space, zone B
   849 		switch (address & 0xF00000) {
   850 			case 0xC00000:				// Expansion slots
   851 			case 0xD00000:
   852 				switch (address & 0xFC0000) {
   853 					case 0xC00000:		// Expansion slot 0
   854 					case 0xC40000:		// Expansion slot 1
   855 					case 0xC80000:		// Expansion slot 2
   856 					case 0xCC0000:		// Expansion slot 3
   857 					case 0xD00000:		// Expansion slot 4
   858 					case 0xD40000:		// Expansion slot 5
   859 					case 0xD80000:		// Expansion slot 6
   860 					case 0xDC0000:		// Expansion slot 7
   861 						fprintf(stderr, "NOTE: WR32 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
   862 						handled = true;
   863 						break;
   864 				}
   865 				break;
   866 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   867 			case 0xF00000:
   868 				switch (address & 0x070000) {
   869 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   870 						break;
   871 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   872 						printf("WD279X: wr32 %02X ==> %02X\n", (address >> 1) & 3, value);
   873 						wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, value);
   874 						handled = true;
   875 						break;
   876 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   877 						break;
   878 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   879 						break;
   880 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   881 						switch (address & 0x077000) {
   882 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   883 								break;
   884 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   885 								state.pie = ((value & 0x8000) == 0x8000);
   886 								handled = true;
   887 								break;
   888 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   889 								break;
   890 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   891 								state.romlmap = ((value & 0x8000) == 0x8000);
   892 								handled = true;
   893 								break;
   894 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   895 								break;
   896 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   897 								break;
   898 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   899 								break;
   900 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   901 								break;
   902 						}
   903 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   904 						break;
   905 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   906 						switch (address & 0x07F000) {
   907 							default:
   908 								break;
   909 						}
   910 						break;
   911 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   912 						break;
   913 				}
   914 		}
   915 	}
   917 	LOG_NOT_HANDLED_W(32);
   918 }
   920 /**
   921  * @brief Write M68K memory, 16-bit
   922  */
   923 void m68k_write_memory_16(uint32_t address, uint32_t value)
   924 {
   925 	bool handled = false;
   927 	// If ROMLMAP is set, force system to access ROM
   928 	if (!state.romlmap)
   929 		address |= 0x800000;
   931 	// Check access permissions
   932 	ACCESS_CHECK_WR(address, 16);
   934 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   935 		// ROM access
   936 		handled = true;
   937 	} else if (address <= (state.ram_size - 1)) {
   938 		// RAM access
   939 		WR16(state.ram, mapAddr(address, false), state.ram_size - 1, value);
   940 		handled = true;
   941 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   942 		// I/O register space, zone A
   943 		switch (address & 0x0F0000) {
   944 			case 0x000000:				// Map RAM access
   945 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   946 				WR16(state.map, address, 0x7FF, value);
   947 				handled = true;
   948 				break;
   949 			case 0x010000:				// General Status Register (read only)
   950 				handled = true;
   951 				break;
   952 			case 0x020000:				// Video RAM
   953 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   954 				WR16(state.vram, address, 0x7FFF, value);
   955 				handled = true;
   956 				break;
   957 			case 0x030000:				// Bus Status Register 0 (read only)
   958 				handled = true;
   959 				break;
   960 			case 0x040000:				// Bus Status Register 1 (read only)
   961 				handled = true;
   962 				break;
   963 			case 0x050000:				// Phone status
   964 				break;
   965 			case 0x060000:				// DMA Count
   966 				printf("WR16 dmacount %08X\n", value);
   967 				state.dma_count = (value & 0x3FFF);
   968 				state.idmarw = ((value & 0x4000) == 0x4000);
   969 				state.dmaen = ((value & 0x8000) == 0x8000);
   970 				printf("\tcount %04X, idmarw %d, dmaen %d\n", state.dma_count, state.idmarw, state.dmaen);
   971 				// This handles the "dummy DMA transfer" mentioned in the docs
   972 				// TODO: access check, peripheral access
   973 				if (!state.idmarw)
   974 					WR32(state.ram, mapAddr(address, false), state.ram_size - 1, 0xDEAD);
   975 				state.dma_count++;
   976 				handled = true;
   977 				break;
   978 			case 0x070000:				// Line Printer Status Register
   979 				break;
   980 			case 0x080000:				// Real Time Clock
   981 				break;
   982 			case 0x090000:				// Phone registers
   983 				switch (address & 0x0FF000) {
   984 					case 0x090000:		// Handset relay
   985 					case 0x098000:
   986 						break;
   987 					case 0x091000:		// Line select 2
   988 					case 0x099000:
   989 						break;
   990 					case 0x092000:		// Hook relay 1
   991 					case 0x09A000:
   992 						break;
   993 					case 0x093000:		// Hook relay 2
   994 					case 0x09B000:
   995 						break;
   996 					case 0x094000:		// Line 1 hold
   997 					case 0x09C000:
   998 						break;
   999 					case 0x095000:		// Line 2 hold
  1000 					case 0x09D000:
  1001 						break;
  1002 					case 0x096000:		// Line 1 A-lead
  1003 					case 0x09E000:
  1004 						break;
  1005 					case 0x097000:		// Line 2 A-lead
  1006 					case 0x09F000:
  1007 						break;
  1009 				break;
  1010 			case 0x0A0000:				// Miscellaneous Control Register
  1011 				// TODO: handle the ctrl bits properly
  1012 				// TODO: &0x8000 --> dismiss 60hz intr
  1013 				state.dma_reading = (value & 0x4000);
  1014 				state.leds = (~value & 0xF00) >> 8;
  1015 				printf("LEDs: %s %s %s %s\n",
  1016 						(state.leds & 8) ? "R" : "-",
  1017 						(state.leds & 4) ? "G" : "-",
  1018 						(state.leds & 2) ? "Y" : "-",
  1019 						(state.leds & 1) ? "R" : "-");
  1020 				handled = true;
  1021 				break;
  1022 			case 0x0B0000:				// TM/DIALWR
  1023 				break;
  1024 			case 0x0C0000:				// Clear Status Register
  1025 				state.genstat = 0xFFFF;
  1026 				state.bsr0 = 0xFFFF;
  1027 				state.bsr1 = 0xFFFF;
  1028 				handled = true;
  1029 				break;
  1030 			case 0x0D0000:				// DMA Address Register
  1031 				if (address & 0x004000) {
  1032 					// A14 high -- set most significant bits
  1033 					state.dma_address = (state.dma_address & 0xff) | ((address & 0x3fff) << 7);
  1034 				} else {
  1035 					// A14 low -- set least significant bits
  1036 					state.dma_address = (state.dma_address & 0x3fff00) | (address & 0xff);
  1038 				printf("WR DMA_ADDR, now %08X\n", state.dma_address);
  1039 				handled = true;
  1040 				break;
  1041 			case 0x0E0000:				// Disk Control Register
  1042 				// B7 = FDD controller reset
  1043 				if ((value & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
  1044 				// B6 = drive 0 select -- TODO
  1045 				// B5 = motor enable -- TODO
  1046 				// B4 = HDD controller reset -- TODO
  1047 				// B3 = HDD0 select -- TODO
  1048 				// B2,1,0 = HDD0 head select
  1049 				handled = true;
  1050 				break;
  1051 			case 0x0F0000:				// Line Printer Data Register
  1052 				break;
  1054 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
  1055 		// I/O register space, zone B
  1056 		switch (address & 0xF00000) {
  1057 			case 0xC00000:				// Expansion slots
  1058 			case 0xD00000:
  1059 				switch (address & 0xFC0000) {
  1060 					case 0xC00000:		// Expansion slot 0
  1061 					case 0xC40000:		// Expansion slot 1
  1062 					case 0xC80000:		// Expansion slot 2
  1063 					case 0xCC0000:		// Expansion slot 3
  1064 					case 0xD00000:		// Expansion slot 4
  1065 					case 0xD40000:		// Expansion slot 5
  1066 					case 0xD80000:		// Expansion slot 6
  1067 					case 0xDC0000:		// Expansion slot 7
  1068 						fprintf(stderr, "NOTE: WR16 to expansion card space, addr=0x%08X, data=0x%04X\n", address, value);
  1069 						break;
  1071 				break;
  1072 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
  1073 			case 0xF00000:
  1074 				switch (address & 0x070000) {
  1075 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
  1076 						break;
  1077 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
  1078 						printf("WD279X: wr16 %02X ==> %02X\n", (address >> 1) & 3, value);
  1079 						wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, value);
  1080 						handled = true;
  1081 						break;
  1082 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
  1083 						break;
  1084 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
  1085 						break;
  1086 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
  1087 						switch (address & 0x077000) {
  1088 							case 0x040000:		// [ef][4c][08]xxx ==> EE
  1089 								break;
  1090 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
  1091 								state.pie = ((value & 0x8000) == 0x8000);
  1092 								handled = true;
  1093 								break;
  1094 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
  1095 								break;
  1096 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
  1097 								state.romlmap = ((value & 0x8000) == 0x8000);
  1098 								handled = true;
  1099 								break;
  1100 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
  1101 								break;
  1102 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
  1103 								break;
  1104 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
  1105 								break;
  1106 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
  1107 								break;
  1109 					case 0x050000:		// [ef][5d]xxxx ==> 8274
  1110 						break;
  1111 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
  1112 						switch (address & 0x07F000) {
  1113 							default:
  1114 								break;
  1116 						break;
  1117 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
  1118 						break;
  1123 	LOG_NOT_HANDLED_W(16);
  1126 /**
  1127  * @brief Write M68K memory, 8-bit
  1128  */
  1129 void m68k_write_memory_8(uint32_t address, uint32_t value)
  1131 	bool handled = false;
  1133 	// If ROMLMAP is set, force system to access ROM
  1134 	if (!state.romlmap)
  1135 		address |= 0x800000;
  1137 	// Check access permissions
  1138 	ACCESS_CHECK_WR(address, 8);
  1140 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
  1141 		// ROM access (read only!)
  1142 		handled = true;
  1143 	} else if (address <= (state.ram_size - 1)) {
  1144 		// RAM access
  1145 		WR8(state.ram, mapAddr(address, false), state.ram_size - 1, value);
  1146 		handled = true;
  1147 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
  1148 		// I/O register space, zone A
  1149 		switch (address & 0x0F0000) {
  1150 			case 0x000000:				// Map RAM access
  1151 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=%08X, data=%02X\n", address, value);
  1152 				WR8(state.map, address, 0x7FF, value);
  1153 				handled = true;
  1154 				break;
  1155 			case 0x010000:				// General Status Register
  1156 				handled = true;
  1157 				break;
  1158 			case 0x020000:				// Video RAM
  1159 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=%08X, data=0x%02X\n", address, value);
  1160 				WR8(state.vram, address, 0x7FFF, value);
  1161 				handled = true;
  1162 				break;
  1163 			case 0x030000:				// Bus Status Register 0
  1164 				handled = true;
  1165 				break;
  1166 			case 0x040000:				// Bus Status Register 1
  1167 				handled = true;
  1168 				break;
  1169 			case 0x050000:				// Phone status
  1170 				break;
  1171 			case 0x060000:				// DMA Count
  1172 				// TODO: how to handle this in 8bit mode?
  1173 				break;
  1174 			case 0x070000:				// Line Printer Status Register
  1175 				break;
  1176 			case 0x080000:				// Real Time Clock
  1177 				break;
  1178 			case 0x090000:				// Phone registers
  1179 				switch (address & 0x0FF000) {
  1180 					case 0x090000:		// Handset relay
  1181 					case 0x098000:
  1182 						break;
  1183 					case 0x091000:		// Line select 2
  1184 					case 0x099000:
  1185 						break;
  1186 					case 0x092000:		// Hook relay 1
  1187 					case 0x09A000:
  1188 						break;
  1189 					case 0x093000:		// Hook relay 2
  1190 					case 0x09B000:
  1191 						break;
  1192 					case 0x094000:		// Line 1 hold
  1193 					case 0x09C000:
  1194 						break;
  1195 					case 0x095000:		// Line 2 hold
  1196 					case 0x09D000:
  1197 						break;
  1198 					case 0x096000:		// Line 1 A-lead
  1199 					case 0x09E000:
  1200 						break;
  1201 					case 0x097000:		// Line 2 A-lead
  1202 					case 0x09F000:
  1203 						break;
  1205 				break;
  1206 			case 0x0A0000:				// Miscellaneous Control Register
  1207 				// TODO: how to handle this in 8bit mode?
  1208 /*
  1209 				// TODO: handle the ctrl bits properly
  1210 				if ((address & 1) == 0) {
  1211 					// low byte
  1212 				} else {
  1213 					// hight byte
  1214 					// TODO: &0x8000 --> dismiss 60hz intr
  1215 					state.dma_reading = (value & 0x40);
  1216 					state.leds = (~value & 0xF);
  1218 				printf("LEDs: %s %s %s %s\n",
  1219 						(state.leds & 8) ? "R" : "-",
  1220 						(state.leds & 4) ? "G" : "-",
  1221 						(state.leds & 2) ? "Y" : "-",
  1222 						(state.leds & 1) ? "R" : "-");
  1223 				handled = true;
  1224 */
  1225 				break;
  1226 			case 0x0B0000:				// TM/DIALWR
  1227 				break;
  1228 			case 0x0C0000:				// Clear Status Register
  1229 				state.genstat = 0xFFFF;
  1230 				state.bsr0 = 0xFFFF;
  1231 				state.bsr1 = 0xFFFF;
  1232 				handled = true;
  1233 				break;
  1234 			case 0x0D0000:				// DMA Address Register
  1235 				if (address & 0x004000) {
  1236 					// A14 high -- set most significant bits
  1237 					state.dma_address = (state.dma_address & 0xff) | ((address & 0x3fff) << 7);
  1238 				} else {
  1239 					// A14 low -- set least significant bits
  1240 					state.dma_address = (state.dma_address & 0x3fff00) | (address & 0xff);
  1242 				printf("WR DMA_ADDR, now %08X\n", state.dma_address);
  1243 				handled = true;
  1244 				break;
  1245 			case 0x0E0000:				// Disk Control Register
  1246 				// B7 = FDD controller reset
  1247 				if ((value & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
  1248 				// B6 = drive 0 select -- TODO
  1249 				// B5 = motor enable -- TODO
  1250 				// B4 = HDD controller reset -- TODO
  1251 				// B3 = HDD0 select -- TODO
  1252 				// B2,1,0 = HDD0 head select
  1253 				handled = true;
  1254 				break;
  1255 			case 0x0F0000:				// Line Printer Data Register
  1256 				break;
  1258 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
  1259 		// I/O register space, zone B
  1260 		switch (address & 0xF00000) {
  1261 			case 0xC00000:				// Expansion slots
  1262 			case 0xD00000:
  1263 				switch (address & 0xFC0000) {
  1264 					case 0xC00000:		// Expansion slot 0
  1265 					case 0xC40000:		// Expansion slot 1
  1266 					case 0xC80000:		// Expansion slot 2
  1267 					case 0xCC0000:		// Expansion slot 3
  1268 					case 0xD00000:		// Expansion slot 4
  1269 					case 0xD40000:		// Expansion slot 5
  1270 					case 0xD80000:		// Expansion slot 6
  1271 					case 0xDC0000:		// Expansion slot 7
  1272 						fprintf(stderr, "NOTE: WR8 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
  1273 						break;
  1275 				break;
  1276 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
  1277 			case 0xF00000:
  1278 				switch (address & 0x070000) {
  1279 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
  1280 						break;
  1281 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
  1282 						printf("WD279X: wr8 %02X ==> %02X\n", (address >> 1) & 3, value);
  1283 						wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, value);
  1284 						handled = true;
  1285 						break;
  1286 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
  1287 						break;
  1288 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
  1289 						break;
  1290 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
  1291 						switch (address & 0x077000) {
  1292 							case 0x040000:		// [ef][4c][08]xxx ==> EE
  1293 								break;
  1294 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
  1295 								if ((address & 1) == 0)
  1296 									state.pie = ((value & 0x80) == 0x80);
  1297 								handled = true;
  1298 								break;
  1299 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
  1300 								break;
  1301 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
  1302 								if ((address & 1) == 0)
  1303 									state.romlmap = ((value & 0x80) == 0x80);
  1304 								handled = true;
  1305 								break;
  1306 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
  1307 								break;
  1308 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
  1309 								break;
  1310 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
  1311 								break;
  1312 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
  1313 								break;
  1315 					case 0x050000:		// [ef][5d]xxxx ==> 8274
  1316 						break;
  1317 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
  1318 						switch (address & 0x07F000) {
  1319 							default:
  1320 								break;
  1322 						break;
  1323 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
  1324 						break;
  1325 					default:
  1326 						fprintf(stderr, "NOTE: WR8 to undefined E/F-block space, addr=0x%08X, data=0x%08X\n", address, value);
  1327 						break;
  1332 	LOG_NOT_HANDLED_W(8);
  1336 // for the disassembler
  1337 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
  1338 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
  1339 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }