Fri, 18 Apr 2014 01:26:01 -0600
treat all DMA reads/writes as kernel mode (previously it would depend on whether the processor happens to be in user mode or kernel mode when the DMA completes, which is totally incorrect); handle 32-bit accesses that straddle page boundaries properly (all 32-bit accesses are now split into two 16-bit accesses); allow reads to the entire zero page, rather than just address 0
1 #include <stdio.h>
2 #include <stdlib.h>
3 #include <stdint.h>
4 #include <stdbool.h>
5 #include <assert.h>
6 #include "musashi/m68k.h"
7 #include "state.h"
8 #include "utils.h"
9 #include "memory.h"
11 // The value which will be returned if the CPU attempts to read from empty memory
12 // TODO (FIXME?) - need to figure out if R/W ops wrap around. This seems to appease the UNIX kernel and P4TEST.
13 #define EMPTY 0xFFFFFFFFUL
14 //#define EMPTY 0x55555555UL
15 //#define EMPTY 0x00000000UL
17 /******************
18 * Memory mapping
19 ******************/
21 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
23 static uint32_t map_address_debug(uint32_t addr)
24 {
25 uint16_t page = (addr >> 12) & 0x3FF;
27 // Look it up in the map RAM and get the physical page address
28 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
29 return (new_page_addr << 12) + (addr & 0xFFF);
30 }
32 uint32_t mapAddr(uint32_t addr, bool writing)/*{{{*/
33 {
34 if (addr < 0x400000) {
35 // RAM access. Check against the Map RAM
36 // Start by getting the original page address
37 uint16_t page = (addr >> 12) & 0x3FF;
39 // Look it up in the map RAM and get the physical page address
40 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
42 // Update the Page Status bits
43 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
44 // Pagebits --
45 // 0 = not present
46 // 1 = present but not accessed
47 // 2 = present, accessed (read from)
48 // 3 = present, dirty (written to)
49 switch (pagebits) {
50 case 0:
51 // Page not present
52 // This should cause a page fault
53 LOGS("Whoa! Pagebit update, when the page is not present!");
54 break;
56 case 1:
57 // Page present -- first access
58 state.map[page*2] &= 0x9F; // turn off "present" bit (but not write enable!)
59 if (writing)
60 state.map[page*2] |= 0x60; // Page written to (dirty)
61 else
62 state.map[page*2] |= 0x40; // Page accessed but not written
63 break;
65 case 2:
66 case 3:
67 // Page present, 2nd or later access
68 if (writing)
69 state.map[page*2] |= 0x60; // Page written to (dirty)
70 break;
71 }
73 // Return the address with the new physical page spliced in
74 return (new_page_addr << 12) + (addr & 0xFFF);
75 } else {
76 // I/O, VRAM or MapRAM space; no mapping is performed or required
77 // TODO: assert here?
78 return addr;
79 }
80 }/*}}}*/
82 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing, bool dma)/*{{{*/
83 {
84 // Get the page bits for this page.
85 uint16_t page = (addr >> 12) & 0x3FF;
86 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
88 // Check page is present (but only for RAM zone)
89 if ((addr < 0x400000) && ((pagebits & 0x03) == 0)) {
90 LOG("Page not mapped in: addr %08X, page %04X, mapbits %04X", addr, page, MAPRAM(page));
91 return MEM_PAGEFAULT;
92 }
94 // Are we in Supervisor mode?
95 if (dma || (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000))
96 // Yes. We can do anything we like.
97 return MEM_ALLOWED;
99 // If we're here, then we must be in User mode.
100 // Check that the user didn't access memory outside of the RAM area
101 if (addr >= 0x400000) {
102 LOGS("User accessed privileged memory");
103 return MEM_UIE;
104 }
106 // User attempt to access the kernel
107 // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
108 if (((addr >> 19) & 0x0F) == 0 && !(!writing && addr <= 0x1000)) {
109 LOGS("Attempt by user code to access kernel space");
110 return MEM_KERNEL;
111 }
113 // Check page is write enabled
114 if (writing && ((pagebits & 0x04) == 0)) {
115 LOG("Page not write enabled: inaddr %08X, page %04X, mapram %04X [%02X %02X], pagebits %d",
116 addr, page, MAPRAM(page), state.map[page*2], state.map[(page*2)+1], pagebits);
117 return MEM_PAGE_NO_WE;
118 }
119 // Page access allowed.
120 return MEM_ALLOWED;
121 }/*}}}*/
123 #define _ACCESS_CHECK_WR_BYTE(address) \
124 do { \
125 switch (st = checkMemoryAccess(address, true, false)) { \
126 case MEM_ALLOWED: \
127 /* Access allowed */ \
128 break; \
129 case MEM_PAGEFAULT: \
130 /* Page fault */ \
131 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0); \
132 fault = true; \
133 break; \
134 case MEM_UIE: \
135 /* User access to memory above 4MB */ \
136 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0); \
137 fault = true; \
138 break; \
139 case MEM_KERNEL: \
140 case MEM_PAGE_NO_WE: \
141 /* kernel access or page not write enabled */ \
142 /* XXX: is this the correct value? */ \
143 state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0); \
144 fault = true; \
145 break; \
146 } \
147 }while (0)
151 /********************************************************
152 * m68k memory read/write support functions for Musashi
153 ********************************************************/
155 /**
156 * @brief Check memory access permissions for a write operation.
157 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
158 * gcc throws warnings when you have a return-with-value in a void
159 * function, even if the return-with-value is completely unreachable.
160 * Similarly it doesn't like it if you have a return without a value
161 * in a non-void function, even if it's impossible to ever reach the
162 * return-with-no-value. UGH!
163 */
164 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
165 #define ACCESS_CHECK_WR(address, bits) \
166 do { \
167 bool fault = false; \
168 MEM_STATUS st; \
169 _ACCESS_CHECK_WR_BYTE(address); \
170 if (!fault && bits == 32 \
171 && ((address + 3) & ~0xfff) != ((address & ~0xfff))){ \
172 _ACCESS_CHECK_WR_BYTE(address + 3); \
173 } \
174 if (fault) { \
175 if (bits >= 16) \
176 state.bsr0 = 0x7C00; \
177 else \
178 state.bsr0 = (address & 1) ? 0x7E00 : 0x7D00; \
179 state.bsr0 |= (address >> 16); \
180 state.bsr1 = address & 0xffff; \
181 LOG("Bus Error while writing, addr %08X, statcode %d", address, st); \
182 if (state.ee) m68k_pulse_bus_error(); \
183 return; \
184 } \
185 } while (0)
186 /*}}}*/
188 #define _ACCESS_CHECK_RD_BYTE(address) \
189 do { \
190 switch (st = checkMemoryAccess(address, false, false)) { \
191 case MEM_ALLOWED: \
192 /* Access allowed */ \
193 break; \
194 case MEM_PAGEFAULT: \
195 /* Page fault */ \
196 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0); \
197 fault = true; \
198 break; \
199 case MEM_UIE: \
200 /* User access to memory above 4MB */ \
201 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0); \
202 fault = true; \
203 break; \
204 case MEM_KERNEL: \
205 case MEM_PAGE_NO_WE: \
206 /* kernel access or page not write enabled */ \
207 /* XXX: is this the correct value? */ \
208 state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0); \
209 fault = true; \
210 break; \
211 } \
212 } while (0)
214 /**
215 * @brief Check memory access permissions for a read operation.
216 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
217 * gcc throws warnings when you have a return-with-value in a void
218 * function, even if the return-with-value is completely unreachable.
219 * Similarly it doesn't like it if you have a return without a value
220 * in a non-void function, even if it's impossible to ever reach the
221 * return-with-no-value. UGH!
222 */
223 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
224 #define ACCESS_CHECK_RD(address, bits) \
225 do { \
226 bool fault = false; \
227 uint32_t faultAddr = address; \
228 MEM_STATUS st; \
229 _ACCESS_CHECK_RD_BYTE(address); \
230 if (!fault && bits == 32 \
231 && ((address + 2) & ~0xfff) != (address & ~0xfff)){ \
232 _ACCESS_CHECK_RD_BYTE(address + 2); \
233 if (fault) faultAddr = address + 2; \
234 } \
235 \
236 if (fault) { \
237 if (bits >= 16) \
238 state.bsr0 = 0x7C00; \
239 else \
240 state.bsr0 = (faultAddr & 1) ? 0x7E00 : 0x7D00; \
241 state.bsr0 |= (faultAddr >> 16); \
242 state.bsr1 = faultAddr & 0xffff; \
243 LOG("Bus Error while reading, addr %08X, statcode %d", faultAddr, st); \
244 if (state.ee) m68k_pulse_bus_error(); \
245 if (bits >= 32) \
246 return EMPTY & 0xFFFFFFFF; \
247 else \
248 return EMPTY & ((1ULL << bits)-1); \
249 } \
250 } while (0)
251 /*}}}*/
253 bool access_check_dma(int reading)
254 {
255 // Check memory access permissions
256 bool access_ok = false;
257 switch (checkMemoryAccess(state.dma_address, !reading, true)) {
258 case MEM_PAGEFAULT:
259 // Page fault
260 state.genstat = 0xABFF
261 | (reading ? 0x4000 : 0)
262 | (state.pie ? 0x0400 : 0);
263 access_ok = false;
264 break;
266 case MEM_UIE:
267 // User access to memory above 4MB
268 // FIXME? Shouldn't be possible with DMA... assert this?
269 state.genstat = 0xBAFF
270 | (reading ? 0x4000 : 0)
271 | (state.pie ? 0x0400 : 0);
272 access_ok = false;
273 break;
275 case MEM_KERNEL:
276 case MEM_PAGE_NO_WE:
277 // Kernel access or page not write enabled
278 /* XXX: is this correct? */
279 state.genstat = 0xBBFF
280 | (reading ? 0x4000 : 0)
281 | (state.pie ? 0x0400 : 0);
282 access_ok = false;
283 break;
285 case MEM_ALLOWED:
286 access_ok = true;
287 break;
288 }
289 if (!access_ok) {
290 state.bsr0 = 0x3C00;
291 state.bsr0 |= (state.dma_address >> 16);
292 state.bsr1 = state.dma_address & 0xffff;
293 if (state.ee) m68k_set_irq(7);
294 printf("BUS ERROR FROM DMA: genstat=%04X, bsr0=%04X, bsr1=%04X\n", state.genstat, state.bsr0, state.bsr1);
295 }
296 return (access_ok);
297 }
299 // Logging macros
300 #define LOG_NOT_HANDLED_R(bits) \
301 if (!handled) printf("unhandled read%02d, addr=0x%08X\n", bits, address);
303 #define LOG_NOT_HANDLED_W(bits) \
304 if (!handled) printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
306 /********************************************************
307 * I/O read/write functions
308 ********************************************************/
310 /**
311 * Issue a warning if a read operation is made with an invalid size
312 */
313 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
314 {
315 assert((bits == 8) || (bits == 16) || (bits == 32));
316 if ((bits & allowed) == 0) {
317 printf("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
318 }
319 }
321 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
322 {
323 ENFORCE_SIZE(bits, address, true, allowed, regname);
324 }
326 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
327 {
328 ENFORCE_SIZE(bits, address, false, allowed, regname);
329 }
331 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
332 {
333 bool handled = false;
335 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
336 // I/O register space, zone A
337 switch (address & 0x0F0000) {
338 case 0x010000: // General Status Register
339 if (bits == 16)
340 state.genstat = (data & 0xffff);
341 else if (bits == 8) {
342 if (address & 0)
343 state.genstat = data;
344 else
345 state.genstat = data << 8;
346 }
347 handled = true;
348 break;
349 case 0x030000: // Bus Status Register 0
350 break;
351 case 0x040000: // Bus Status Register 1
352 break;
353 case 0x050000: // Phone status
354 break;
355 case 0x060000: // DMA Count
356 ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
357 state.dma_count = (data & 0x3FFF);
358 state.idmarw = ((data & 0x4000) == 0x4000);
359 state.dmaen = ((data & 0x8000) == 0x8000);
360 // This handles the "dummy DMA transfer" mentioned in the docs
361 // disabled because it causes the floppy test to fail
362 #if 0
363 if (!state.idmarw){
364 if (access_check_dma(true)){
365 uint32_t newAddr = mapAddr(state.dma_address, true);
366 // RAM access
367 if (newAddr <= 0x1fffff)
368 WR16(state.base_ram, newAddr, state.base_ram_size - 1, 0xFF);
369 else if (address <= 0x3FFFFF)
370 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, 0xFF);
371 }
372 }
373 #endif
374 state.dma_count++;
375 handled = true;
376 break;
377 case 0x070000: // Line Printer Status Register
378 break;
379 case 0x080000: // Real Time Clock
380 break;
381 case 0x090000: // Phone registers
382 switch (address & 0x0FF000) {
383 case 0x090000: // Handset relay
384 case 0x098000:
385 break;
386 case 0x091000: // Line select 2
387 case 0x099000:
388 break;
389 case 0x092000: // Hook relay 1
390 case 0x09A000:
391 break;
392 case 0x093000: // Hook relay 2
393 case 0x09B000:
394 break;
395 case 0x094000: // Line 1 hold
396 case 0x09C000:
397 break;
398 case 0x095000: // Line 2 hold
399 case 0x09D000:
400 break;
401 case 0x096000: // Line 1 A-lead
402 case 0x09E000:
403 break;
404 case 0x097000: // Line 2 A-lead
405 case 0x09F000:
406 break;
407 }
408 break;
409 case 0x0A0000: // Miscellaneous Control Register
410 ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
411 // TODO: handle the ctrl bits properly
412 if (data & 0x8000){
413 state.timer_enabled = 1;
414 }else{
415 state.timer_enabled = 0;
416 state.timer_asserted = 0;
417 }
418 state.dma_reading = (data & 0x4000);
419 if (state.leds != ((~data & 0xF00) >> 8)) {
420 state.leds = (~data & 0xF00) >> 8;
421 #ifdef SHOW_LEDS
422 printf("LEDs: %s %s %s %s\n",
423 (state.leds & 8) ? "R" : "-",
424 (state.leds & 4) ? "G" : "-",
425 (state.leds & 2) ? "Y" : "-",
426 (state.leds & 1) ? "R" : "-");
427 #endif
428 }
429 handled = true;
430 break;
431 case 0x0B0000: // TM/DIALWR
432 break;
433 case 0x0C0000: // Clear Status Register
434 state.genstat = 0xFFFF;
435 state.bsr0 = 0xFFFF;
436 state.bsr1 = 0xFFFF;
437 handled = true;
438 break;
439 case 0x0D0000: // DMA Address Register
440 if (address & 0x004000) {
441 // A14 high -- set most significant bits
442 state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
443 } else {
444 // A14 low -- set least significant bits
445 state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
446 }
447 handled = true;
448 break;
449 case 0x0E0000: // Disk Control Register
450 {
451 bool fd_selected;
452 bool hd_selected;
453 ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
454 // B7 = FDD controller reset
455 if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
456 // B6 = drive 0 select
457 fd_selected = (data & 0x40) != 0;
458 // B5 = motor enable -- TODO
459 // B4 = HDD controller reset
460 if ((data & 0x10) == 0) wd2010_reset(&state.hdc_ctx);
461 // B3 = HDD0 select
462 hd_selected = (data & 0x08) != 0;
463 // B2,1,0 = HDD0 head select -- TODO?
464 if (hd_selected && !state.hd_selected){
465 state.fd_selected = false;
466 state.hd_selected = true;
467 }else if (fd_selected && !state.fd_selected){
468 state.hd_selected = false;
469 state.fd_selected = true;
470 }
471 handled = true;
472 break;
473 }
474 case 0x0F0000: // Line Printer Data Register
475 break;
476 }
477 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
478 // I/O register space, zone B
479 switch (address & 0xF00000) {
480 case 0xC00000: // Expansion slots
481 case 0xD00000:
482 switch (address & 0xFC0000) {
483 case 0xC00000: // Expansion slot 0
484 case 0xC40000: // Expansion slot 1
485 case 0xC80000: // Expansion slot 2
486 case 0xCC0000: // Expansion slot 3
487 case 0xD00000: // Expansion slot 4
488 case 0xD40000: // Expansion slot 5
489 case 0xD80000: // Expansion slot 6
490 case 0xDC0000: // Expansion slot 7
491 fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
492 handled = true;
493 break;
494 }
495 break;
496 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
497 case 0xF00000:
498 switch (address & 0x070000) {
499 case 0x000000: // [ef][08]xxxx ==> WD2010 hard disc controller
500 wd2010_write_reg(&state.hdc_ctx, (address >> 1) & 7, data);
501 handled = true;
502 break;
503 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
504 /*ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");*/
505 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
506 handled = true;
507 break;
508 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
509 // MCR2 - UNIX PC Rev. P5.1 HDD head select b3 and potential HDD#2 select
510 wd2010_write_reg(&state.hdc_ctx, UNIXPC_REG_MCR2, data);
511 handled = true;
512 break;
513 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
514 break;
515 case 0x040000: // [ef][4c]xxxx ==> General Control Register
516 switch (address & 0x077000) {
517 case 0x040000: // [ef][4c][08]xxx ==> EE
518 // Error Enable. If =0, Level7 intrs and bus errors are masked.
519 ENFORCE_SIZE_W(bits, address, 16, "EE");
520 state.ee = ((data & 0x8000) == 0x8000);
521 handled = true;
522 break;
523 case 0x041000: // [ef][4c][19]xxx ==> PIE
524 ENFORCE_SIZE_W(bits, address, 16, "PIE");
525 state.pie = ((data & 0x8000) == 0x8000);
526 handled = true;
527 break;
528 case 0x042000: // [ef][4c][2A]xxx ==> BP
529 break;
530 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
531 ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
532 state.romlmap = ((data & 0x8000) == 0x8000);
533 handled = true;
534 break;
535 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
536 ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
537 break;
538 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
539 ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
540 break;
541 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
542 ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
543 break;
544 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
545 ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
546 break;
547 }
548 case 0x050000: // [ef][5d]xxxx ==> 8274
549 break;
550 case 0x060000: // [ef][6e]xxxx ==> Control regs
551 switch (address & 0x07F000) {
552 default:
553 break;
554 }
555 break;
556 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
557 // TODO: figure out which sizes are valid (probably just 8 and 16)
558 // ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER");
559 if (bits == 8) {
560 printf("KBD WR %02X => %02X\n", (address >> 1) & 3, data);
561 keyboard_write(&state.kbd, (address >> 1) & 3, data);
562 handled = true;
563 } else if (bits == 16) {
564 printf("KBD WR %02X => %04X\n", (address >> 1) & 3, data);
565 keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8);
566 handled = true;
567 }
568 break;
569 }
570 }
571 }
573 LOG_NOT_HANDLED_W(bits);
574 }/*}}}*/
576 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
577 {
578 bool handled = false;
579 uint32_t data = EMPTY & 0xFFFFFFFF;
581 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
582 // I/O register space, zone A
583 switch (address & 0x0F0000) {
584 case 0x010000: // General Status Register
585 /* ENFORCE_SIZE_R(bits, address, 16, "GENSTAT"); */
586 if (bits == 32) {
587 return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
588 } else if (bits == 16) {
589 return (uint16_t)state.genstat;
590 } else {
591 return (uint8_t)(state.genstat & 0xff);
592 }
593 break;
594 case 0x030000: // Bus Status Register 0
595 ENFORCE_SIZE_R(bits, address, 16, "BSR0");
596 return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
597 break;
598 case 0x040000: // Bus Status Register 1
599 ENFORCE_SIZE_R(bits, address, 16, "BSR1");
600 return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
601 break;
602 case 0x050000: // Phone status
603 ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
604 break;
605 case 0x060000: // DMA Count
606 // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
607 // Bit 14 is always unused, so leave it set
608 ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
609 return (state.dma_count & 0x3fff) | 0xC000;
610 break;
611 case 0x070000: // Line Printer Status Register
612 data = 0x00120012; // no parity error, no line printer error, no irqs from FDD or HDD
613 data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0;
614 data |= wd2010_get_irq(&state.hdc_ctx) ? 0x00040004 : 0;
615 return data;
616 break;
617 case 0x080000: // Real Time Clock
618 printf("READ NOTIMP: Realtime Clock\n");
619 break;
620 case 0x090000: // Phone registers
621 switch (address & 0x0FF000) {
622 case 0x090000: // Handset relay
623 case 0x098000:
624 break;
625 case 0x091000: // Line select 2
626 case 0x099000:
627 break;
628 case 0x092000: // Hook relay 1
629 case 0x09A000:
630 break;
631 case 0x093000: // Hook relay 2
632 case 0x09B000:
633 break;
634 case 0x094000: // Line 1 hold
635 case 0x09C000:
636 break;
637 case 0x095000: // Line 2 hold
638 case 0x09D000:
639 break;
640 case 0x096000: // Line 1 A-lead
641 case 0x09E000:
642 break;
643 case 0x097000: // Line 2 A-lead
644 case 0x09F000:
645 break;
646 }
647 break;
648 case 0x0A0000: // Miscellaneous Control Register -- write only!
649 handled = true;
650 break;
651 case 0x0B0000: // TM/DIALWR
652 break;
653 case 0x0C0000: // Clear Status Register -- write only!
654 handled = true;
655 break;
656 case 0x0D0000: // DMA Address Register
657 break;
658 case 0x0E0000: // Disk Control Register
659 break;
660 case 0x0F0000: // Line Printer Data Register
661 break;
662 }
663 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
664 // I/O register space, zone B
665 switch (address & 0xF00000) {
666 case 0xC00000: // Expansion slots
667 case 0xD00000:
668 switch (address & 0xFC0000) {
669 case 0xC00000: // Expansion slot 0
670 case 0xC40000: // Expansion slot 1
671 case 0xC80000: // Expansion slot 2
672 case 0xCC0000: // Expansion slot 3
673 case 0xD00000: // Expansion slot 4
674 case 0xD40000: // Expansion slot 5
675 case 0xD80000: // Expansion slot 6
676 case 0xDC0000: // Expansion slot 7
677 fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
678 handled = true;
679 break;
680 }
681 break;
682 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
683 case 0xF00000:
684 switch (address & 0x070000) {
685 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
686 return (wd2010_read_reg(&state.hdc_ctx, (address >> 1) & 7));
688 break;
689 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
690 /*ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");*/
691 return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
692 break;
693 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
694 break;
695 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
696 break;
697 case 0x040000: // [ef][4c]xxxx ==> General Control Register
698 switch (address & 0x077000) {
699 case 0x040000: // [ef][4c][08]xxx ==> EE
700 case 0x041000: // [ef][4c][19]xxx ==> PIE
701 case 0x042000: // [ef][4c][2A]xxx ==> BP
702 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
703 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
704 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
705 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
706 // All write-only registers... TODO: bus error?
707 handled = true;
708 break;
709 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
710 break;
711 }
712 break;
713 case 0x050000: // [ef][5d]xxxx ==> 8274
714 break;
715 case 0x060000: // [ef][6e]xxxx ==> Control regs
716 switch (address & 0x07F000) {
717 default:
718 break;
719 }
720 break;
721 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
722 // TODO: figure out which sizes are valid (probably just 8 and 16)
723 //ENFORCE_SIZE_R(bits, address, 16, "KEYBOARD CONTROLLER");
724 {
725 if (bits == 8) {
726 return keyboard_read(&state.kbd, (address >> 1) & 3);
727 } else {
728 return keyboard_read(&state.kbd, (address >> 1) & 3) << 8;
729 }
730 return data;
731 }
732 break;
733 }
734 }
735 }
737 LOG_NOT_HANDLED_R(bits);
739 return data;
740 }/*}}}*/
743 /********************************************************
744 * m68k memory read/write support functions for Musashi
745 ********************************************************/
748 static uint16_t ram_read_16(uint32_t address)
749 {
750 if (address <= 0x1fffff) {
751 // Base memory wraps around
752 return RD16(state.base_ram, address, state.base_ram_size - 1);
753 } else {
754 if ((address <= (state.exp_ram_size + 0x200000 - 1)) && (address >= 0x200000)){
755 return RD16(state.exp_ram, address - 0x200000, state.exp_ram_size - 1);
756 }else
757 return EMPTY & 0xffff;
758 }
759 }
761 /**
762 * @brief Read M68K memory, 32-bit
763 */
764 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
765 {
766 uint32_t data = EMPTY & 0xFFFFFFFF;
768 // If ROMLMAP is set, force system to access ROM
769 if (!state.romlmap)
770 address |= 0x800000;
772 // Check access permissions
773 ACCESS_CHECK_RD(address, 32);
775 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
776 // ROM access
777 return RD32(state.rom, address, ROM_SIZE - 1);
778 } else if (address <= 0x3fffff) {
779 // RAM access
780 uint32_t newAddr = mapAddr(address, false);
781 // Base memory wraps around
782 data = ((ram_read_16(newAddr) << 16) |
783 ram_read_16(mapAddr(address + 2, false)));
785 return (data);
786 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
787 // I/O register space, zone A
788 switch (address & 0x0F0000) {
789 case 0x000000: // Map RAM access
790 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
791 return RD32(state.map, address, 0x7FF);
792 break;
793 case 0x020000: // Video RAM
794 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
795 return RD32(state.vram, address, 0x7FFF);
796 break;
797 default:
798 return IoRead(address, 32);
799 }
800 } else {
801 return IoRead(address, 32);
802 }
804 return data;
805 }/*}}}*/
807 /**
808 * @brief Read M68K memory, 16-bit
809 */
810 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
811 {
812 uint16_t data = EMPTY & 0xFFFF;
814 // If ROMLMAP is set, force system to access ROM
815 if (!state.romlmap)
816 address |= 0x800000;
818 // Check access permissions
819 ACCESS_CHECK_RD(address, 16);
821 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
822 // ROM access
823 data = RD16(state.rom, address, ROM_SIZE - 1);
824 } else if (address <= 0x3fffff) {
825 // RAM access
826 uint32_t newAddr = mapAddr(address, false);
827 if (newAddr <= 0x1fffff) {
828 // Base memory wraps around
829 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
830 } else {
831 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
832 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
833 else
834 return EMPTY & 0xffff;
835 }
836 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
837 // I/O register space, zone A
838 switch (address & 0x0F0000) {
839 case 0x000000: // Map RAM access
840 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
841 data = RD16(state.map, address, 0x7FF);
842 break;
843 case 0x020000: // Video RAM
844 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
845 data = RD16(state.vram, address, 0x7FFF);
846 break;
847 default:
848 data = IoRead(address, 16);
849 }
850 } else {
851 data = IoRead(address, 16);
852 }
854 return data;
855 }/*}}}*/
857 /**
858 * @brief Read M68K memory, 8-bit
859 */
860 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
861 {
862 uint8_t data = EMPTY & 0xFF;
864 // If ROMLMAP is set, force system to access ROM
865 if (!state.romlmap)
866 address |= 0x800000;
868 // Check access permissions
869 ACCESS_CHECK_RD(address, 8);
871 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
872 // ROM access
873 data = RD8(state.rom, address, ROM_SIZE - 1);
874 } else if (address <= 0x3fffff) {
875 // RAM access
876 uint32_t newAddr = mapAddr(address, false);
877 if (newAddr <= 0x1fffff) {
878 // Base memory wraps around
879 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
880 } else {
881 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
882 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
883 else
884 return EMPTY & 0xff;
885 }
886 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
887 // I/O register space, zone A
888 switch (address & 0x0F0000) {
889 case 0x000000: // Map RAM access
890 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
891 data = RD8(state.map, address, 0x7FF);
892 break;
893 case 0x020000: // Video RAM
894 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
895 data = RD8(state.vram, address, 0x7FFF);
896 break;
897 default:
898 data = IoRead(address, 8);
899 }
900 } else {
901 data = IoRead(address, 8);
902 }
904 return data;
905 }/*}}}*/
908 static void ram_write_16(uint32_t address, uint32_t value)/*{{{*/
909 {
910 if (address <= 0x1fffff) {
911 if (address < state.base_ram_size) {
912 WR16(state.base_ram, address, state.base_ram_size - 1, value);
913 }
914 } else {
915 if ((address - 0x200000) < state.exp_ram_size) {
916 WR16(state.exp_ram, address - 0x200000, state.exp_ram_size - 1, value);
917 }
918 }
919 }
921 /**
922 * @brief Write M68K memory, 32-bit
923 */
924 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
925 {
926 // If ROMLMAP is set, force system to access ROM
927 if (!state.romlmap)
928 address |= 0x800000;
930 // Check access permissions
931 ACCESS_CHECK_WR(address, 32);
932 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
933 // ROM access
934 } else if (address <= 0x3FFFFF) {
935 // RAM access
936 uint32_t newAddr = mapAddr(address, true);
937 ram_write_16(newAddr, (value & 0xffff0000) >> 16);
938 ram_write_16(mapAddr(address + 2, true), (value & 0xffff));
939 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
940 // I/O register space, zone A
941 switch (address & 0x0F0000) {
942 case 0x000000: // Map RAM access
943 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X\n", address);
944 WR32(state.map, address, 0x7FF, value);
945 break;
946 case 0x020000: // Video RAM
947 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X\n", address);
948 WR32(state.vram, address, 0x7FFF, value);
949 break;
950 default:
951 IoWrite(address, value, 32);
952 }
953 } else {
954 IoWrite(address, value, 32);
955 }
956 }/*}}}*/
958 /**
959 * @brief Write M68K memory, 16-bit
960 */
961 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
962 {
963 // If ROMLMAP is set, force system to access ROM
964 if (!state.romlmap)
965 address |= 0x800000;
967 // Check access permissions
968 ACCESS_CHECK_WR(address, 16);
970 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
971 // ROM access
972 } else if (address <= 0x3FFFFF) {
973 // RAM access
974 uint32_t newAddr = mapAddr(address, true);
976 if (newAddr <= 0x1fffff) {
977 if (newAddr < state.base_ram_size) {
978 WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
979 }
980 } else {
981 if ((newAddr - 0x200000) < state.exp_ram_size) {
982 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
983 }
984 }
985 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
986 // I/O register space, zone A
987 switch (address & 0x0F0000) {
988 case 0x000000: // Map RAM access
989 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
990 WR16(state.map, address, 0x7FF, value);
991 break;
992 case 0x020000: // Video RAM
993 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
994 WR16(state.vram, address, 0x7FFF, value);
995 break;
996 default:
997 IoWrite(address, value, 16);
998 }
999 } else {
1000 IoWrite(address, value, 16);
1001 }
1002 }/*}}}*/
1004 /**
1005 * @brief Write M68K memory, 8-bit
1006 */
1007 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
1008 {
1009 // If ROMLMAP is set, force system to access ROM
1010 if (!state.romlmap)
1011 address |= 0x800000;
1013 // Check access permissions
1014 ACCESS_CHECK_WR(address, 8);
1016 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
1017 // ROM access (read only!)
1018 } else if (address <= 0x3FFFFF) {
1019 // RAM access
1020 uint32_t newAddr = mapAddr(address, true);
1021 if (newAddr <= 0x1fffff) {
1022 if (newAddr < state.base_ram_size) {
1023 WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
1024 }
1025 } else {
1026 if ((newAddr - 0x200000) < state.exp_ram_size) {
1027 WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
1028 }
1029 }
1030 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
1031 // I/O register space, zone A
1032 switch (address & 0x0F0000) {
1033 case 0x000000: // Map RAM access
1034 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
1035 WR8(state.map, address, 0x7FF, value);
1036 break;
1037 case 0x020000: // Video RAM
1038 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
1039 WR8(state.vram, address, 0x7FFF, value);
1040 break;
1041 default:
1042 IoWrite(address, value, 8);
1043 }
1044 } else {
1045 IoWrite(address, value, 8);
1046 }
1047 }/*}}}*/
1050 // for the disassembler
1051 uint32_t m68k_read_disassembler_32(uint32_t addr)
1052 {
1053 if (addr < 0x400000) {
1054 uint32_t newAddrHigh, newAddrLow;
1055 newAddrHigh = map_address_debug(addr);
1056 newAddrLow = map_address_debug(addr + 2);
1057 return ((ram_read_16(newAddrHigh) << 16) |
1058 ram_read_16(newAddrLow));
1060 } else {
1061 printf(">>> WARNING Disassembler RD32 out of range 0x%08X\n", addr);
1062 return EMPTY;
1063 }
1064 }
1066 uint32_t m68k_read_disassembler_16(uint32_t addr)
1067 {
1068 if (addr < 0x400000) {
1069 uint16_t page = (addr >> 12) & 0x3FF;
1070 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
1071 uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
1072 if (newAddr <= 0x1fffff) {
1073 if (newAddr >= state.base_ram_size)
1074 return EMPTY & 0xffff;
1075 else
1076 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
1077 } else {
1078 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
1079 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
1080 else
1081 return EMPTY & 0xffff;
1082 }
1083 } else {
1084 printf(">>> WARNING Disassembler RD16 out of range 0x%08X\n", addr);
1085 return EMPTY & 0xffff;
1086 }
1087 }
1089 uint32_t m68k_read_disassembler_8 (uint32_t addr)
1090 {
1091 if (addr < 0x400000) {
1092 uint16_t page = (addr >> 12) & 0x3FF;
1093 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
1094 uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
1095 if (newAddr <= 0x1fffff) {
1096 if (newAddr >= state.base_ram_size)
1097 return EMPTY & 0xff;
1098 else
1099 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
1100 } else {
1101 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
1102 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
1103 else
1104 return EMPTY & 0xff;
1105 }
1106 } else {
1107 printf(">>> WARNING Disassembler RD8 out of range 0x%08X\n", addr);
1108 return EMPTY & 0xff;
1109 }
1110 }