src/memory.c

Tue, 28 Dec 2010 21:47:43 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Tue, 28 Dec 2010 21:47:43 +0000
changeset 72
c66c98c7a768
parent 70
5bbe76e71698
child 77
e7898cbae0c6
child 78
c149c13aff1c
permissions
-rw-r--r--

Only print LED state if it has changed

     1 #include <stdio.h>
     2 #include <stdlib.h>
     3 #include <stdint.h>
     4 #include <stdbool.h>
     5 #include <assert.h>
     6 #include "musashi/m68k.h"
     7 #include "state.h"
     8 #include "memory.h"
    10 /******************
    11  * Memory mapping
    12  ******************/
    14 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
    16 uint32_t mapAddr(uint32_t addr, bool writing)/*{{{*/
    17 {
    18 	if (addr < 0x400000) {
    19 		// RAM access. Check against the Map RAM
    20 		// Start by getting the original page address
    21 		uint16_t page = (addr >> 12) & 0x3FF;
    23 		// Look it up in the map RAM and get the physical page address
    24 		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
    26 		// Update the Page Status bits
    27 		uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
    28 		if (pagebits != 0) {
    29 			if (writing)
    30 				state.map[page*2] |= 0x60;		// Page written to (dirty)
    31 			else
    32 				state.map[page*2] |= 0x40;		// Page accessed but not written
    33 		}
    35 		// Return the address with the new physical page spliced in
    36 		return (new_page_addr << 12) + (addr & 0xFFF);
    37 	} else {
    38 		// I/O, VRAM or MapRAM space; no mapping is performed or required
    39 		// TODO: assert here?
    40 		return addr;
    41 	}
    42 }/*}}}*/
    44 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)/*{{{*/
    45 {
    46 	// Are we in Supervisor mode?
    47 	if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
    48 		// Yes. We can do anything we like.
    49 		return MEM_ALLOWED;
    51 	// If we're here, then we must be in User mode.
    52 	// Check that the user didn't access memory outside of the RAM area
    53 	if (addr >= 0x400000)
    54 		return MEM_UIE;
    56 	// This leaves us with Page Fault checking. Get the page bits for this page.
    57 	uint16_t page = (addr >> 12) & 0x3FF;
    58 	uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
    60 	// Check page is present
    61 	if ((pagebits & 0x03) == 0)
    62 		return MEM_PAGEFAULT;
    64 	// User attempt to access the kernel
    65 	// A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
    66 	if (((addr >> 19) & 0x0F) == 0)
    67 		return MEM_KERNEL;
    69 	// Check page is write enabled
    70 	if (writing && ((pagebits & 0x04) == 0))
    71 		return MEM_PAGE_NO_WE;
    73 	// Page access allowed.
    74 	return MEM_ALLOWED;
    75 }/*}}}*/
    77 #undef MAPRAM
    80 /********************************************************
    81  * m68k memory read/write support functions for Musashi
    82  ********************************************************/
    84 /**
    85  * @brief	Check memory access permissions for a write operation.
    86  * @note	This used to be a single macro (merged with ACCESS_CHECK_RD), but
    87  * 			gcc throws warnings when you have a return-with-value in a void
    88  * 			function, even if the return-with-value is completely unreachable.
    89  * 			Similarly it doesn't like it if you have a return without a value
    90  * 			in a non-void function, even if it's impossible to ever reach the
    91  * 			return-with-no-value. UGH!
    92  */
    93 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
    94 #define ACCESS_CHECK_WR(address, bits)								\
    95 	do {															\
    96 		bool fault = false;											\
    97 		/* MEM_STATUS st; */										\
    98 		switch (checkMemoryAccess(address, true)) {					\
    99 			case MEM_ALLOWED:										\
   100 				/* Access allowed */								\
   101 				break;												\
   102 			case MEM_PAGEFAULT:										\
   103 				/* Page fault */									\
   104 				state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0);	\
   105 				fault = true;										\
   106 				break;												\
   107 			case MEM_UIE:											\
   108 				/* User access to memory above 4MB */				\
   109 				state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0);	\
   110 				fault = true;										\
   111 				break;												\
   112 			case MEM_KERNEL:										\
   113 			case MEM_PAGE_NO_WE:									\
   114 				/* kernel access or page not write enabled */		\
   115 				/* FIXME: which regs need setting? */				\
   116 				fault = true;										\
   117 				break;												\
   118 		}															\
   119 																	\
   120 		if (fault) {												\
   121 			if (bits >= 16)											\
   122 				state.bsr0 = 0x7C00;								\
   123 			else													\
   124 				state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00;		\
   125 			state.bsr0 |= (address >> 16);							\
   126 			state.bsr1 = address & 0xffff;							\
   127 			printf("ERR: BusError WR\n");							\
   128 			m68k_pulse_bus_error();									\
   129 			return;													\
   130 		}															\
   131 	} while (0)
   132 /*}}}*/
   134 /**
   135  * @brief Check memory access permissions for a read operation.
   136  * @note	This used to be a single macro (merged with ACCESS_CHECK_WR), but
   137  * 			gcc throws warnings when you have a return-with-value in a void
   138  * 			function, even if the return-with-value is completely unreachable.
   139  * 			Similarly it doesn't like it if you have a return without a value
   140  * 			in a non-void function, even if it's impossible to ever reach the
   141  * 			return-with-no-value. UGH!
   142  */
   143 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
   144 #define ACCESS_CHECK_RD(address, bits)								\
   145 	do {															\
   146 		bool fault = false;											\
   147 		/* MEM_STATUS st; */										\
   148 		switch (checkMemoryAccess(address, false)) {				\
   149 			case MEM_ALLOWED:										\
   150 				/* Access allowed */								\
   151 				break;												\
   152 			case MEM_PAGEFAULT:										\
   153 				/* Page fault */									\
   154 				state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0);	\
   155 				fault = true;										\
   156 				break;												\
   157 			case MEM_UIE:											\
   158 				/* User access to memory above 4MB */				\
   159 				state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0);	\
   160 				fault = true;										\
   161 				break;												\
   162 			case MEM_KERNEL:										\
   163 			case MEM_PAGE_NO_WE:									\
   164 				/* kernel access or page not write enabled */		\
   165 				/* FIXME: which regs need setting? */				\
   166 				fault = true;										\
   167 				break;												\
   168 		}															\
   169 																	\
   170 		if (fault) {												\
   171 			if (bits >= 16)											\
   172 				state.bsr0 = 0x7C00;								\
   173 			else													\
   174 				state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00;		\
   175 			state.bsr0 |= (address >> 16);							\
   176 			state.bsr1 = address & 0xffff;							\
   177 			printf("ERR: BusError RD\n");							\
   178 			m68k_pulse_bus_error();									\
   179 			return 0xFFFFFFFF;										\
   180 		}															\
   181 	} while (0)
   182 /*}}}*/
   184 // Logging macros
   185 #define LOG_NOT_HANDLED_R(bits)															\
   186 	if (!handled) printf("unhandled read%02d, addr=0x%08X\n", bits, address);
   188 #define LOG_NOT_HANDLED_W(bits)															\
   189 	if (!handled) printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
   191 /********************************************************
   192  * I/O read/write functions
   193  ********************************************************/
   195 /**
   196  * Issue a warning if a read operation is made with an invalid size
   197  */
   198 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
   199 {
   200 	assert((bits == 8) || (bits == 16) || (bits == 32));
   201 	if ((bits & allowed) == 0) {
   202 		printf("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
   203 	}
   204 }
   206 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
   207 {
   208 	ENFORCE_SIZE(bits, address, true, allowed, regname);
   209 }
   211 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
   212 {
   213 	ENFORCE_SIZE(bits, address, false, allowed, regname);
   214 }
   216 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
   217 {
   218 	bool handled = false;
   220 	if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   221 		// I/O register space, zone A
   222 		switch (address & 0x0F0000) {
   223 			case 0x010000:				// General Status Register
   224 				if (bits == 16)
   225 					state.genstat = (data & 0xffff);
   226 				else if (bits == 8) {
   227 					if (address & 0)
   228 						state.genstat = data;
   229 					else
   230 						state.genstat = data << 8;
   231 				}
   232 				handled = true;
   233 				break;
   234 			case 0x030000:				// Bus Status Register 0
   235 				break;
   236 			case 0x040000:				// Bus Status Register 1
   237 				break;
   238 			case 0x050000:				// Phone status
   239 				break;
   240 			case 0x060000:				// DMA Count
   241 				ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
   242 				state.dma_count = (data & 0x3FFF);
   243 				state.idmarw = ((data & 0x4000) == 0x4000);
   244 				state.dmaen = ((data & 0x8000) == 0x8000);
   245 				// This handles the "dummy DMA transfer" mentioned in the docs
   246 				// TODO: access check, peripheral access
   247 				if (!state.idmarw)
   248 					WR32(state.base_ram, mapAddr(address, true), state.base_ram_size - 1, 0xDEAD);
   249 				state.dma_count++;
   250 				handled = true;
   251 				break;
   252 			case 0x070000:				// Line Printer Status Register
   253 				break;
   254 			case 0x080000:				// Real Time Clock
   255 				break;
   256 			case 0x090000:				// Phone registers
   257 				switch (address & 0x0FF000) {
   258 					case 0x090000:		// Handset relay
   259 					case 0x098000:
   260 						break;
   261 					case 0x091000:		// Line select 2
   262 					case 0x099000:
   263 						break;
   264 					case 0x092000:		// Hook relay 1
   265 					case 0x09A000:
   266 						break;
   267 					case 0x093000:		// Hook relay 2
   268 					case 0x09B000:
   269 						break;
   270 					case 0x094000:		// Line 1 hold
   271 					case 0x09C000:
   272 						break;
   273 					case 0x095000:		// Line 2 hold
   274 					case 0x09D000:
   275 						break;
   276 					case 0x096000:		// Line 1 A-lead
   277 					case 0x09E000:
   278 						break;
   279 					case 0x097000:		// Line 2 A-lead
   280 					case 0x09F000:
   281 						break;
   282 				}
   283 				break;
   284 			case 0x0A0000:				// Miscellaneous Control Register
   285 				ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
   286 				// TODO: handle the ctrl bits properly
   287 				// TODO: &0x8000 --> dismiss 60hz intr
   288 				state.dma_reading = (data & 0x4000);
   289 				if (state.leds != ((~data & 0xF00) >> 8)) {
   290 					state.leds = (~data & 0xF00) >> 8;
   291 					printf("LEDs: %s %s %s %s\n",
   292 							(state.leds & 8) ? "R" : "-",
   293 							(state.leds & 4) ? "G" : "-",
   294 							(state.leds & 2) ? "Y" : "-",
   295 							(state.leds & 1) ? "R" : "-");
   296 				}
   297 				handled = true;
   298 				break;
   299 			case 0x0B0000:				// TM/DIALWR
   300 				break;
   301 			case 0x0C0000:				// Clear Status Register
   302 				state.genstat = 0xFFFF;
   303 				state.bsr0 = 0xFFFF;
   304 				state.bsr1 = 0xFFFF;
   305 				handled = true;
   306 				break;
   307 			case 0x0D0000:				// DMA Address Register
   308 				if (address & 0x004000) {
   309 					// A14 high -- set most significant bits
   310 					state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
   311 				} else {
   312 					// A14 low -- set least significant bits
   313 					state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
   314 				}
   315 				handled = true;
   316 				break;
   317 			case 0x0E0000:				// Disk Control Register
   318 				ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
   319 				// B7 = FDD controller reset
   320 				if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
   321 				// B6 = drive 0 select -- TODO
   322 				// B5 = motor enable -- TODO
   323 				// B4 = HDD controller reset -- TODO
   324 				// B3 = HDD0 select -- TODO
   325 				// B2,1,0 = HDD0 head select
   326 				handled = true;
   327 				break;
   328 			case 0x0F0000:				// Line Printer Data Register
   329 				break;
   330 		}
   331 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   332 		// I/O register space, zone B
   333 		switch (address & 0xF00000) {
   334 			case 0xC00000:				// Expansion slots
   335 			case 0xD00000:
   336 				switch (address & 0xFC0000) {
   337 					case 0xC00000:		// Expansion slot 0
   338 					case 0xC40000:		// Expansion slot 1
   339 					case 0xC80000:		// Expansion slot 2
   340 					case 0xCC0000:		// Expansion slot 3
   341 					case 0xD00000:		// Expansion slot 4
   342 					case 0xD40000:		// Expansion slot 5
   343 					case 0xD80000:		// Expansion slot 6
   344 					case 0xDC0000:		// Expansion slot 7
   345 						fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
   346 						handled = true;
   347 						break;
   348 				}
   349 				break;
   350 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   351 			case 0xF00000:
   352 				switch (address & 0x070000) {
   353 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   354 						break;
   355 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   356 						ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");
   357 						wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
   358 						handled = true;
   359 						break;
   360 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   361 						break;
   362 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   363 						break;
   364 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   365 						switch (address & 0x077000) {
   366 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   367 								break;
   368 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   369 								ENFORCE_SIZE_W(bits, address, 16, "PIE");
   370 								state.pie = ((data & 0x8000) == 0x8000);
   371 								handled = true;
   372 								break;
   373 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   374 								break;
   375 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   376 								ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
   377 								state.romlmap = ((data & 0x8000) == 0x8000);
   378 								handled = true;
   379 								break;
   380 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   381 								ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
   382 								break;
   383 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   384 								ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
   385 								break;
   386 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   387 								ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
   388 								break;
   389 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   390 								ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
   391 								break;
   392 						}
   393 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   394 						break;
   395 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   396 						switch (address & 0x07F000) {
   397 							default:
   398 								break;
   399 						}
   400 						break;
   401 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   402 						break;
   403 				}
   404 		}
   405 	}
   407 	LOG_NOT_HANDLED_W(bits);
   408 }/*}}}*/
   410 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
   411 {
   412 	bool handled = false;
   413 	uint32_t data = 0xFFFFFFFF;
   415 	if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   416 		// I/O register space, zone A
   417 		switch (address & 0x0F0000) {
   418 			case 0x010000:				// General Status Register
   419 				ENFORCE_SIZE_R(bits, address, 16, "GENSTAT");
   420 				return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
   421 				break;
   422 			case 0x030000:				// Bus Status Register 0
   423 				ENFORCE_SIZE_R(bits, address, 16, "BSR0");
   424 				return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
   425 				break;
   426 			case 0x040000:				// Bus Status Register 1
   427 				ENFORCE_SIZE_R(bits, address, 16, "BSR1");
   428 				return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
   429 				break;
   430 			case 0x050000:				// Phone status
   431 				ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
   432 				break;
   433 			case 0x060000:				// DMA Count
   434 				// TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
   435 				// Bit 14 is always unused, so leave it set
   436 				ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
   437 				return (state.dma_count & 0x3fff) | 0xC000;
   438 				break;
   439 			case 0x070000:				// Line Printer Status Register
   440 				data = 0x00120012;	// no parity error, no line printer error, no irqs from FDD or HDD
   441 				data |= (state.fdc_ctx.irql) ? 0x00080008 : 0;	// FIXME! HACKHACKHACK! shouldn't peek inside FDC structs like this
   442 				return data;
   443 				break;
   444 			case 0x080000:				// Real Time Clock
   445 				printf("READ NOTIMP: Realtime Clock\n");
   446 				break;
   447 			case 0x090000:				// Phone registers
   448 				switch (address & 0x0FF000) {
   449 					case 0x090000:		// Handset relay
   450 					case 0x098000:
   451 						break;
   452 					case 0x091000:		// Line select 2
   453 					case 0x099000:
   454 						break;
   455 					case 0x092000:		// Hook relay 1
   456 					case 0x09A000:
   457 						break;
   458 					case 0x093000:		// Hook relay 2
   459 					case 0x09B000:
   460 						break;
   461 					case 0x094000:		// Line 1 hold
   462 					case 0x09C000:
   463 						break;
   464 					case 0x095000:		// Line 2 hold
   465 					case 0x09D000:
   466 						break;
   467 					case 0x096000:		// Line 1 A-lead
   468 					case 0x09E000:
   469 						break;
   470 					case 0x097000:		// Line 2 A-lead
   471 					case 0x09F000:
   472 						break;
   473 				}
   474 				break;
   475 			case 0x0A0000:				// Miscellaneous Control Register -- write only!
   476 				handled = true;
   477 				break;
   478 			case 0x0B0000:				// TM/DIALWR
   479 				break;
   480 			case 0x0C0000:				// Clear Status Register -- write only!
   481 				handled = true;
   482 				break;
   483 			case 0x0D0000:				// DMA Address Register
   484 				break;
   485 			case 0x0E0000:				// Disk Control Register
   486 				break;
   487 			case 0x0F0000:				// Line Printer Data Register
   488 				break;
   489 		}
   490 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   491 		// I/O register space, zone B
   492 		switch (address & 0xF00000) {
   493 			case 0xC00000:				// Expansion slots
   494 			case 0xD00000:
   495 				switch (address & 0xFC0000) {
   496 					case 0xC00000:		// Expansion slot 0
   497 					case 0xC40000:		// Expansion slot 1
   498 					case 0xC80000:		// Expansion slot 2
   499 					case 0xCC0000:		// Expansion slot 3
   500 					case 0xD00000:		// Expansion slot 4
   501 					case 0xD40000:		// Expansion slot 5
   502 					case 0xD80000:		// Expansion slot 6
   503 					case 0xDC0000:		// Expansion slot 7
   504 						fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
   505 						handled = true;
   506 						break;
   507 				}
   508 				break;
   509 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   510 			case 0xF00000:
   511 				switch (address & 0x070000) {
   512 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   513 						break;
   514 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   515 						ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");
   516 						return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
   517 						break;
   518 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   519 						break;
   520 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   521 						break;
   522 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   523 						switch (address & 0x077000) {
   524 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   525 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   526 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   527 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   528 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   529 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   530 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   531 								// All write-only registers... TODO: bus error?
   532 								handled = true;
   533 								break;
   534 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
   535 								break;
   536 						}
   537 						break;
   538 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   539 						break;
   540 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   541 						switch (address & 0x07F000) {
   542 							default:
   543 								break;
   544 						}
   545 						break;
   546 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   547 						break;
   548 				}
   549 		}
   550 	}
   552 	LOG_NOT_HANDLED_R(bits);
   554 	return data;
   555 }/*}}}*/
   558 /********************************************************
   559  * m68k memory read/write support functions for Musashi
   560  ********************************************************/
   562 /**
   563  * @brief Read M68K memory, 32-bit
   564  */
   565 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
   566 {
   567 	uint32_t data = 0xFFFFFFFF;
   569 	// If ROMLMAP is set, force system to access ROM
   570 	if (!state.romlmap)
   571 		address |= 0x800000;
   573 	// Check access permissions
   574 	ACCESS_CHECK_RD(address, 32);
   576 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   577 		// ROM access
   578 		return RD32(state.rom, address, ROM_SIZE - 1);
   579 	} else if (address <= 0x3fffff) {
   580 		// RAM access
   581 		uint32_t newAddr = mapAddr(address, false);
   582 		if (newAddr <= 0x1fffff) {
   583 			return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
   584 		} else {
   585 			if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
   586 				return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   587 			else
   588 				return 0xffffffff;
   589 		}
   590 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   591 		// I/O register space, zone A
   592 		switch (address & 0x0F0000) {
   593 			case 0x000000:				// Map RAM access
   594 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
   595 				return RD32(state.map, address, 0x7FF);
   596 				break;
   597 			case 0x020000:				// Video RAM
   598 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
   599 				return RD32(state.vram, address, 0x7FFF);
   600 				break;
   601 			default:
   602 				return IoRead(address, 32);
   603 		}
   604 	} else {
   605 		return IoRead(address, 32);
   606 	}
   608 	return data;
   609 }/*}}}*/
   611 /**
   612  * @brief Read M68K memory, 16-bit
   613  */
   614 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
   615 {
   616 	uint16_t data = 0xFFFF;
   618 	// If ROMLMAP is set, force system to access ROM
   619 	if (!state.romlmap)
   620 		address |= 0x800000;
   622 	// Check access permissions
   623 	ACCESS_CHECK_RD(address, 16);
   625 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   626 		// ROM access
   627 		data = RD16(state.rom, address, ROM_SIZE - 1);
   628 	} else if (address <= 0x3fffff) {
   629 		// RAM access
   630 		uint32_t newAddr = mapAddr(address, false);
   631 		if (newAddr <= 0x1fffff) {
   632 			return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
   633 		} else {
   634 			if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
   635 				return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   636 			else
   637 				return 0xffff;
   638 		}
   639 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   640 		// I/O register space, zone A
   641 		switch (address & 0x0F0000) {
   642 			case 0x000000:				// Map RAM access
   643 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
   644 				data = RD16(state.map, address, 0x7FF);
   645 				break;
   646 			case 0x020000:				// Video RAM
   647 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
   648 				data = RD16(state.vram, address, 0x7FFF);
   649 				break;
   650 			default:
   651 				data = IoRead(address, 16);
   652 		}
   653 	} else {
   654 		data = IoRead(address, 16);
   655 	}
   657 	return data;
   658 }/*}}}*/
   660 /**
   661  * @brief Read M68K memory, 8-bit
   662  */
   663 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
   664 {
   665 	uint8_t data = 0xFF;
   667 	// If ROMLMAP is set, force system to access ROM
   668 	if (!state.romlmap)
   669 		address |= 0x800000;
   671 	// Check access permissions
   672 	ACCESS_CHECK_RD(address, 8);
   674 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   675 		// ROM access
   676 		data = RD8(state.rom, address, ROM_SIZE - 1);
   677 	} else if (address <= 0x3fffff) {
   678 		// RAM access
   679 		uint32_t newAddr = mapAddr(address, false);
   680 		if (newAddr <= 0x1fffff) {
   681 			return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
   682 		} else {
   683 			if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
   684 				return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   685 			else
   686 				return 0xff;
   687 		}
   688 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   689 		// I/O register space, zone A
   690 		switch (address & 0x0F0000) {
   691 			case 0x000000:				// Map RAM access
   692 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
   693 				data = RD8(state.map, address, 0x7FF);
   694 				break;
   695 			case 0x020000:				// Video RAM
   696 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
   697 				data = RD8(state.vram, address, 0x7FFF);
   698 				break;
   699 			default:
   700 				data = IoRead(address, 8);
   701 		}
   702 	} else {
   703 		data = IoRead(address, 8);
   704 	}
   706 	return data;
   707 }/*}}}*/
   709 /**
   710  * @brief Write M68K memory, 32-bit
   711  */
   712 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
   713 {
   714 	// If ROMLMAP is set, force system to access ROM
   715 	if (!state.romlmap)
   716 		address |= 0x800000;
   718 	// Check access permissions
   719 	ACCESS_CHECK_WR(address, 32);
   721 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   722 		// ROM access
   723 	} else if (address <= 0x3FFFFF) {
   724 		// RAM access
   725 		uint32_t newAddr = mapAddr(address, true);
   726 		if (newAddr <= 0x1fffff)
   727 			WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
   728 		else
   729 			WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   730 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   731 		// I/O register space, zone A
   732 		switch (address & 0x0F0000) {
   733 			case 0x000000:				// Map RAM access
   734 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
   735 				WR32(state.map, address, 0x7FF, value);
   736 				break;
   737 			case 0x020000:				// Video RAM
   738 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
   739 				WR32(state.vram, address, 0x7FFF, value);
   740 				break;
   741 			default:
   742 				IoWrite(address, value, 32);
   743 		}
   744 	} else {
   745 		IoWrite(address, value, 32);
   746 	}
   747 }/*}}}*/
   749 /**
   750  * @brief Write M68K memory, 16-bit
   751  */
   752 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
   753 {
   754 	// If ROMLMAP is set, force system to access ROM
   755 	if (!state.romlmap)
   756 		address |= 0x800000;
   758 	// Check access permissions
   759 	ACCESS_CHECK_WR(address, 16);
   761 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   762 		// ROM access
   763 	} else if (address <= 0x3FFFFF) {
   764 		// RAM access
   765 		uint32_t newAddr = mapAddr(address, true);
   766 		if (newAddr <= 0x1fffff)
   767 			WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
   768 		else
   769 			WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   770 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   771 		// I/O register space, zone A
   772 		switch (address & 0x0F0000) {
   773 			case 0x000000:				// Map RAM access
   774 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   775 				WR16(state.map, address, 0x7FF, value);
   776 				break;
   777 			case 0x020000:				// Video RAM
   778 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   779 				WR16(state.vram, address, 0x7FFF, value);
   780 				break;
   781 			default:
   782 				IoWrite(address, value, 16);
   783 		}
   784 	} else {
   785 		IoWrite(address, value, 16);
   786 	}
   787 }/*}}}*/
   789 /**
   790  * @brief Write M68K memory, 8-bit
   791  */
   792 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
   793 {
   794 	// If ROMLMAP is set, force system to access ROM
   795 	if (!state.romlmap)
   796 		address |= 0x800000;
   798 	// Check access permissions
   799 	ACCESS_CHECK_WR(address, 8);
   801 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   802 		// ROM access (read only!)
   803 	} else if (address <= 0x3FFFFF) {
   804 		// RAM access
   805 		uint32_t newAddr = mapAddr(address, true);
   806 		if (newAddr <= 0x1fffff)
   807 			WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
   808 		else
   809 			WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   810 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   811 		// I/O register space, zone A
   812 		switch (address & 0x0F0000) {
   813 			case 0x000000:				// Map RAM access
   814 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   815 				WR8(state.map, address, 0x7FF, value);
   816 				break;
   817 			case 0x020000:				// Video RAM
   818 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   819 				WR8(state.vram, address, 0x7FFF, value);
   820 				break;
   821 			default:
   822 				IoWrite(address, value, 8);
   823 		}
   824 	} else {
   825 		IoWrite(address, value, 8);
   826 	}
   827 }/*}}}*/
   830 // for the disassembler
   831 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
   832 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
   833 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }