src/memory.c

Thu, 03 Mar 2011 13:05:21 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Thu, 03 Mar 2011 13:05:21 +0000
changeset 100
d6f699f89303
parent 97
240e195e4bed
child 102
4e1c29899aca
permissions
-rw-r--r--

Fix broken pagebit update code (was failing S4TEST 19 Map Translation test)

     1 #include <stdio.h>
     2 #include <stdlib.h>
     3 #include <stdint.h>
     4 #include <stdbool.h>
     5 #include <assert.h>
     6 #include "musashi/m68k.h"
     7 #include "state.h"
     8 #include "utils.h"
     9 #include "memory.h"
    11 /******************
    12  * Memory mapping
    13  ******************/
    15 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
    17 uint32_t mapAddr(uint32_t addr, bool writing)/*{{{*/
    18 {
    19 	if (addr < 0x400000) {
    20 		// RAM access. Check against the Map RAM
    21 		// Start by getting the original page address
    22 		uint16_t page = (addr >> 12) & 0x3FF;
    24 		// Look it up in the map RAM and get the physical page address
    25 		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
    27 		// Update the Page Status bits
    28 		uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
    29 		// Pagebits --
    30 		//   0 = not present
    31 		//   1 = present but not accessed
    32 		//   2 = present, accessed (read from)
    33 		//   3 = present, dirty (written to)
    34 		switch (pagebits) {
    35 			case 0:
    36 				// Page not present
    37 				// This should cause a page fault
    38 				LOGS("Whoa! Pagebit update, when the page is not present!");
    39 				break;
    41 			case 1:
    42 				// Page present -- first access
    43 				state.map[page*2] &= 0x1F;	// turn off "present" bit
    44 				if (writing)
    45 					state.map[page*2] |= 0x60;		// Page written to (dirty)
    46 				else
    47 					state.map[page*2] |= 0x40;		// Page accessed but not written
    48 				break;
    50 			case 2:
    51 			case 3:
    52 				// Page present, 2nd or later access
    53 				if (writing)
    54 					state.map[page*2] |= 0x60;		// Page written to (dirty)
    55 				break;
    56 		}
    58 		// Return the address with the new physical page spliced in
    59 		return (new_page_addr << 12) + (addr & 0xFFF);
    60 	} else {
    61 		// I/O, VRAM or MapRAM space; no mapping is performed or required
    62 		// TODO: assert here?
    63 		return addr;
    64 	}
    65 }/*}}}*/
    67 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)/*{{{*/
    68 {
    69 	// Are we in Supervisor mode?
    70 	if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
    71 		// Yes. We can do anything we like.
    72 		return MEM_ALLOWED;
    74 	// If we're here, then we must be in User mode.
    75 	// Check that the user didn't access memory outside of the RAM area
    76 	if (addr >= 0x400000)
    77 		return MEM_UIE;
    79 	// This leaves us with Page Fault checking. Get the page bits for this page.
    80 	uint16_t page = (addr >> 12) & 0x3FF;
    81 	uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
    83 	// Check page is present
    84 	if ((pagebits & 0x03) == 0)
    85 		return MEM_PAGEFAULT;
    87 	// User attempt to access the kernel
    88 	// A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
    89 	if (((addr >> 19) & 0x0F) == 0)
    90 		return MEM_KERNEL;
    92 	// Check page is write enabled
    93 	if (writing && ((pagebits & 0x04) == 0))
    94 		return MEM_PAGE_NO_WE;
    96 	// Page access allowed.
    97 	return MEM_ALLOWED;
    98 }/*}}}*/
   100 #undef MAPRAM
   103 /********************************************************
   104  * m68k memory read/write support functions for Musashi
   105  ********************************************************/
   107 /**
   108  * @brief	Check memory access permissions for a write operation.
   109  * @note	This used to be a single macro (merged with ACCESS_CHECK_RD), but
   110  * 			gcc throws warnings when you have a return-with-value in a void
   111  * 			function, even if the return-with-value is completely unreachable.
   112  * 			Similarly it doesn't like it if you have a return without a value
   113  * 			in a non-void function, even if it's impossible to ever reach the
   114  * 			return-with-no-value. UGH!
   115  */
   116 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
   117 #define ACCESS_CHECK_WR(address, bits)								\
   118 	do {															\
   119 		bool fault = false;											\
   120 		/* MEM_STATUS st; */										\
   121 		switch (checkMemoryAccess(address, true)) {					\
   122 			case MEM_ALLOWED:										\
   123 				/* Access allowed */								\
   124 				break;												\
   125 			case MEM_PAGEFAULT:										\
   126 				/* Page fault */									\
   127 				state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0);	\
   128 				fault = true;										\
   129 				break;												\
   130 			case MEM_UIE:											\
   131 				/* User access to memory above 4MB */				\
   132 				state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0);	\
   133 				fault = true;										\
   134 				break;												\
   135 			case MEM_KERNEL:										\
   136 			case MEM_PAGE_NO_WE:									\
   137 				/* kernel access or page not write enabled */		\
   138 				/* FIXME: which regs need setting? */				\
   139 				fault = true;										\
   140 				break;												\
   141 		}															\
   142 																	\
   143 		if (fault) {												\
   144 			if (bits >= 16)											\
   145 				state.bsr0 = 0x7C00;								\
   146 			else													\
   147 				state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00;		\
   148 			state.bsr0 |= (address >> 16);							\
   149 			state.bsr1 = address & 0xffff;							\
   150 			printf("ERR: BusError WR\n");							\
   151 			m68k_pulse_bus_error();									\
   152 			return;													\
   153 		}															\
   154 	} while (0)
   155 /*}}}*/
   157 /**
   158  * @brief Check memory access permissions for a read operation.
   159  * @note	This used to be a single macro (merged with ACCESS_CHECK_WR), but
   160  * 			gcc throws warnings when you have a return-with-value in a void
   161  * 			function, even if the return-with-value is completely unreachable.
   162  * 			Similarly it doesn't like it if you have a return without a value
   163  * 			in a non-void function, even if it's impossible to ever reach the
   164  * 			return-with-no-value. UGH!
   165  */
   166 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
   167 #define ACCESS_CHECK_RD(address, bits)								\
   168 	do {															\
   169 		bool fault = false;											\
   170 		/* MEM_STATUS st; */										\
   171 		switch (checkMemoryAccess(address, false)) {				\
   172 			case MEM_ALLOWED:										\
   173 				/* Access allowed */								\
   174 				break;												\
   175 			case MEM_PAGEFAULT:										\
   176 				/* Page fault */									\
   177 				state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0);	\
   178 				fault = true;										\
   179 				break;												\
   180 			case MEM_UIE:											\
   181 				/* User access to memory above 4MB */				\
   182 				state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0);	\
   183 				fault = true;										\
   184 				break;												\
   185 			case MEM_KERNEL:										\
   186 			case MEM_PAGE_NO_WE:									\
   187 				/* kernel access or page not write enabled */		\
   188 				/* FIXME: which regs need setting? */				\
   189 				fault = true;										\
   190 				break;												\
   191 		}															\
   192 																	\
   193 		if (fault) {												\
   194 			if (bits >= 16)											\
   195 				state.bsr0 = 0x7C00;								\
   196 			else													\
   197 				state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00;		\
   198 			state.bsr0 |= (address >> 16);							\
   199 			state.bsr1 = address & 0xffff;							\
   200 			printf("ERR: BusError RD\n");							\
   201 			m68k_pulse_bus_error();									\
   202 			return 0xFFFFFFFF;										\
   203 		}															\
   204 	} while (0)
   205 /*}}}*/
   207 // Logging macros
   208 #define LOG_NOT_HANDLED_R(bits)															\
   209 	if (!handled) printf("unhandled read%02d, addr=0x%08X\n", bits, address);
   211 #define LOG_NOT_HANDLED_W(bits)															\
   212 	if (!handled) printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
   214 /********************************************************
   215  * I/O read/write functions
   216  ********************************************************/
   218 /**
   219  * Issue a warning if a read operation is made with an invalid size
   220  */
   221 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
   222 {
   223 	assert((bits == 8) || (bits == 16) || (bits == 32));
   224 	if ((bits & allowed) == 0) {
   225 		printf("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
   226 	}
   227 }
   229 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
   230 {
   231 	ENFORCE_SIZE(bits, address, true, allowed, regname);
   232 }
   234 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
   235 {
   236 	ENFORCE_SIZE(bits, address, false, allowed, regname);
   237 }
   239 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
   240 {
   241 	bool handled = false;
   243 	if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   244 		// I/O register space, zone A
   245 		switch (address & 0x0F0000) {
   246 			case 0x010000:				// General Status Register
   247 				if (bits == 16)
   248 					state.genstat = (data & 0xffff);
   249 				else if (bits == 8) {
   250 					if (address & 0)
   251 						state.genstat = data;
   252 					else
   253 						state.genstat = data << 8;
   254 				}
   255 				handled = true;
   256 				break;
   257 			case 0x030000:				// Bus Status Register 0
   258 				break;
   259 			case 0x040000:				// Bus Status Register 1
   260 				break;
   261 			case 0x050000:				// Phone status
   262 				break;
   263 			case 0x060000:				// DMA Count
   264 				ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
   265 				state.dma_count = (data & 0x3FFF);
   266 				state.idmarw = ((data & 0x4000) == 0x4000);
   267 				state.dmaen = ((data & 0x8000) == 0x8000);
   268 				// This handles the "dummy DMA transfer" mentioned in the docs
   269 				// TODO: access check, peripheral access
   270 				if (!state.idmarw)
   271 					WR32(state.base_ram, mapAddr(address, true), state.base_ram_size - 1, 0xDEAD);
   272 				state.dma_count++;
   273 				handled = true;
   274 				break;
   275 			case 0x070000:				// Line Printer Status Register
   276 				break;
   277 			case 0x080000:				// Real Time Clock
   278 				break;
   279 			case 0x090000:				// Phone registers
   280 				switch (address & 0x0FF000) {
   281 					case 0x090000:		// Handset relay
   282 					case 0x098000:
   283 						break;
   284 					case 0x091000:		// Line select 2
   285 					case 0x099000:
   286 						break;
   287 					case 0x092000:		// Hook relay 1
   288 					case 0x09A000:
   289 						break;
   290 					case 0x093000:		// Hook relay 2
   291 					case 0x09B000:
   292 						break;
   293 					case 0x094000:		// Line 1 hold
   294 					case 0x09C000:
   295 						break;
   296 					case 0x095000:		// Line 2 hold
   297 					case 0x09D000:
   298 						break;
   299 					case 0x096000:		// Line 1 A-lead
   300 					case 0x09E000:
   301 						break;
   302 					case 0x097000:		// Line 2 A-lead
   303 					case 0x09F000:
   304 						break;
   305 				}
   306 				break;
   307 			case 0x0A0000:				// Miscellaneous Control Register
   308 				ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
   309 				// TODO: handle the ctrl bits properly
   310 				// TODO: &0x8000 --> dismiss 60hz intr
   311 				if (data & 0x8000){
   312 					state.timer_enabled = 1;
   313 				}else{
   314 					state.timer_enabled = 0;
   315 					state.timer_asserted = 0;
   316 				}
   317 				state.dma_reading = (data & 0x4000);
   318 				if (state.leds != ((~data & 0xF00) >> 8)) {
   319 					state.leds = (~data & 0xF00) >> 8;
   320 					printf("LEDs: %s %s %s %s\n",
   321 							(state.leds & 8) ? "R" : "-",
   322 							(state.leds & 4) ? "G" : "-",
   323 							(state.leds & 2) ? "Y" : "-",
   324 							(state.leds & 1) ? "R" : "-");
   325 				}
   326 				handled = true;
   327 				break;
   328 			case 0x0B0000:				// TM/DIALWR
   329 				break;
   330 			case 0x0C0000:				// Clear Status Register
   331 				state.genstat = 0xFFFF;
   332 				state.bsr0 = 0xFFFF;
   333 				state.bsr1 = 0xFFFF;
   334 				handled = true;
   335 				break;
   336 			case 0x0D0000:				// DMA Address Register
   337 				if (address & 0x004000) {
   338 					// A14 high -- set most significant bits
   339 					state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
   340 				} else {
   341 					// A14 low -- set least significant bits
   342 					state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
   343 				}
   344 				handled = true;
   345 				break;
   346 			case 0x0E0000:				// Disk Control Register
   347 				ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
   348 				// B7 = FDD controller reset
   349 				if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
   350 				// B6 = drive 0 select -- TODO
   351 				// B5 = motor enable -- TODO
   352 				// B4 = HDD controller reset -- TODO
   353 				// B3 = HDD0 select -- TODO
   354 				// B2,1,0 = HDD0 head select
   355 				handled = true;
   356 				break;
   357 			case 0x0F0000:				// Line Printer Data Register
   358 				break;
   359 		}
   360 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   361 		// I/O register space, zone B
   362 		switch (address & 0xF00000) {
   363 			case 0xC00000:				// Expansion slots
   364 			case 0xD00000:
   365 				switch (address & 0xFC0000) {
   366 					case 0xC00000:		// Expansion slot 0
   367 					case 0xC40000:		// Expansion slot 1
   368 					case 0xC80000:		// Expansion slot 2
   369 					case 0xCC0000:		// Expansion slot 3
   370 					case 0xD00000:		// Expansion slot 4
   371 					case 0xD40000:		// Expansion slot 5
   372 					case 0xD80000:		// Expansion slot 6
   373 					case 0xDC0000:		// Expansion slot 7
   374 						fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
   375 						handled = true;
   376 						break;
   377 				}
   378 				break;
   379 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   380 			case 0xF00000:
   381 				switch (address & 0x070000) {
   382 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   383 						break;
   384 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   385 						ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");
   386 						wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
   387 						handled = true;
   388 						break;
   389 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   390 						break;
   391 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   392 						break;
   393 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   394 						switch (address & 0x077000) {
   395 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   396 								break;
   397 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   398 								ENFORCE_SIZE_W(bits, address, 16, "PIE");
   399 								state.pie = ((data & 0x8000) == 0x8000);
   400 								handled = true;
   401 								break;
   402 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   403 								break;
   404 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   405 								ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
   406 								state.romlmap = ((data & 0x8000) == 0x8000);
   407 								handled = true;
   408 								break;
   409 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   410 								ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
   411 								break;
   412 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   413 								ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
   414 								break;
   415 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   416 								ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
   417 								break;
   418 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   419 								ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
   420 								break;
   421 						}
   422 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   423 						break;
   424 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   425 						switch (address & 0x07F000) {
   426 							default:
   427 								break;
   428 						}
   429 						break;
   430 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   431 						// TODO: figure out which sizes are valid (probably just 8 and 16)
   432 						// ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER");
   433 						if (bits == 8) {
   434 							printf("KBD WR %02X => %02X\n", (address >> 1) & 3, data);
   435 							keyboard_write(&state.kbd, (address >> 1) & 3, data);
   436 							handled = true;
   437 						} else if (bits == 16) {
   438 							printf("KBD WR %02X => %04X\n", (address >> 1) & 3, data);
   439 							keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8);
   440 							handled = true;
   441 						}
   442 						break;
   443 				}
   444 		}
   445 	}
   447 	LOG_NOT_HANDLED_W(bits);
   448 }/*}}}*/
   450 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
   451 {
   452 	bool handled = false;
   453 	uint32_t data = 0xFFFFFFFF;
   455 	if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   456 		// I/O register space, zone A
   457 		switch (address & 0x0F0000) {
   458 			case 0x010000:				// General Status Register
   459 				ENFORCE_SIZE_R(bits, address, 16, "GENSTAT");
   460 				return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
   461 				break;
   462 			case 0x030000:				// Bus Status Register 0
   463 				ENFORCE_SIZE_R(bits, address, 16, "BSR0");
   464 				return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
   465 				break;
   466 			case 0x040000:				// Bus Status Register 1
   467 				ENFORCE_SIZE_R(bits, address, 16, "BSR1");
   468 				return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
   469 				break;
   470 			case 0x050000:				// Phone status
   471 				ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
   472 				break;
   473 			case 0x060000:				// DMA Count
   474 				// TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
   475 				// Bit 14 is always unused, so leave it set
   476 				ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
   477 				return (state.dma_count & 0x3fff) | 0xC000;
   478 				break;
   479 			case 0x070000:				// Line Printer Status Register
   480 				data = 0x00120012;	// no parity error, no line printer error, no irqs from FDD or HDD
   481 				data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0;
   482 				return data;
   483 				break;
   484 			case 0x080000:				// Real Time Clock
   485 				printf("READ NOTIMP: Realtime Clock\n");
   486 				break;
   487 			case 0x090000:				// Phone registers
   488 				switch (address & 0x0FF000) {
   489 					case 0x090000:		// Handset relay
   490 					case 0x098000:
   491 						break;
   492 					case 0x091000:		// Line select 2
   493 					case 0x099000:
   494 						break;
   495 					case 0x092000:		// Hook relay 1
   496 					case 0x09A000:
   497 						break;
   498 					case 0x093000:		// Hook relay 2
   499 					case 0x09B000:
   500 						break;
   501 					case 0x094000:		// Line 1 hold
   502 					case 0x09C000:
   503 						break;
   504 					case 0x095000:		// Line 2 hold
   505 					case 0x09D000:
   506 						break;
   507 					case 0x096000:		// Line 1 A-lead
   508 					case 0x09E000:
   509 						break;
   510 					case 0x097000:		// Line 2 A-lead
   511 					case 0x09F000:
   512 						break;
   513 				}
   514 				break;
   515 			case 0x0A0000:				// Miscellaneous Control Register -- write only!
   516 				handled = true;
   517 				break;
   518 			case 0x0B0000:				// TM/DIALWR
   519 				break;
   520 			case 0x0C0000:				// Clear Status Register -- write only!
   521 				handled = true;
   522 				break;
   523 			case 0x0D0000:				// DMA Address Register
   524 				break;
   525 			case 0x0E0000:				// Disk Control Register
   526 				break;
   527 			case 0x0F0000:				// Line Printer Data Register
   528 				break;
   529 		}
   530 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   531 		// I/O register space, zone B
   532 		switch (address & 0xF00000) {
   533 			case 0xC00000:				// Expansion slots
   534 			case 0xD00000:
   535 				switch (address & 0xFC0000) {
   536 					case 0xC00000:		// Expansion slot 0
   537 					case 0xC40000:		// Expansion slot 1
   538 					case 0xC80000:		// Expansion slot 2
   539 					case 0xCC0000:		// Expansion slot 3
   540 					case 0xD00000:		// Expansion slot 4
   541 					case 0xD40000:		// Expansion slot 5
   542 					case 0xD80000:		// Expansion slot 6
   543 					case 0xDC0000:		// Expansion slot 7
   544 						fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
   545 						handled = true;
   546 						break;
   547 				}
   548 				break;
   549 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   550 			case 0xF00000:
   551 				switch (address & 0x070000) {
   552 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   553 						break;
   554 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   555 						ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");
   556 						return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
   557 						break;
   558 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   559 						break;
   560 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   561 						break;
   562 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   563 						switch (address & 0x077000) {
   564 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   565 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   566 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   567 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   568 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   569 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   570 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   571 								// All write-only registers... TODO: bus error?
   572 								handled = true;
   573 								break;
   574 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
   575 								break;
   576 						}
   577 						break;
   578 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   579 						break;
   580 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   581 						switch (address & 0x07F000) {
   582 							default:
   583 								break;
   584 						}
   585 						break;
   586 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   587 						// TODO: figure out which sizes are valid (probably just 8 and 16)
   588 						//ENFORCE_SIZE_R(bits, address, 16, "KEYBOARD CONTROLLER");
   589 						{
   590 							if (bits == 8) {
   591 								return keyboard_read(&state.kbd, (address >> 1) & 3);
   592 							} else {
   593 								return keyboard_read(&state.kbd, (address >> 1) & 3) << 8;
   594 							}
   595 							return data;
   596 						}
   597 						break;
   598 				}
   599 		}
   600 	}
   602 	LOG_NOT_HANDLED_R(bits);
   604 	return data;
   605 }/*}}}*/
   608 /********************************************************
   609  * m68k memory read/write support functions for Musashi
   610  ********************************************************/
   612 /**
   613  * @brief Read M68K memory, 32-bit
   614  */
   615 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
   616 {
   617 	uint32_t data = 0xFFFFFFFF;
   619 	// If ROMLMAP is set, force system to access ROM
   620 	if (!state.romlmap)
   621 		address |= 0x800000;
   623 	// Check access permissions
   624 	ACCESS_CHECK_RD(address, 32);
   626 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   627 		// ROM access
   628 		return RD32(state.rom, address, ROM_SIZE - 1);
   629 	} else if (address <= 0x3fffff) {
   630 		// RAM access
   631 		uint32_t newAddr = mapAddr(address, false);
   632 		if (newAddr <= 0x1fffff) {
   633 			return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
   634 		} else {
   635 			if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
   636 				return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   637 			else
   638 				return 0xffffffff;
   639 		}
   640 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   641 		// I/O register space, zone A
   642 		switch (address & 0x0F0000) {
   643 			case 0x000000:				// Map RAM access
   644 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
   645 				return RD32(state.map, address, 0x7FF);
   646 				break;
   647 			case 0x020000:				// Video RAM
   648 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
   649 				return RD32(state.vram, address, 0x7FFF);
   650 				break;
   651 			default:
   652 				return IoRead(address, 32);
   653 		}
   654 	} else {
   655 		return IoRead(address, 32);
   656 	}
   658 	return data;
   659 }/*}}}*/
   661 /**
   662  * @brief Read M68K memory, 16-bit
   663  */
   664 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
   665 {
   666 	uint16_t data = 0xFFFF;
   668 	// If ROMLMAP is set, force system to access ROM
   669 	if (!state.romlmap)
   670 		address |= 0x800000;
   672 	// Check access permissions
   673 	ACCESS_CHECK_RD(address, 16);
   675 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   676 		// ROM access
   677 		data = RD16(state.rom, address, ROM_SIZE - 1);
   678 	} else if (address <= 0x3fffff) {
   679 		// RAM access
   680 		uint32_t newAddr = mapAddr(address, false);
   681 		if (newAddr <= 0x1fffff) {
   682 			return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
   683 		} else {
   684 			if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
   685 				return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   686 			else
   687 				return 0xffff;
   688 		}
   689 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   690 		// I/O register space, zone A
   691 		switch (address & 0x0F0000) {
   692 			case 0x000000:				// Map RAM access
   693 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
   694 				data = RD16(state.map, address, 0x7FF);
   695 				break;
   696 			case 0x020000:				// Video RAM
   697 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
   698 				data = RD16(state.vram, address, 0x7FFF);
   699 				break;
   700 			default:
   701 				data = IoRead(address, 16);
   702 		}
   703 	} else {
   704 		data = IoRead(address, 16);
   705 	}
   707 	return data;
   708 }/*}}}*/
   710 /**
   711  * @brief Read M68K memory, 8-bit
   712  */
   713 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
   714 {
   715 	uint8_t data = 0xFF;
   717 	// If ROMLMAP is set, force system to access ROM
   718 	if (!state.romlmap)
   719 		address |= 0x800000;
   721 	// Check access permissions
   722 	ACCESS_CHECK_RD(address, 8);
   724 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   725 		// ROM access
   726 		data = RD8(state.rom, address, ROM_SIZE - 1);
   727 	} else if (address <= 0x3fffff) {
   728 		// RAM access
   729 		uint32_t newAddr = mapAddr(address, false);
   730 		if (newAddr <= 0x1fffff) {
   731 			return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
   732 		} else {
   733 			if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
   734 				return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
   735 			else
   736 				return 0xff;
   737 		}
   738 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   739 		// I/O register space, zone A
   740 		switch (address & 0x0F0000) {
   741 			case 0x000000:				// Map RAM access
   742 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
   743 				data = RD8(state.map, address, 0x7FF);
   744 				break;
   745 			case 0x020000:				// Video RAM
   746 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
   747 				data = RD8(state.vram, address, 0x7FFF);
   748 				break;
   749 			default:
   750 				data = IoRead(address, 8);
   751 		}
   752 	} else {
   753 		data = IoRead(address, 8);
   754 	}
   756 	return data;
   757 }/*}}}*/
   759 /**
   760  * @brief Write M68K memory, 32-bit
   761  */
   762 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
   763 {
   764 	// If ROMLMAP is set, force system to access ROM
   765 	if (!state.romlmap)
   766 		address |= 0x800000;
   768 	// Check access permissions
   769 	ACCESS_CHECK_WR(address, 32);
   771 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   772 		// ROM access
   773 	} else if (address <= 0x3FFFFF) {
   774 		// RAM access
   775 		uint32_t newAddr = mapAddr(address, true);
   776 		if (newAddr <= 0x1fffff)
   777 			WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
   778 		else
   779 			WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   780 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   781 		// I/O register space, zone A
   782 		switch (address & 0x0F0000) {
   783 			case 0x000000:				// Map RAM access
   784 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
   785 				WR32(state.map, address, 0x7FF, value);
   786 				break;
   787 			case 0x020000:				// Video RAM
   788 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
   789 				WR32(state.vram, address, 0x7FFF, value);
   790 				break;
   791 			default:
   792 				IoWrite(address, value, 32);
   793 		}
   794 	} else {
   795 		IoWrite(address, value, 32);
   796 	}
   797 }/*}}}*/
   799 /**
   800  * @brief Write M68K memory, 16-bit
   801  */
   802 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
   803 {
   804 	// If ROMLMAP is set, force system to access ROM
   805 	if (!state.romlmap)
   806 		address |= 0x800000;
   808 	// Check access permissions
   809 	ACCESS_CHECK_WR(address, 16);
   811 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   812 		// ROM access
   813 	} else if (address <= 0x3FFFFF) {
   814 		// RAM access
   815 		uint32_t newAddr = mapAddr(address, true);
   816 		if (newAddr <= 0x1fffff)
   817 			WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
   818 		else
   819 			WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   820 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   821 		// I/O register space, zone A
   822 		switch (address & 0x0F0000) {
   823 			case 0x000000:				// Map RAM access
   824 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   825 				WR16(state.map, address, 0x7FF, value);
   826 				break;
   827 			case 0x020000:				// Video RAM
   828 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   829 				WR16(state.vram, address, 0x7FFF, value);
   830 				break;
   831 			default:
   832 				IoWrite(address, value, 16);
   833 		}
   834 	} else {
   835 		IoWrite(address, value, 16);
   836 	}
   837 }/*}}}*/
   839 /**
   840  * @brief Write M68K memory, 8-bit
   841  */
   842 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
   843 {
   844 	// If ROMLMAP is set, force system to access ROM
   845 	if (!state.romlmap)
   846 		address |= 0x800000;
   848 	// Check access permissions
   849 	ACCESS_CHECK_WR(address, 8);
   851 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   852 		// ROM access (read only!)
   853 	} else if (address <= 0x3FFFFF) {
   854 		// RAM access
   855 		uint32_t newAddr = mapAddr(address, true);
   856 		if (newAddr <= 0x1fffff)
   857 			WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
   858 		else
   859 			WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
   860 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   861 		// I/O register space, zone A
   862 		switch (address & 0x0F0000) {
   863 			case 0x000000:				// Map RAM access
   864 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   865 				WR8(state.map, address, 0x7FF, value);
   866 				break;
   867 			case 0x020000:				// Video RAM
   868 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   869 				WR8(state.vram, address, 0x7FFF, value);
   870 				break;
   871 			default:
   872 				IoWrite(address, value, 8);
   873 		}
   874 	} else {
   875 		IoWrite(address, value, 8);
   876 	}
   877 }/*}}}*/
   880 // for the disassembler
   881 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
   882 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
   883 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }