src/memory.c

Fri, 03 Dec 2010 00:12:53 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Fri, 03 Dec 2010 00:12:53 +0000
changeset 44
f928be115194
parent 43
4d59e4ceef52
child 46
7d14fab5e4aa
permissions
-rw-r--r--

fix state/status transposition, add GENCON.PIE handling

     1 #include <stdio.h>
     2 #include <stdlib.h>
     3 #include <stdint.h>
     4 #include <stdbool.h>
     5 #include "musashi/m68k.h"
     6 #include "state.h"
     7 #include "memory.h"
     9 /******************
    10  * Memory mapping
    11  ******************/
    13 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
    15 uint32_t mapAddr(uint32_t addr, bool writing)
    16 {
    17 	if (addr < 0x400000) {
    18 		// RAM access. Check against the Map RAM
    19 		// Start by getting the original page address
    20 		uint16_t page = (addr >> 12) & 0x3FF;
    22 		// Look it up in the map RAM and get the physical page address
    23 		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
    25 		// Update the Page Status bits
    26 		uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
    27 		if (pagebits != 0) {
    28 			if (writing)
    29 				state.map[page*2] |= 0x60;		// Page written to (dirty)
    30 			else
    31 				state.map[page*2] |= 0x40;		// Page accessed but not written
    32 		}
    34 		// Return the address with the new physical page spliced in
    35 		return (new_page_addr << 12) + (addr & 0xFFF);
    36 	} else {
    37 		// I/O, VRAM or MapRAM space; no mapping is performed or required
    38 		// TODO: assert here?
    39 		return addr;
    40 	}
    41 }
    43 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)
    44 {
    45 	// Are we in Supervisor mode?
    46 	if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
    47 		// Yes. We can do anything we like.
    48 		return MEM_ALLOWED;
    50 	// If we're here, then we must be in User mode.
    51 	// Check that the user didn't access memory outside of the RAM area
    52 	if (addr >= 0x400000)
    53 		return MEM_UIE;
    55 	// This leaves us with Page Fault checking. Get the page bits for this page.
    56 	uint16_t page = (addr >> 12) & 0x3FF;
    57 	uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
    59 	// Check page is present
    60 	if ((pagebits & 0x03) == 0)
    61 		return MEM_PAGEFAULT;
    63 	// User attempt to access the kernel
    64 	// A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
    65 	if (((addr >> 19) & 0x0F) == 0)
    66 		return MEM_KERNEL;
    68 	// Check page is write enabled
    69 	if ((pagebits & 0x04) == 0)
    70 		return MEM_PAGE_NO_WE;
    72 	// Page access allowed.
    73 	return MEM_ALLOWED;
    74 }
    76 #undef MAPRAM
    79 /********************************************************
    80  * m68k memory read/write support functions for Musashi
    81  ********************************************************/
    83 /**
    84  * @brief	Check memory access permissions for a write operation.
    85  * @note	This used to be a single macro (merged with ACCESS_CHECK_RD), but
    86  * 			gcc throws warnings when you have a return-with-value in a void
    87  * 			function, even if the return-with-value is completely unreachable.
    88  * 			Similarly it doesn't like it if you have a return without a value
    89  * 			in a non-void function, even if it's impossible to ever reach the
    90  * 			return-with-no-value. UGH!
    91  */
    92 #define ACCESS_CHECK_WR(address, bits) do {							\
    93 		bool fault = false;											\
    94 		/* MEM_STATUS st; */										\
    95 		switch (checkMemoryAccess(address, true)) {					\
    96 			case MEM_ALLOWED:										\
    97 				/* Access allowed */								\
    98 				break;												\
    99 			case MEM_PAGEFAULT:										\
   100 				/* Page fault */									\
   101 				state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0);	\
   102 				fault = true;										\
   103 				break;												\
   104 			case MEM_UIE:											\
   105 				/* User access to memory above 4MB */				\
   106 				state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0);	\
   107 				fault = true;										\
   108 				break;												\
   109 			case MEM_KERNEL:										\
   110 			case MEM_PAGE_NO_WE:									\
   111 				/* kernel access or page not write enabled */		\
   112 				/* TODO: which regs need setting? */				\
   113 				fault = true;										\
   114 				break;												\
   115 		}															\
   116 																	\
   117 		if (fault) {												\
   118 			if (bits >= 16)											\
   119 				state.bsr0 = 0x7F00;								\
   120 			else													\
   121 				state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00;		\
   122 			state.bsr0 |= (address >> 16);							\
   123 			state.bsr1 = address & 0xffff;							\
   124 			printf("ERR: BusError WR\n");							\
   125 			m68k_pulse_bus_error();									\
   126 			return;													\
   127 		}															\
   128 	} while (false)
   130 /**
   131  * @brief Check memory access permissions for a read operation.
   132  * @note	This used to be a single macro (merged with ACCESS_CHECK_WR), but
   133  * 			gcc throws warnings when you have a return-with-value in a void
   134  * 			function, even if the return-with-value is completely unreachable.
   135  * 			Similarly it doesn't like it if you have a return without a value
   136  * 			in a non-void function, even if it's impossible to ever reach the
   137  * 			return-with-no-value. UGH!
   138  */
   139 #define ACCESS_CHECK_RD(address, bits) do {							\
   140 		bool fault = false;											\
   141 		/* MEM_STATUS st; */										\
   142 		switch (checkMemoryAccess(address, false)) {				\
   143 			case MEM_ALLOWED:										\
   144 				/* Access allowed */								\
   145 				break;												\
   146 			case MEM_PAGEFAULT:										\
   147 				/* Page fault */									\
   148 				state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0);	\
   149 				fault = true;										\
   150 				break;												\
   151 			case MEM_UIE:											\
   152 				/* User access to memory above 4MB */				\
   153 				state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0);	\
   154 				fault = true;										\
   155 				break;												\
   156 			case MEM_KERNEL:										\
   157 			case MEM_PAGE_NO_WE:									\
   158 				/* kernel access or page not write enabled */		\
   159 				/* TODO: which regs need setting? */				\
   160 				fault = true;										\
   161 				break;												\
   162 		}															\
   163 																	\
   164 		if (fault) {												\
   165 			if (bits >= 16)											\
   166 				state.bsr0 = 0x7F00;								\
   167 			else													\
   168 				state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00;		\
   169 			state.bsr0 |= (address >> 16);							\
   170 			state.bsr1 = address & 0xffff;							\
   171 			printf("ERR: BusError RD\n");							\
   172 			m68k_pulse_bus_error();									\
   173 			return 0xFFFFFFFF;										\
   174 		}															\
   175 	} while (false)
   177 // Logging macros
   178 #define LOG_NOT_HANDLED_R(bits)																	\
   179 	do {																						\
   180 		if (!handled)																			\
   181 			printf("unhandled read%02d, addr=0x%08X\n", bits, address);							\
   182 	} while (0);
   184 #define LOG_NOT_HANDLED_W(bits)																	\
   185 	do {																						\
   186 		if (!handled)																			\
   187 			printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, value);	\
   188 	} while (0);
   190 /**
   191  * @brief Read M68K memory, 32-bit
   192  */
   193 uint32_t m68k_read_memory_32(uint32_t address)
   194 {
   195 	uint32_t data = 0xFFFFFFFF;
   196 	bool handled = false;
   198 	// If ROMLMAP is set, force system to access ROM
   199 	if (!state.romlmap)
   200 		address |= 0x800000;
   202 	// Check access permissions
   203 	ACCESS_CHECK_RD(address, 32);
   205 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   206 		// ROM access
   207 		data = RD32(state.rom, address, ROM_SIZE - 1);
   208 		handled = true;
   209 	} else if (address <= (state.ram_size - 1)) {
   210 		// RAM access
   211 		data = RD32(state.ram, mapAddr(address, false), state.ram_size - 1);
   212 		handled = true;
   213 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   214 		// I/O register space, zone A
   215 		switch (address & 0x0F0000) {
   216 			case 0x000000:				// Map RAM access
   217 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
   218 				data = RD32(state.map, address, 0x7FF);
   219 				handled = true;
   220 				break;
   221 			case 0x010000:				// General Status Register
   222 				data = ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
   223 				handled = true;
   224 				break;
   225 			case 0x020000:				// Video RAM
   226 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
   227 				data = RD32(state.vram, address, 0x7FFF);
   228 				handled = true;
   229 				break;
   230 			case 0x030000:				// Bus Status Register 0
   231 				data = ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
   232 				handled = true;
   233 				break;
   234 			case 0x040000:				// Bus Status Register 1
   235 				data = ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
   236 				handled = true;
   237 				break;
   238 			case 0x050000:				// Phone status
   239 				break;
   240 			case 0x060000:				// DMA Count
   241 				break;
   242 			case 0x070000:				// Line Printer Status Register
   243 				break;
   244 			case 0x080000:				// Real Time Clock
   245 				break;
   246 			case 0x090000:				// Phone registers
   247 				switch (address & 0x0FF000) {
   248 					case 0x090000:		// Handset relay
   249 					case 0x098000:
   250 						break;
   251 					case 0x091000:		// Line select 2
   252 					case 0x099000:
   253 						break;
   254 					case 0x092000:		// Hook relay 1
   255 					case 0x09A000:
   256 						break;
   257 					case 0x093000:		// Hook relay 2
   258 					case 0x09B000:
   259 						break;
   260 					case 0x094000:		// Line 1 hold
   261 					case 0x09C000:
   262 						break;
   263 					case 0x095000:		// Line 2 hold
   264 					case 0x09D000:
   265 						break;
   266 					case 0x096000:		// Line 1 A-lead
   267 					case 0x09E000:
   268 						break;
   269 					case 0x097000:		// Line 2 A-lead
   270 					case 0x09F000:
   271 						break;
   272 				}
   273 				break;
   274 			case 0x0A0000:				// Miscellaneous Control Register
   275 				break;
   276 			case 0x0B0000:				// TM/DIALWR
   277 				break;
   278 			case 0x0C0000:				// Clear Status Register
   279 				handled = true;
   280 				break;
   281 			case 0x0D0000:				// DMA Address Register
   282 				break;
   283 			case 0x0E0000:				// Disk Control Register
   284 				break;
   285 			case 0x0F0000:				// Line Printer Data Register
   286 				break;
   287 		}
   288 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   289 		// I/O register space, zone B
   290 		switch (address & 0xF00000) {
   291 			case 0xC00000:				// Expansion slots
   292 			case 0xD00000:
   293 				switch (address & 0xFC0000) {
   294 					case 0xC00000:		// Expansion slot 0
   295 					case 0xC40000:		// Expansion slot 1
   296 					case 0xC80000:		// Expansion slot 2
   297 					case 0xCC0000:		// Expansion slot 3
   298 					case 0xD00000:		// Expansion slot 4
   299 					case 0xD40000:		// Expansion slot 5
   300 					case 0xD80000:		// Expansion slot 6
   301 					case 0xDC0000:		// Expansion slot 7
   302 						fprintf(stderr, "NOTE: RD32 from expansion card space, addr=0x%08X\n", address);
   303 						break;
   304 				}
   305 				break;
   306 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   307 			case 0xF00000:
   308 				switch (address & 0x070000) {
   309 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   310 						break;
   311 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   312 						break;
   313 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   314 						break;
   315 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   316 						break;
   317 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   318 						switch (address & 0x077000) {
   319 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   320 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   321 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   322 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   323 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   324 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   325 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   326 								// All write-only registers... TODO: bus error?
   327 								handled = true;
   328 								break;
   329 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
   330 								break;
   331 						}
   332 						break;
   333 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   334 						break;
   335 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   336 						switch (address & 0x07F000) {
   337 							default:
   338 								break;
   339 						}
   340 						break;
   341 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   342 						break;
   343 				}
   344 		}
   345 	}
   347 	LOG_NOT_HANDLED_R(32);
   348 	return data;
   349 }
   351 /**
   352  * @brief Read M68K memory, 16-bit
   353  */
   354 uint32_t m68k_read_memory_16(uint32_t address)
   355 {
   356 	uint16_t data = 0xFFFF;
   357 	bool handled = false;
   359 	// If ROMLMAP is set, force system to access ROM
   360 	if (!state.romlmap)
   361 		address |= 0x800000;
   363 	// Check access permissions
   364 	ACCESS_CHECK_RD(address, 16);
   366 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   367 		// ROM access
   368 		data = RD16(state.rom, address, ROM_SIZE - 1);
   369 		handled = true;
   370 	} else if (address <= (state.ram_size - 1)) {
   371 		// RAM access
   372 		data = RD16(state.ram, mapAddr(address, false), state.ram_size - 1);
   373 		handled = true;
   374 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   375 		// I/O register space, zone A
   376 		switch (address & 0x0F0000) {
   377 			case 0x000000:				// Map RAM access
   378 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
   379 				data = RD16(state.map, address, 0x7FF);
   380 				handled = true;
   381 				break;
   382 			case 0x010000:				// General Status Register
   383 				data = state.genstat;
   384 				handled = true;
   385 				break;
   386 			case 0x020000:				// Video RAM
   387 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
   388 				data = RD16(state.vram, address, 0x7FFF);
   389 				handled = true;
   390 				break;
   391 			case 0x030000:				// Bus Status Register 0
   392 				data = state.bsr0;
   393 				handled = true;
   394 				break;
   395 			case 0x040000:				// Bus Status Register 1
   396 				data = state.bsr1;
   397 				handled = true;
   398 				break;
   399 			case 0x050000:				// Phone status
   400 				break;
   401 			case 0x060000:				// DMA Count
   402 				break;
   403 			case 0x070000:				// Line Printer Status Register
   404 				break;
   405 			case 0x080000:				// Real Time Clock
   406 				break;
   407 			case 0x090000:				// Phone registers
   408 				switch (address & 0x0FF000) {
   409 					case 0x090000:		// Handset relay
   410 					case 0x098000:
   411 						break;
   412 					case 0x091000:		// Line select 2
   413 					case 0x099000:
   414 						break;
   415 					case 0x092000:		// Hook relay 1
   416 					case 0x09A000:
   417 						break;
   418 					case 0x093000:		// Hook relay 2
   419 					case 0x09B000:
   420 						break;
   421 					case 0x094000:		// Line 1 hold
   422 					case 0x09C000:
   423 						break;
   424 					case 0x095000:		// Line 2 hold
   425 					case 0x09D000:
   426 						break;
   427 					case 0x096000:		// Line 1 A-lead
   428 					case 0x09E000:
   429 						break;
   430 					case 0x097000:		// Line 2 A-lead
   431 					case 0x09F000:
   432 						break;
   433 				}
   434 				break;
   435 			case 0x0A0000:				// Miscellaneous Control Register
   436 				break;
   437 			case 0x0B0000:				// TM/DIALWR
   438 				break;
   439 			case 0x0C0000:				// Clear Status Register
   440 				handled = true;
   441 				break;
   442 			case 0x0D0000:				// DMA Address Register
   443 				break;
   444 			case 0x0E0000:				// Disk Control Register
   445 				break;
   446 			case 0x0F0000:				// Line Printer Data Register
   447 				break;
   448 		}
   449 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   450 		// I/O register space, zone B
   451 		switch (address & 0xF00000) {
   452 			case 0xC00000:				// Expansion slots
   453 			case 0xD00000:
   454 				switch (address & 0xFC0000) {
   455 					case 0xC00000:		// Expansion slot 0
   456 					case 0xC40000:		// Expansion slot 1
   457 					case 0xC80000:		// Expansion slot 2
   458 					case 0xCC0000:		// Expansion slot 3
   459 					case 0xD00000:		// Expansion slot 4
   460 					case 0xD40000:		// Expansion slot 5
   461 					case 0xD80000:		// Expansion slot 6
   462 					case 0xDC0000:		// Expansion slot 7
   463 						fprintf(stderr, "NOTE: RD16 from expansion card space, addr=0x%08X\n", address);
   464 						break;
   465 				}
   466 				break;
   467 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   468 			case 0xF00000:
   469 				switch (address & 0x070000) {
   470 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   471 						break;
   472 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   473 						break;
   474 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   475 						break;
   476 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   477 						break;
   478 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   479 						switch (address & 0x077000) {
   480 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   481 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   482 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   483 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   484 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   485 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   486 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   487 								// All write-only registers... TODO: bus error?
   488 								handled = true;
   489 								break;
   490 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   491 								break;
   492 						}
   493 						break;
   494 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   495 						break;
   496 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   497 						switch (address & 0x07F000) {
   498 							default:
   499 								break;
   500 						}
   501 						break;
   502 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   503 						break;
   504 				}
   505 		}
   506 	}
   508 	LOG_NOT_HANDLED_R(32);
   509 	return data;
   510 }
   512 /**
   513  * @brief Read M68K memory, 8-bit
   514  */
   515 uint32_t m68k_read_memory_8(uint32_t address)
   516 {
   517 	uint8_t data = 0xFF;
   518 	bool handled = false;
   520 	// If ROMLMAP is set, force system to access ROM
   521 	if (!state.romlmap)
   522 		address |= 0x800000;
   524 	// Check access permissions
   525 	ACCESS_CHECK_RD(address, 8);
   527 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   528 		// ROM access
   529 		data = RD8(state.rom, address, ROM_SIZE - 1);
   530 		handled = true;
   531 	} else if (address <= (state.ram_size - 1)) {
   532 		// RAM access
   533 		data = RD8(state.ram, mapAddr(address, false), state.ram_size - 1);
   534 		handled = true;
   535 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   536 		// I/O register space, zone A
   537 		switch (address & 0x0F0000) {
   538 			case 0x000000:				// Map RAM access
   539 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
   540 				data = RD8(state.map, address, 0x7FF);
   541 				handled = true;
   542 				break;
   543 			case 0x010000:				// General Status Register
   544 				if ((address & 1) == 0)
   545 					data = (state.genstat >> 8) & 0xff;
   546 				else
   547 					data = (state.genstat)      & 0xff;
   548 				handled = true;
   549 				break;
   550 			case 0x020000:				// Video RAM
   551 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
   552 				data = RD8(state.vram, address, 0x7FFF);
   553 				handled = true;
   554 				break;
   555 			case 0x030000:				// Bus Status Register 0
   556 				if ((address & 1) == 0)
   557 					data = (state.bsr0 >> 8) & 0xff;
   558 				else
   559 					data = (state.bsr0)      & 0xff;
   560 				handled = true;
   561 				break;
   562 			case 0x040000:				// Bus Status Register 1
   563 				if ((address & 1) == 0)
   564 					data = (state.bsr1 >> 8) & 0xff;
   565 				else
   566 					data = (state.bsr1)      & 0xff;
   567 				handled = true;
   568 				break;
   569 			case 0x050000:				// Phone status
   570 				break;
   571 			case 0x060000:				// DMA Count
   572 				break;
   573 			case 0x070000:				// Line Printer Status Register
   574 				break;
   575 			case 0x080000:				// Real Time Clock
   576 				break;
   577 			case 0x090000:				// Phone registers
   578 				switch (address & 0x0FF000) {
   579 					case 0x090000:		// Handset relay
   580 					case 0x098000:
   581 						break;
   582 					case 0x091000:		// Line select 2
   583 					case 0x099000:
   584 						break;
   585 					case 0x092000:		// Hook relay 1
   586 					case 0x09A000:
   587 						break;
   588 					case 0x093000:		// Hook relay 2
   589 					case 0x09B000:
   590 						break;
   591 					case 0x094000:		// Line 1 hold
   592 					case 0x09C000:
   593 						break;
   594 					case 0x095000:		// Line 2 hold
   595 					case 0x09D000:
   596 						break;
   597 					case 0x096000:		// Line 1 A-lead
   598 					case 0x09E000:
   599 						break;
   600 					case 0x097000:		// Line 2 A-lead
   601 					case 0x09F000:
   602 						break;
   603 				}
   604 				break;
   605 			case 0x0A0000:				// Miscellaneous Control Register
   606 				break;
   607 			case 0x0B0000:				// TM/DIALWR
   608 				break;
   609 			case 0x0C0000:				// Clear Status Register
   610 				handled = true;
   611 				break;
   612 			case 0x0D0000:				// DMA Address Register
   613 				break;
   614 			case 0x0E0000:				// Disk Control Register
   615 				break;
   616 			case 0x0F0000:				// Line Printer Data Register
   617 				break;
   618 		}
   619 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   620 		// I/O register space, zone B
   621 		switch (address & 0xF00000) {
   622 			case 0xC00000:				// Expansion slots
   623 			case 0xD00000:
   624 				switch (address & 0xFC0000) {
   625 					case 0xC00000:		// Expansion slot 0
   626 					case 0xC40000:		// Expansion slot 1
   627 					case 0xC80000:		// Expansion slot 2
   628 					case 0xCC0000:		// Expansion slot 3
   629 					case 0xD00000:		// Expansion slot 4
   630 					case 0xD40000:		// Expansion slot 5
   631 					case 0xD80000:		// Expansion slot 6
   632 					case 0xDC0000:		// Expansion slot 7
   633 						fprintf(stderr, "NOTE: RD8 from expansion card space, addr=0x%08X\n", address);
   634 						break;
   635 				}
   636 				break;
   637 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   638 			case 0xF00000:
   639 				switch (address & 0x070000) {
   640 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   641 						break;
   642 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   643 						break;
   644 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   645 						break;
   646 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   647 						break;
   648 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   649 						switch (address & 0x077000) {
   650 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   651 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   652 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   653 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   654 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   655 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   656 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   657 								// All write-only registers... TODO: bus error?
   658 								handled = true;
   659 								break;
   660 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   661 								break;
   662 						}
   663 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   664 						break;
   665 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   666 						switch (address & 0x07F000) {
   667 							default:
   668 								break;
   669 						}
   670 						break;
   671 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   672 						break;
   673 				}
   674 		}
   675 	}
   677 	LOG_NOT_HANDLED_R(8);
   679 	return data;
   680 }
   682 /**
   683  * @brief Write M68K memory, 32-bit
   684  */
   685 void m68k_write_memory_32(uint32_t address, uint32_t value)
   686 {
   687 	bool handled = false;
   689 	// If ROMLMAP is set, force system to access ROM
   690 	if (!state.romlmap)
   691 		address |= 0x800000;
   693 	// Check access permissions
   694 	ACCESS_CHECK_WR(address, 32);
   696 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   697 		// ROM access
   698 		handled = true;
   699 	} else if (address <= (state.ram_size - 1)) {
   700 		// RAM access
   701 		WR32(state.ram, mapAddr(address, false), state.ram_size - 1, value);
   702 		handled = true;
   703 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   704 		// I/O register space, zone A
   705 		switch (address & 0x0F0000) {
   706 			case 0x000000:				// Map RAM access
   707 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
   708 				WR32(state.map, address, 0x7FF, value);
   709 				handled = true;
   710 				break;
   711 			case 0x010000:				// General Status Register
   712 				state.genstat = (value & 0xffff);
   713 				handled = true;
   714 				break;
   715 			case 0x020000:				// Video RAM
   716 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
   717 				WR32(state.vram, address, 0x7FFF, value);
   718 				handled = true;
   719 				break;
   720 			case 0x030000:				// Bus Status Register 0
   721 				break;
   722 			case 0x040000:				// Bus Status Register 1
   723 				break;
   724 			case 0x050000:				// Phone status
   725 				break;
   726 			case 0x060000:				// DMA Count
   727 				break;
   728 			case 0x070000:				// Line Printer Status Register
   729 				break;
   730 			case 0x080000:				// Real Time Clock
   731 				break;
   732 			case 0x090000:				// Phone registers
   733 				switch (address & 0x0FF000) {
   734 					case 0x090000:		// Handset relay
   735 					case 0x098000:
   736 						break;
   737 					case 0x091000:		// Line select 2
   738 					case 0x099000:
   739 						break;
   740 					case 0x092000:		// Hook relay 1
   741 					case 0x09A000:
   742 						break;
   743 					case 0x093000:		// Hook relay 2
   744 					case 0x09B000:
   745 						break;
   746 					case 0x094000:		// Line 1 hold
   747 					case 0x09C000:
   748 						break;
   749 					case 0x095000:		// Line 2 hold
   750 					case 0x09D000:
   751 						break;
   752 					case 0x096000:		// Line 1 A-lead
   753 					case 0x09E000:
   754 						break;
   755 					case 0x097000:		// Line 2 A-lead
   756 					case 0x09F000:
   757 						break;
   758 				}
   759 				break;
   760 			case 0x0A0000:				// Miscellaneous Control Register
   761 				break;
   762 			case 0x0B0000:				// TM/DIALWR
   763 				break;
   764 			case 0x0C0000:				// Clear Status Register
   765 				state.genstat = 0xFFFF;
   766 				state.bsr0 = 0xFFFF;
   767 				state.bsr1 = 0xFFFF;
   768 				handled = true;
   769 				break;
   770 			case 0x0D0000:				// DMA Address Register
   771 				break;
   772 			case 0x0E0000:				// Disk Control Register
   773 				break;
   774 			case 0x0F0000:				// Line Printer Data Register
   775 				break;
   776 		}
   777 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   778 		// I/O register space, zone B
   779 		switch (address & 0xF00000) {
   780 			case 0xC00000:				// Expansion slots
   781 			case 0xD00000:
   782 				switch (address & 0xFC0000) {
   783 					case 0xC00000:		// Expansion slot 0
   784 					case 0xC40000:		// Expansion slot 1
   785 					case 0xC80000:		// Expansion slot 2
   786 					case 0xCC0000:		// Expansion slot 3
   787 					case 0xD00000:		// Expansion slot 4
   788 					case 0xD40000:		// Expansion slot 5
   789 					case 0xD80000:		// Expansion slot 6
   790 					case 0xDC0000:		// Expansion slot 7
   791 						fprintf(stderr, "NOTE: WR32 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
   792 						handled = true;
   793 						break;
   794 				}
   795 				break;
   796 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   797 			case 0xF00000:
   798 				switch (address & 0x070000) {
   799 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   800 						break;
   801 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   802 						break;
   803 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   804 						break;
   805 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   806 						break;
   807 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   808 						switch (address & 0x077000) {
   809 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   810 								break;
   811 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   812 								state.pie = ((value & 0x8000) == 0x8000);
   813 								handled = true;
   814 								break;
   815 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   816 								break;
   817 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   818 								state.romlmap = ((value & 0x8000) == 0x8000);
   819 								handled = true;
   820 								break;
   821 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   822 								break;
   823 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   824 								break;
   825 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   826 								break;
   827 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   828 								break;
   829 						}
   830 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   831 						break;
   832 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   833 						switch (address & 0x07F000) {
   834 							default:
   835 								break;
   836 						}
   837 						break;
   838 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   839 						break;
   840 				}
   841 		}
   842 	}
   844 	LOG_NOT_HANDLED_W(32);
   845 }
   847 /**
   848  * @brief Write M68K memory, 16-bit
   849  */
   850 void m68k_write_memory_16(uint32_t address, uint32_t value)
   851 {
   852 	bool handled = false;
   854 	// If ROMLMAP is set, force system to access ROM
   855 	if (!state.romlmap)
   856 		address |= 0x800000;
   858 	// Check access permissions
   859 	ACCESS_CHECK_WR(address, 16);
   861 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   862 		// ROM access
   863 		handled = true;
   864 	} else if (address <= (state.ram_size - 1)) {
   865 		// RAM access
   866 		WR16(state.ram, mapAddr(address, false), state.ram_size - 1, value);
   867 		handled = true;
   868 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   869 		// I/O register space, zone A
   870 		switch (address & 0x0F0000) {
   871 			case 0x000000:				// Map RAM access
   872 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   873 				WR16(state.map, address, 0x7FF, value);
   874 				handled = true;
   875 				break;
   876 			case 0x010000:				// General Status Register (read only)
   877 				handled = true;
   878 				break;
   879 			case 0x020000:				// Video RAM
   880 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   881 				WR16(state.vram, address, 0x7FFF, value);
   882 				handled = true;
   883 				break;
   884 			case 0x030000:				// Bus Status Register 0 (read only)
   885 				handled = true;
   886 				break;
   887 			case 0x040000:				// Bus Status Register 1 (read only)
   888 				handled = true;
   889 				break;
   890 			case 0x050000:				// Phone status
   891 				break;
   892 			case 0x060000:				// DMA Count
   893 				break;
   894 			case 0x070000:				// Line Printer Status Register
   895 				break;
   896 			case 0x080000:				// Real Time Clock
   897 				break;
   898 			case 0x090000:				// Phone registers
   899 				switch (address & 0x0FF000) {
   900 					case 0x090000:		// Handset relay
   901 					case 0x098000:
   902 						break;
   903 					case 0x091000:		// Line select 2
   904 					case 0x099000:
   905 						break;
   906 					case 0x092000:		// Hook relay 1
   907 					case 0x09A000:
   908 						break;
   909 					case 0x093000:		// Hook relay 2
   910 					case 0x09B000:
   911 						break;
   912 					case 0x094000:		// Line 1 hold
   913 					case 0x09C000:
   914 						break;
   915 					case 0x095000:		// Line 2 hold
   916 					case 0x09D000:
   917 						break;
   918 					case 0x096000:		// Line 1 A-lead
   919 					case 0x09E000:
   920 						break;
   921 					case 0x097000:		// Line 2 A-lead
   922 					case 0x09F000:
   923 						break;
   924 				}
   925 				break;
   926 			case 0x0A0000:				// Miscellaneous Control Register
   927 				break;
   928 			case 0x0B0000:				// TM/DIALWR
   929 				break;
   930 			case 0x0C0000:				// Clear Status Register
   931 				state.genstat = 0xFFFF;
   932 				state.bsr0 = 0xFFFF;
   933 				state.bsr1 = 0xFFFF;
   934 				handled = true;
   935 				break;
   936 			case 0x0D0000:				// DMA Address Register
   937 				break;
   938 			case 0x0E0000:				// Disk Control Register
   939 				break;
   940 			case 0x0F0000:				// Line Printer Data Register
   941 				break;
   942 		}
   943 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   944 		// I/O register space, zone B
   945 		switch (address & 0xF00000) {
   946 			case 0xC00000:				// Expansion slots
   947 			case 0xD00000:
   948 				switch (address & 0xFC0000) {
   949 					case 0xC00000:		// Expansion slot 0
   950 					case 0xC40000:		// Expansion slot 1
   951 					case 0xC80000:		// Expansion slot 2
   952 					case 0xCC0000:		// Expansion slot 3
   953 					case 0xD00000:		// Expansion slot 4
   954 					case 0xD40000:		// Expansion slot 5
   955 					case 0xD80000:		// Expansion slot 6
   956 					case 0xDC0000:		// Expansion slot 7
   957 						fprintf(stderr, "NOTE: WR16 to expansion card space, addr=0x%08X, data=0x%04X\n", address, value);
   958 						break;
   959 				}
   960 				break;
   961 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   962 			case 0xF00000:
   963 				switch (address & 0x070000) {
   964 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   965 						break;
   966 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   967 						break;
   968 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   969 						break;
   970 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   971 						break;
   972 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   973 						switch (address & 0x077000) {
   974 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   975 								break;
   976 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   977 								state.pie = ((value & 0x8000) == 0x8000);
   978 								handled = true;
   979 								break;
   980 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   981 								break;
   982 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   983 								state.romlmap = ((value & 0x8000) == 0x8000);
   984 								handled = true;
   985 								break;
   986 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   987 								break;
   988 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   989 								break;
   990 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   991 								break;
   992 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   993 								break;
   994 						}
   995 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   996 						break;
   997 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   998 						switch (address & 0x07F000) {
   999 							default:
  1000 								break;
  1002 						break;
  1003 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
  1004 						break;
  1009 	LOG_NOT_HANDLED_W(16);
  1012 /**
  1013  * @brief Write M68K memory, 8-bit
  1014  */
  1015 void m68k_write_memory_8(uint32_t address, uint32_t value)
  1017 	bool handled = false;
  1019 	// If ROMLMAP is set, force system to access ROM
  1020 	if (!state.romlmap)
  1021 		address |= 0x800000;
  1023 	// Check access permissions
  1024 	ACCESS_CHECK_WR(address, 8);
  1026 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
  1027 		// ROM access (read only!)
  1028 		handled = true;
  1029 	} else if (address <= (state.ram_size - 1)) {
  1030 		// RAM access
  1031 		WR8(state.ram, mapAddr(address, false), state.ram_size - 1, value);
  1032 		handled = true;
  1033 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
  1034 		// I/O register space, zone A
  1035 		switch (address & 0x0F0000) {
  1036 			case 0x000000:				// Map RAM access
  1037 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=%08X, data=%02X\n", address, value);
  1038 				WR8(state.map, address, 0x7FF, value);
  1039 				handled = true;
  1040 				break;
  1041 			case 0x010000:				// General Status Register
  1042 				handled = true;
  1043 				break;
  1044 			case 0x020000:				// Video RAM
  1045 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=%08X\n, data=0x%02X", address, value);
  1046 				WR8(state.vram, address, 0x7FFF, value);
  1047 				handled = true;
  1048 				break;
  1049 			case 0x030000:				// Bus Status Register 0
  1050 				handled = true;
  1051 				break;
  1052 			case 0x040000:				// Bus Status Register 1
  1053 				handled = true;
  1054 				break;
  1055 			case 0x050000:				// Phone status
  1056 				break;
  1057 			case 0x060000:				// DMA Count
  1058 				break;
  1059 			case 0x070000:				// Line Printer Status Register
  1060 				break;
  1061 			case 0x080000:				// Real Time Clock
  1062 				break;
  1063 			case 0x090000:				// Phone registers
  1064 				switch (address & 0x0FF000) {
  1065 					case 0x090000:		// Handset relay
  1066 					case 0x098000:
  1067 						break;
  1068 					case 0x091000:		// Line select 2
  1069 					case 0x099000:
  1070 						break;
  1071 					case 0x092000:		// Hook relay 1
  1072 					case 0x09A000:
  1073 						break;
  1074 					case 0x093000:		// Hook relay 2
  1075 					case 0x09B000:
  1076 						break;
  1077 					case 0x094000:		// Line 1 hold
  1078 					case 0x09C000:
  1079 						break;
  1080 					case 0x095000:		// Line 2 hold
  1081 					case 0x09D000:
  1082 						break;
  1083 					case 0x096000:		// Line 1 A-lead
  1084 					case 0x09E000:
  1085 						break;
  1086 					case 0x097000:		// Line 2 A-lead
  1087 					case 0x09F000:
  1088 						break;
  1090 				break;
  1091 			case 0x0A0000:				// Miscellaneous Control Register
  1092 				break;
  1093 			case 0x0B0000:				// TM/DIALWR
  1094 				break;
  1095 			case 0x0C0000:				// Clear Status Register
  1096 				state.genstat = 0xFFFF;
  1097 				state.bsr0 = 0xFFFF;
  1098 				state.bsr1 = 0xFFFF;
  1099 				handled = true;
  1100 				break;
  1101 			case 0x0D0000:				// DMA Address Register
  1102 				break;
  1103 			case 0x0E0000:				// Disk Control Register
  1104 				break;
  1105 			case 0x0F0000:				// Line Printer Data Register
  1106 				break;
  1108 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
  1109 		// I/O register space, zone B
  1110 		switch (address & 0xF00000) {
  1111 			case 0xC00000:				// Expansion slots
  1112 			case 0xD00000:
  1113 				switch (address & 0xFC0000) {
  1114 					case 0xC00000:		// Expansion slot 0
  1115 					case 0xC40000:		// Expansion slot 1
  1116 					case 0xC80000:		// Expansion slot 2
  1117 					case 0xCC0000:		// Expansion slot 3
  1118 					case 0xD00000:		// Expansion slot 4
  1119 					case 0xD40000:		// Expansion slot 5
  1120 					case 0xD80000:		// Expansion slot 6
  1121 					case 0xDC0000:		// Expansion slot 7
  1122 						fprintf(stderr, "NOTE: WR8 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
  1123 						break;
  1125 				break;
  1126 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
  1127 			case 0xF00000:
  1128 				switch (address & 0x070000) {
  1129 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
  1130 						break;
  1131 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
  1132 						break;
  1133 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
  1134 						break;
  1135 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
  1136 						break;
  1137 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
  1138 						switch (address & 0x077000) {
  1139 							case 0x040000:		// [ef][4c][08]xxx ==> EE
  1140 								break;
  1141 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
  1142 								if ((address & 1) == 0)
  1143 									state.pie = ((value & 0x80) == 0x80);
  1144 								handled = true;
  1145 								break;
  1146 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
  1147 								break;
  1148 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
  1149 								if ((address & 1) == 0)
  1150 									state.romlmap = ((value & 0x80) == 0x80);
  1151 								handled = true;
  1152 								break;
  1153 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
  1154 								break;
  1155 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
  1156 								break;
  1157 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
  1158 								break;
  1159 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
  1160 								break;
  1162 					case 0x050000:		// [ef][5d]xxxx ==> 8274
  1163 						break;
  1164 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
  1165 						switch (address & 0x07F000) {
  1166 							default:
  1167 								break;
  1169 						break;
  1170 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
  1171 						break;
  1172 					default:
  1173 						fprintf(stderr, "NOTE: WR8 to undefined E/F-block space, addr=0x%08X, data=0x%08X\n", address, value);
  1174 						break;
  1179 	LOG_NOT_HANDLED_W(8);
  1183 // for the disassembler
  1184 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
  1185 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
  1186 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }