src/memory.c

Tue, 14 Dec 2010 02:41:40 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Tue, 14 Dec 2010 02:41:40 +0000
changeset 57
feb84193a43a
parent 56
b3f309d46e97
child 59
d2e3b9e5d082
permissions
-rw-r--r--

add CHS param checking (FDC), fix DMA address setting (DMA_XFER)

* Floppy controller wasn't checking CHS values. Fixed.
* DMA ADDRESS COUNT register was implemented completely wrong -- shifts and ANDmasks were wrong. Fixed.

Boot PROM and Loader now run to the point of booting the kernel!

     1 #include <stdio.h>
     2 #include <stdlib.h>
     3 #include <stdint.h>
     4 #include <stdbool.h>
     5 #include "musashi/m68k.h"
     6 #include "state.h"
     7 #include "memory.h"
     9 /******************
    10  * Memory mapping
    11  ******************/
    13 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
    15 uint32_t mapAddr(uint32_t addr, bool writing)
    16 {
    17 	if (addr < 0x400000) {
    18 		// RAM access. Check against the Map RAM
    19 		// Start by getting the original page address
    20 		uint16_t page = (addr >> 12) & 0x3FF;
    22 		// Look it up in the map RAM and get the physical page address
    23 		uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
    25 		// Update the Page Status bits
    26 		uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
    27 		if (pagebits != 0) {
    28 			if (writing)
    29 				state.map[page*2] |= 0x60;		// Page written to (dirty)
    30 			else
    31 				state.map[page*2] |= 0x40;		// Page accessed but not written
    32 		}
    34 		// Return the address with the new physical page spliced in
    35 		return (new_page_addr << 12) + (addr & 0xFFF);
    36 	} else {
    37 		// I/O, VRAM or MapRAM space; no mapping is performed or required
    38 		// TODO: assert here?
    39 		return addr;
    40 	}
    41 }
    43 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)
    44 {
    45 	// Are we in Supervisor mode?
    46 	if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
    47 		// Yes. We can do anything we like.
    48 		return MEM_ALLOWED;
    50 	// If we're here, then we must be in User mode.
    51 	// Check that the user didn't access memory outside of the RAM area
    52 	if (addr >= 0x400000)
    53 		return MEM_UIE;
    55 	// This leaves us with Page Fault checking. Get the page bits for this page.
    56 	uint16_t page = (addr >> 12) & 0x3FF;
    57 	uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
    59 	// Check page is present
    60 	if ((pagebits & 0x03) == 0)
    61 		return MEM_PAGEFAULT;
    63 	// User attempt to access the kernel
    64 	// A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
    65 	if (((addr >> 19) & 0x0F) == 0)
    66 		return MEM_KERNEL;
    68 	// Check page is write enabled
    69 	if ((pagebits & 0x04) == 0)
    70 		return MEM_PAGE_NO_WE;
    72 	// Page access allowed.
    73 	return MEM_ALLOWED;
    74 }
    76 #undef MAPRAM
    79 /********************************************************
    80  * m68k memory read/write support functions for Musashi
    81  ********************************************************/
    83 /**
    84  * @brief	Check memory access permissions for a write operation.
    85  * @note	This used to be a single macro (merged with ACCESS_CHECK_RD), but
    86  * 			gcc throws warnings when you have a return-with-value in a void
    87  * 			function, even if the return-with-value is completely unreachable.
    88  * 			Similarly it doesn't like it if you have a return without a value
    89  * 			in a non-void function, even if it's impossible to ever reach the
    90  * 			return-with-no-value. UGH!
    91  */
    92 #define ACCESS_CHECK_WR(address, bits) do {							\
    93 		bool fault = false;											\
    94 		/* MEM_STATUS st; */										\
    95 		switch (checkMemoryAccess(address, true)) {					\
    96 			case MEM_ALLOWED:										\
    97 				/* Access allowed */								\
    98 				break;												\
    99 			case MEM_PAGEFAULT:										\
   100 				/* Page fault */									\
   101 				state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0);	\
   102 				fault = true;										\
   103 				break;												\
   104 			case MEM_UIE:											\
   105 				/* User access to memory above 4MB */				\
   106 				state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0);	\
   107 				fault = true;										\
   108 				break;												\
   109 			case MEM_KERNEL:										\
   110 			case MEM_PAGE_NO_WE:									\
   111 				/* kernel access or page not write enabled */		\
   112 				/* TODO: which regs need setting? */				\
   113 				fault = true;										\
   114 				break;												\
   115 		}															\
   116 																	\
   117 		if (fault) {												\
   118 			if (bits >= 16)											\
   119 				state.bsr0 = 0x7F00;								\
   120 			else													\
   121 				state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00;		\
   122 			state.bsr0 |= (address >> 16);							\
   123 			state.bsr1 = address & 0xffff;							\
   124 			printf("ERR: BusError WR\n");							\
   125 			m68k_pulse_bus_error();									\
   126 			return;													\
   127 		}															\
   128 	} while (false)
   130 /**
   131  * @brief Check memory access permissions for a read operation.
   132  * @note	This used to be a single macro (merged with ACCESS_CHECK_WR), but
   133  * 			gcc throws warnings when you have a return-with-value in a void
   134  * 			function, even if the return-with-value is completely unreachable.
   135  * 			Similarly it doesn't like it if you have a return without a value
   136  * 			in a non-void function, even if it's impossible to ever reach the
   137  * 			return-with-no-value. UGH!
   138  */
   139 #define ACCESS_CHECK_RD(address, bits) do {							\
   140 		bool fault = false;											\
   141 		/* MEM_STATUS st; */										\
   142 		switch (checkMemoryAccess(address, false)) {				\
   143 			case MEM_ALLOWED:										\
   144 				/* Access allowed */								\
   145 				break;												\
   146 			case MEM_PAGEFAULT:										\
   147 				/* Page fault */									\
   148 				state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0);	\
   149 				fault = true;										\
   150 				break;												\
   151 			case MEM_UIE:											\
   152 				/* User access to memory above 4MB */				\
   153 				state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0);	\
   154 				fault = true;										\
   155 				break;												\
   156 			case MEM_KERNEL:										\
   157 			case MEM_PAGE_NO_WE:									\
   158 				/* kernel access or page not write enabled */		\
   159 				/* TODO: which regs need setting? */				\
   160 				fault = true;										\
   161 				break;												\
   162 		}															\
   163 																	\
   164 		if (fault) {												\
   165 			if (bits >= 16)											\
   166 				state.bsr0 = 0x7F00;								\
   167 			else													\
   168 				state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00;		\
   169 			state.bsr0 |= (address >> 16);							\
   170 			state.bsr1 = address & 0xffff;							\
   171 			printf("ERR: BusError RD\n");							\
   172 			m68k_pulse_bus_error();									\
   173 			return 0xFFFFFFFF;										\
   174 		}															\
   175 	} while (false)
   177 // Logging macros
   178 #define LOG_NOT_HANDLED_R(bits)																	\
   179 	do {																						\
   180 		if (!handled)																			\
   181 			printf("unhandled read%02d, addr=0x%08X\n", bits, address);							\
   182 	} while (0);
   184 #define LOG_NOT_HANDLED_W(bits)																	\
   185 	do {																						\
   186 		if (!handled)																			\
   187 			printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, value);	\
   188 	} while (0);
   190 /**
   191  * @brief Read M68K memory, 32-bit
   192  */
   193 uint32_t m68k_read_memory_32(uint32_t address)
   194 {
   195 	uint32_t data = 0xFFFFFFFF;
   196 	bool handled = false;
   198 	// If ROMLMAP is set, force system to access ROM
   199 	if (!state.romlmap)
   200 		address |= 0x800000;
   202 	// Check access permissions
   203 	ACCESS_CHECK_RD(address, 32);
   205 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   206 		// ROM access
   207 		data = RD32(state.rom, address, ROM_SIZE - 1);
   208 		handled = true;
   209 	} else if (address <= (state.ram_size - 1)) {
   210 		// RAM access
   211 		data = RD32(state.ram, mapAddr(address, false), state.ram_size - 1);
   212 		handled = true;
   213 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   214 		// I/O register space, zone A
   215 		switch (address & 0x0F0000) {
   216 			case 0x000000:				// Map RAM access
   217 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
   218 				data = RD32(state.map, address, 0x7FF);
   219 				handled = true;
   220 				break;
   221 			case 0x010000:				// General Status Register
   222 				data = ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
   223 				handled = true;
   224 				break;
   225 			case 0x020000:				// Video RAM
   226 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
   227 				data = RD32(state.vram, address, 0x7FFF);
   228 				handled = true;
   229 				break;
   230 			case 0x030000:				// Bus Status Register 0
   231 				data = ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
   232 				handled = true;
   233 				break;
   234 			case 0x040000:				// Bus Status Register 1
   235 				data = ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
   236 				handled = true;
   237 				break;
   238 			case 0x050000:				// Phone status
   239 				break;
   240 			case 0x060000:				// DMA Count
   241 				// TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
   242 				// Bit 14 is always unused, so leave it set
   243 				data = (state.dma_count & 0x3fff) | 0xC000;
   244 				handled = true;
   245 				break;
   246 			case 0x070000:				// Line Printer Status Register
   247 				data = 0x00120012;	// no parity error, no line printer error, no irqs from FDD or HDD
   248 				data |= (state.fdc_ctx.irql) ? 0x00080008 : 0;	// FIXME! HACKHACKHACK! shouldn't peek inside FDC structs like this
   249 				break;
   250 			case 0x080000:				// Real Time Clock
   251 				break;
   252 			case 0x090000:				// Phone registers
   253 				switch (address & 0x0FF000) {
   254 					case 0x090000:		// Handset relay
   255 					case 0x098000:
   256 						break;
   257 					case 0x091000:		// Line select 2
   258 					case 0x099000:
   259 						break;
   260 					case 0x092000:		// Hook relay 1
   261 					case 0x09A000:
   262 						break;
   263 					case 0x093000:		// Hook relay 2
   264 					case 0x09B000:
   265 						break;
   266 					case 0x094000:		// Line 1 hold
   267 					case 0x09C000:
   268 						break;
   269 					case 0x095000:		// Line 2 hold
   270 					case 0x09D000:
   271 						break;
   272 					case 0x096000:		// Line 1 A-lead
   273 					case 0x09E000:
   274 						break;
   275 					case 0x097000:		// Line 2 A-lead
   276 					case 0x09F000:
   277 						break;
   278 				}
   279 				break;
   280 			case 0x0A0000:				// Miscellaneous Control Register -- write only!
   281 				handled = true;
   282 				break;
   283 			case 0x0B0000:				// TM/DIALWR
   284 				break;
   285 			case 0x0C0000:				// Clear Status Register -- write only!
   286 				handled = true;
   287 				break;
   288 			case 0x0D0000:				// DMA Address Register
   289 				break;
   290 			case 0x0E0000:				// Disk Control Register
   291 				break;
   292 			case 0x0F0000:				// Line Printer Data Register
   293 				break;
   294 		}
   295 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   296 		// I/O register space, zone B
   297 		switch (address & 0xF00000) {
   298 			case 0xC00000:				// Expansion slots
   299 			case 0xD00000:
   300 				switch (address & 0xFC0000) {
   301 					case 0xC00000:		// Expansion slot 0
   302 					case 0xC40000:		// Expansion slot 1
   303 					case 0xC80000:		// Expansion slot 2
   304 					case 0xCC0000:		// Expansion slot 3
   305 					case 0xD00000:		// Expansion slot 4
   306 					case 0xD40000:		// Expansion slot 5
   307 					case 0xD80000:		// Expansion slot 6
   308 					case 0xDC0000:		// Expansion slot 7
   309 						fprintf(stderr, "NOTE: RD32 from expansion card space, addr=0x%08X\n", address);
   310 						break;
   311 				}
   312 				break;
   313 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   314 			case 0xF00000:
   315 				switch (address & 0x070000) {
   316 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   317 						break;
   318 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   319 						data = wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
   320 						printf("WD279X: rd32 %02X ==> %02X\n", (address >> 1) & 3, data);
   321 						handled = true;
   322 						break;
   323 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   324 						break;
   325 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   326 						break;
   327 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   328 						switch (address & 0x077000) {
   329 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   330 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   331 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   332 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   333 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   334 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   335 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   336 								// All write-only registers... TODO: bus error?
   337 								handled = true;
   338 								break;
   339 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
   340 								break;
   341 						}
   342 						break;
   343 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   344 						break;
   345 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   346 						switch (address & 0x07F000) {
   347 							default:
   348 								break;
   349 						}
   350 						break;
   351 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   352 						break;
   353 				}
   354 		}
   355 	}
   357 	LOG_NOT_HANDLED_R(32);
   358 	return data;
   359 }
   361 /**
   362  * @brief Read M68K memory, 16-bit
   363  */
   364 uint32_t m68k_read_memory_16(uint32_t address)
   365 {
   366 	uint16_t data = 0xFFFF;
   367 	bool handled = false;
   369 	// If ROMLMAP is set, force system to access ROM
   370 	if (!state.romlmap)
   371 		address |= 0x800000;
   373 	// Check access permissions
   374 	ACCESS_CHECK_RD(address, 16);
   376 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   377 		// ROM access
   378 		data = RD16(state.rom, address, ROM_SIZE - 1);
   379 		handled = true;
   380 	} else if (address <= (state.ram_size - 1)) {
   381 		// RAM access
   382 		data = RD16(state.ram, mapAddr(address, false), state.ram_size - 1);
   383 		handled = true;
   384 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   385 		// I/O register space, zone A
   386 		switch (address & 0x0F0000) {
   387 			case 0x000000:				// Map RAM access
   388 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
   389 				data = RD16(state.map, address, 0x7FF);
   390 				handled = true;
   391 				break;
   392 			case 0x010000:				// General Status Register
   393 				data = state.genstat;
   394 				handled = true;
   395 				break;
   396 			case 0x020000:				// Video RAM
   397 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
   398 				data = RD16(state.vram, address, 0x7FFF);
   399 				handled = true;
   400 				break;
   401 			case 0x030000:				// Bus Status Register 0
   402 				data = state.bsr0;
   403 				handled = true;
   404 				break;
   405 			case 0x040000:				// Bus Status Register 1
   406 				data = state.bsr1;
   407 				handled = true;
   408 				break;
   409 			case 0x050000:				// Phone status
   410 				break;
   411 			case 0x060000:				// DMA Count
   412 				// TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
   413 				// Bit 14 is always unused, so leave it set
   414 				data = (state.dma_count & 0x3fff) | 0xC000;
   415 				handled = true;
   416 				break;
   417 			case 0x070000:				// Line Printer Status Register
   418 				data = 0x0012;	// no parity error, no line printer error, no irqs from FDD or HDD
   419 				data |= (state.fdc_ctx.irql) ? 0x0008 : 0;	// FIXME! HACKHACKHACK! shouldn't peek inside FDC structs like this
   420 				break;
   421 			case 0x080000:				// Real Time Clock
   422 				break;
   423 			case 0x090000:				// Phone registers
   424 				switch (address & 0x0FF000) {
   425 					case 0x090000:		// Handset relay
   426 					case 0x098000:
   427 						break;
   428 					case 0x091000:		// Line select 2
   429 					case 0x099000:
   430 						break;
   431 					case 0x092000:		// Hook relay 1
   432 					case 0x09A000:
   433 						break;
   434 					case 0x093000:		// Hook relay 2
   435 					case 0x09B000:
   436 						break;
   437 					case 0x094000:		// Line 1 hold
   438 					case 0x09C000:
   439 						break;
   440 					case 0x095000:		// Line 2 hold
   441 					case 0x09D000:
   442 						break;
   443 					case 0x096000:		// Line 1 A-lead
   444 					case 0x09E000:
   445 						break;
   446 					case 0x097000:		// Line 2 A-lead
   447 					case 0x09F000:
   448 						break;
   449 				}
   450 				break;
   451 			case 0x0A0000:				// Miscellaneous Control Register -- write only!
   452 				handled = true;
   453 				break;
   454 			case 0x0B0000:				// TM/DIALWR
   455 				break;
   456 			case 0x0C0000:				// Clear Status Register -- write only!
   457 				handled = true;
   458 				break;
   459 			case 0x0D0000:				// DMA Address Register
   460 				break;
   461 			case 0x0E0000:				// Disk Control Register
   462 				break;
   463 			case 0x0F0000:				// Line Printer Data Register
   464 				break;
   465 		}
   466 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   467 		// I/O register space, zone B
   468 		switch (address & 0xF00000) {
   469 			case 0xC00000:				// Expansion slots
   470 			case 0xD00000:
   471 				switch (address & 0xFC0000) {
   472 					case 0xC00000:		// Expansion slot 0
   473 					case 0xC40000:		// Expansion slot 1
   474 					case 0xC80000:		// Expansion slot 2
   475 					case 0xCC0000:		// Expansion slot 3
   476 					case 0xD00000:		// Expansion slot 4
   477 					case 0xD40000:		// Expansion slot 5
   478 					case 0xD80000:		// Expansion slot 6
   479 					case 0xDC0000:		// Expansion slot 7
   480 						fprintf(stderr, "NOTE: RD16 from expansion card space, addr=0x%08X\n", address);
   481 						break;
   482 				}
   483 				break;
   484 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   485 			case 0xF00000:
   486 				switch (address & 0x070000) {
   487 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   488 						break;
   489 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   490 						data = wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
   491 						printf("WD279X: rd16 %02X ==> %02X\n", (address >> 1) & 3, data);
   492 						handled = true;
   493 						break;
   494 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   495 						break;
   496 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   497 						break;
   498 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   499 						switch (address & 0x077000) {
   500 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   501 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   502 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   503 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   504 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   505 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   506 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   507 								// All write-only registers... TODO: bus error?
   508 								handled = true;
   509 								break;
   510 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   511 								break;
   512 						}
   513 						break;
   514 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   515 						break;
   516 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   517 						switch (address & 0x07F000) {
   518 							default:
   519 								break;
   520 						}
   521 						break;
   522 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   523 						break;
   524 				}
   525 		}
   526 	}
   528 	LOG_NOT_HANDLED_R(16);
   529 	return data;
   530 }
   532 /**
   533  * @brief Read M68K memory, 8-bit
   534  */
   535 uint32_t m68k_read_memory_8(uint32_t address)
   536 {
   537 	uint8_t data = 0xFF;
   538 	bool handled = false;
   540 	// If ROMLMAP is set, force system to access ROM
   541 	if (!state.romlmap)
   542 		address |= 0x800000;
   544 	// Check access permissions
   545 	ACCESS_CHECK_RD(address, 8);
   547 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   548 		// ROM access
   549 		data = RD8(state.rom, address, ROM_SIZE - 1);
   550 		handled = true;
   551 	} else if (address <= (state.ram_size - 1)) {
   552 		// RAM access
   553 		data = RD8(state.ram, mapAddr(address, false), state.ram_size - 1);
   554 		handled = true;
   555 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   556 		// I/O register space, zone A
   557 		switch (address & 0x0F0000) {
   558 			case 0x000000:				// Map RAM access
   559 				if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
   560 				data = RD8(state.map, address, 0x7FF);
   561 				handled = true;
   562 				break;
   563 			case 0x010000:				// General Status Register
   564 				if ((address & 1) == 0)
   565 					data = (state.genstat >> 8) & 0xff;
   566 				else
   567 					data = (state.genstat)      & 0xff;
   568 				handled = true;
   569 				break;
   570 			case 0x020000:				// Video RAM
   571 				if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
   572 				data = RD8(state.vram, address, 0x7FFF);
   573 				handled = true;
   574 				break;
   575 			case 0x030000:				// Bus Status Register 0
   576 				if ((address & 1) == 0)
   577 					data = (state.bsr0 >> 8) & 0xff;
   578 				else
   579 					data = (state.bsr0)      & 0xff;
   580 				handled = true;
   581 				break;
   582 			case 0x040000:				// Bus Status Register 1
   583 				if ((address & 1) == 0)
   584 					data = (state.bsr1 >> 8) & 0xff;
   585 				else
   586 					data = (state.bsr1)      & 0xff;
   587 				handled = true;
   588 				break;
   589 			case 0x050000:				// Phone status
   590 				break;
   591 			case 0x060000:				// DMA Count
   592 				// TODO: how to handle this in 8bit mode?
   593 				break;
   594 			case 0x070000:				// Line Printer Status Register
   595 				printf("\tLPSR RD8 fdc irql=%d, irqe=%d\n", state.fdc_ctx.irql, state.fdc_ctx.irqe);
   596 				if (address & 1) {
   597 					data = 0x12;	// no parity error, no line printer error, no irqs from FDD or HDD
   598 					data |= (state.fdc_ctx.irql) ? 0x08 : 0;	// FIXME! HACKHACKHACK! shouldn't peek inside FDC structs like this
   599 //					data |= 0x04; // HDD interrupt, i.e. command complete -- HACKHACKHACK!
   600 				} else {
   601 					data = 0;
   602 				}
   603 				handled = true;
   604 				break;
   605 			case 0x080000:				// Real Time Clock
   606 				break;
   607 			case 0x090000:				// Phone registers
   608 				switch (address & 0x0FF000) {
   609 					case 0x090000:		// Handset relay
   610 					case 0x098000:
   611 						break;
   612 					case 0x091000:		// Line select 2
   613 					case 0x099000:
   614 						break;
   615 					case 0x092000:		// Hook relay 1
   616 					case 0x09A000:
   617 						break;
   618 					case 0x093000:		// Hook relay 2
   619 					case 0x09B000:
   620 						break;
   621 					case 0x094000:		// Line 1 hold
   622 					case 0x09C000:
   623 						break;
   624 					case 0x095000:		// Line 2 hold
   625 					case 0x09D000:
   626 						break;
   627 					case 0x096000:		// Line 1 A-lead
   628 					case 0x09E000:
   629 						break;
   630 					case 0x097000:		// Line 2 A-lead
   631 					case 0x09F000:
   632 						break;
   633 				}
   634 				break;
   635 			case 0x0A0000:				// Miscellaneous Control Register -- write only!
   636 				handled = true;
   637 				break;
   638 			case 0x0B0000:				// TM/DIALWR
   639 				break;
   640 			case 0x0C0000:				// Clear Status Register -- write only!
   641 				handled = true;
   642 				break;
   643 			case 0x0D0000:				// DMA Address Register
   644 				break;
   645 			case 0x0E0000:				// Disk Control Register
   646 				break;
   647 			case 0x0F0000:				// Line Printer Data Register
   648 				break;
   649 		}
   650 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   651 		// I/O register space, zone B
   652 		switch (address & 0xF00000) {
   653 			case 0xC00000:				// Expansion slots
   654 			case 0xD00000:
   655 				switch (address & 0xFC0000) {
   656 					case 0xC00000:		// Expansion slot 0
   657 					case 0xC40000:		// Expansion slot 1
   658 					case 0xC80000:		// Expansion slot 2
   659 					case 0xCC0000:		// Expansion slot 3
   660 					case 0xD00000:		// Expansion slot 4
   661 					case 0xD40000:		// Expansion slot 5
   662 					case 0xD80000:		// Expansion slot 6
   663 					case 0xDC0000:		// Expansion slot 7
   664 						fprintf(stderr, "NOTE: RD8 from expansion card space, addr=0x%08X\n", address);
   665 						break;
   666 				}
   667 				break;
   668 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   669 			case 0xF00000:
   670 				switch (address & 0x070000) {
   671 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   672 						break;
   673 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   674 						data = wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
   675 						printf("WD279X: rd8 %02X ==> %02X\n", (address >> 1) & 3, data);
   676 						handled = true;
   677 						break;
   678 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   679 						break;
   680 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   681 						break;
   682 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   683 						switch (address & 0x077000) {
   684 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   685 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   686 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   687 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   688 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   689 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   690 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   691 								// All write-only registers... TODO: bus error?
   692 								handled = true;
   693 								break;
   694 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   695 								break;
   696 						}
   697 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   698 						break;
   699 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   700 						switch (address & 0x07F000) {
   701 							default:
   702 								break;
   703 						}
   704 						break;
   705 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   706 						break;
   707 				}
   708 		}
   709 	}
   711 	LOG_NOT_HANDLED_R(8);
   713 	return data;
   714 }
   716 /**
   717  * @brief Write M68K memory, 32-bit
   718  */
   719 void m68k_write_memory_32(uint32_t address, uint32_t value)
   720 {
   721 	bool handled = false;
   723 	// If ROMLMAP is set, force system to access ROM
   724 	if (!state.romlmap)
   725 		address |= 0x800000;
   727 	// Check access permissions
   728 	ACCESS_CHECK_WR(address, 32);
   730 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   731 		// ROM access
   732 		handled = true;
   733 	} else if (address <= (state.ram_size - 1)) {
   734 		// RAM access
   735 		WR32(state.ram, mapAddr(address, false), state.ram_size - 1, value);
   736 		handled = true;
   737 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   738 		// I/O register space, zone A
   739 		switch (address & 0x0F0000) {
   740 			case 0x000000:				// Map RAM access
   741 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
   742 				WR32(state.map, address, 0x7FF, value);
   743 				handled = true;
   744 				break;
   745 			case 0x010000:				// General Status Register
   746 				state.genstat = (value & 0xffff);
   747 				handled = true;
   748 				break;
   749 			case 0x020000:				// Video RAM
   750 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X, data=0x%08X\n", address, value);
   751 				WR32(state.vram, address, 0x7FFF, value);
   752 				handled = true;
   753 				break;
   754 			case 0x030000:				// Bus Status Register 0
   755 				break;
   756 			case 0x040000:				// Bus Status Register 1
   757 				break;
   758 			case 0x050000:				// Phone status
   759 				break;
   760 			case 0x060000:				// DMA Count
   761 				printf("WR32 dmacount %08X\n", value);
   762 				state.dma_count = (value & 0x3FFF);
   763 				state.idmarw = ((value & 0x4000) == 0x4000);
   764 				state.dmaen = ((value & 0x8000) == 0x8000);
   765 				printf("\tcount %04X, idmarw %d, dmaen %d\n", state.dma_count, state.idmarw, state.dmaen);
   766 				// This handles the "dummy DMA transfer" mentioned in the docs
   767 				// TODO: access check, peripheral access
   768 				if (!state.idmarw)
   769 					WR32(state.ram, mapAddr(address, false), state.ram_size - 1, 0xDEAD);
   770 				state.dma_count++;
   771 				handled = true;
   772 				break;
   773 			case 0x070000:				// Line Printer Status Register
   774 				break;
   775 			case 0x080000:				// Real Time Clock
   776 				break;
   777 			case 0x090000:				// Phone registers
   778 				switch (address & 0x0FF000) {
   779 					case 0x090000:		// Handset relay
   780 					case 0x098000:
   781 						break;
   782 					case 0x091000:		// Line select 2
   783 					case 0x099000:
   784 						break;
   785 					case 0x092000:		// Hook relay 1
   786 					case 0x09A000:
   787 						break;
   788 					case 0x093000:		// Hook relay 2
   789 					case 0x09B000:
   790 						break;
   791 					case 0x094000:		// Line 1 hold
   792 					case 0x09C000:
   793 						break;
   794 					case 0x095000:		// Line 2 hold
   795 					case 0x09D000:
   796 						break;
   797 					case 0x096000:		// Line 1 A-lead
   798 					case 0x09E000:
   799 						break;
   800 					case 0x097000:		// Line 2 A-lead
   801 					case 0x09F000:
   802 						break;
   803 				}
   804 				break;
   805 			case 0x0A0000:				// Miscellaneous Control Register
   806 				// TODO: handle the ctrl bits properly
   807 				// TODO: &0x8000 --> dismiss 60hz intr
   808 				state.dma_reading = (value & 0x4000);
   809 				state.leds = (~value & 0xF00) >> 8;
   810 				printf("LEDs: %s %s %s %s\n",
   811 						(state.leds & 8) ? "R" : "-",
   812 						(state.leds & 4) ? "G" : "-",
   813 						(state.leds & 2) ? "Y" : "-",
   814 						(state.leds & 1) ? "R" : "-");
   815 				handled = true;
   816 				break;
   817 			case 0x0B0000:				// TM/DIALWR
   818 				break;
   819 			case 0x0C0000:				// Clear Status Register
   820 				state.genstat = 0xFFFF;
   821 				state.bsr0 = 0xFFFF;
   822 				state.bsr1 = 0xFFFF;
   823 				handled = true;
   824 				break;
   825 			case 0x0D0000:				// DMA Address Register
   826 				if (address & 0x004000) {
   827 					// A14 high -- set most significant bits
   828 					state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
   829 				} else {
   830 					// A14 low -- set least significant bits
   831 					state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
   832 				}
   833 				printf("WR32 DMA_ADDR %s, now %08X\n", address & 0x004000 ? "HI" : "LO", state.dma_address);
   834 				handled = true;
   835 				break;
   836 			case 0x0E0000:				// Disk Control Register
   837 				// B7 = FDD controller reset
   838 				if ((value & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
   839 				// B6 = drive 0 select -- TODO
   840 				// B5 = motor enable -- TODO
   841 				// B4 = HDD controller reset -- TODO
   842 				// B3 = HDD0 select -- TODO
   843 				// B2,1,0 = HDD0 head select
   844 				handled = true;
   845 				break;
   846 			case 0x0F0000:				// Line Printer Data Register
   847 				break;
   848 		}
   849 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
   850 		// I/O register space, zone B
   851 		switch (address & 0xF00000) {
   852 			case 0xC00000:				// Expansion slots
   853 			case 0xD00000:
   854 				switch (address & 0xFC0000) {
   855 					case 0xC00000:		// Expansion slot 0
   856 					case 0xC40000:		// Expansion slot 1
   857 					case 0xC80000:		// Expansion slot 2
   858 					case 0xCC0000:		// Expansion slot 3
   859 					case 0xD00000:		// Expansion slot 4
   860 					case 0xD40000:		// Expansion slot 5
   861 					case 0xD80000:		// Expansion slot 6
   862 					case 0xDC0000:		// Expansion slot 7
   863 						fprintf(stderr, "NOTE: WR32 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
   864 						handled = true;
   865 						break;
   866 				}
   867 				break;
   868 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
   869 			case 0xF00000:
   870 				switch (address & 0x070000) {
   871 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
   872 						break;
   873 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
   874 						printf("WD279X: wr32 %02X ==> %02X\n", (address >> 1) & 3, value);
   875 						wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, value);
   876 						handled = true;
   877 						break;
   878 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
   879 						break;
   880 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
   881 						break;
   882 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
   883 						switch (address & 0x077000) {
   884 							case 0x040000:		// [ef][4c][08]xxx ==> EE
   885 								break;
   886 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
   887 								state.pie = ((value & 0x8000) == 0x8000);
   888 								handled = true;
   889 								break;
   890 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
   891 								break;
   892 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
   893 								state.romlmap = ((value & 0x8000) == 0x8000);
   894 								handled = true;
   895 								break;
   896 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
   897 								break;
   898 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
   899 								break;
   900 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
   901 								break;
   902 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
   903 								break;
   904 						}
   905 					case 0x050000:		// [ef][5d]xxxx ==> 8274
   906 						break;
   907 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
   908 						switch (address & 0x07F000) {
   909 							default:
   910 								break;
   911 						}
   912 						break;
   913 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
   914 						break;
   915 				}
   916 		}
   917 	}
   919 	LOG_NOT_HANDLED_W(32);
   920 }
   922 /**
   923  * @brief Write M68K memory, 16-bit
   924  */
   925 void m68k_write_memory_16(uint32_t address, uint32_t value)
   926 {
   927 	bool handled = false;
   929 	// If ROMLMAP is set, force system to access ROM
   930 	if (!state.romlmap)
   931 		address |= 0x800000;
   933 	// Check access permissions
   934 	ACCESS_CHECK_WR(address, 16);
   936 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   937 		// ROM access
   938 		handled = true;
   939 	} else if (address <= (state.ram_size - 1)) {
   940 		// RAM access
   941 		WR16(state.ram, mapAddr(address, false), state.ram_size - 1, value);
   942 		handled = true;
   943 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   944 		// I/O register space, zone A
   945 		switch (address & 0x0F0000) {
   946 			case 0x000000:				// Map RAM access
   947 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   948 				WR16(state.map, address, 0x7FF, value);
   949 				handled = true;
   950 				break;
   951 			case 0x010000:				// General Status Register (read only)
   952 				handled = true;
   953 				break;
   954 			case 0x020000:				// Video RAM
   955 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
   956 				WR16(state.vram, address, 0x7FFF, value);
   957 				handled = true;
   958 				break;
   959 			case 0x030000:				// Bus Status Register 0 (read only)
   960 				handled = true;
   961 				break;
   962 			case 0x040000:				// Bus Status Register 1 (read only)
   963 				handled = true;
   964 				break;
   965 			case 0x050000:				// Phone status
   966 				break;
   967 			case 0x060000:				// DMA Count
   968 				printf("WR16 dmacount %08X\n", value);
   969 				state.dma_count = (value & 0x3FFF);
   970 				state.idmarw = ((value & 0x4000) == 0x4000);
   971 				state.dmaen = ((value & 0x8000) == 0x8000);
   972 				printf("\tcount %04X, idmarw %d, dmaen %d\n", state.dma_count, state.idmarw, state.dmaen);
   973 				// This handles the "dummy DMA transfer" mentioned in the docs
   974 				// TODO: access check, peripheral access
   975 				if (!state.idmarw)
   976 					WR32(state.ram, mapAddr(address, false), state.ram_size - 1, 0xDEAD);
   977 				state.dma_count++;
   978 				handled = true;
   979 				break;
   980 			case 0x070000:				// Line Printer Status Register
   981 				break;
   982 			case 0x080000:				// Real Time Clock
   983 				break;
   984 			case 0x090000:				// Phone registers
   985 				switch (address & 0x0FF000) {
   986 					case 0x090000:		// Handset relay
   987 					case 0x098000:
   988 						break;
   989 					case 0x091000:		// Line select 2
   990 					case 0x099000:
   991 						break;
   992 					case 0x092000:		// Hook relay 1
   993 					case 0x09A000:
   994 						break;
   995 					case 0x093000:		// Hook relay 2
   996 					case 0x09B000:
   997 						break;
   998 					case 0x094000:		// Line 1 hold
   999 					case 0x09C000:
  1000 						break;
  1001 					case 0x095000:		// Line 2 hold
  1002 					case 0x09D000:
  1003 						break;
  1004 					case 0x096000:		// Line 1 A-lead
  1005 					case 0x09E000:
  1006 						break;
  1007 					case 0x097000:		// Line 2 A-lead
  1008 					case 0x09F000:
  1009 						break;
  1011 				break;
  1012 			case 0x0A0000:				// Miscellaneous Control Register
  1013 				// TODO: handle the ctrl bits properly
  1014 				// TODO: &0x8000 --> dismiss 60hz intr
  1015 				state.dma_reading = (value & 0x4000);
  1016 				state.leds = (~value & 0xF00) >> 8;
  1017 				printf("LEDs: %s %s %s %s\n",
  1018 						(state.leds & 8) ? "R" : "-",
  1019 						(state.leds & 4) ? "G" : "-",
  1020 						(state.leds & 2) ? "Y" : "-",
  1021 						(state.leds & 1) ? "R" : "-");
  1022 				handled = true;
  1023 				break;
  1024 			case 0x0B0000:				// TM/DIALWR
  1025 				break;
  1026 			case 0x0C0000:				// Clear Status Register
  1027 				state.genstat = 0xFFFF;
  1028 				state.bsr0 = 0xFFFF;
  1029 				state.bsr1 = 0xFFFF;
  1030 				handled = true;
  1031 				break;
  1032 			case 0x0D0000:				// DMA Address Register
  1033 				if (address & 0x004000) {
  1034 					// A14 high -- set most significant bits
  1035 					state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
  1036 				} else {
  1037 					// A14 low -- set least significant bits
  1038 					state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
  1040 				printf("WR16 DMA_ADDR %s, now %08X\n", address & 0x004000 ? "HI" : "LO", state.dma_address);
  1041 				handled = true;
  1042 				break;
  1043 			case 0x0E0000:				// Disk Control Register
  1044 				// B7 = FDD controller reset
  1045 				if ((value & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
  1046 				// B6 = drive 0 select -- TODO
  1047 				// B5 = motor enable -- TODO
  1048 				// B4 = HDD controller reset -- TODO
  1049 				// B3 = HDD0 select -- TODO
  1050 				// B2,1,0 = HDD0 head select
  1051 				handled = true;
  1052 				break;
  1053 			case 0x0F0000:				// Line Printer Data Register
  1054 				break;
  1056 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
  1057 		// I/O register space, zone B
  1058 		switch (address & 0xF00000) {
  1059 			case 0xC00000:				// Expansion slots
  1060 			case 0xD00000:
  1061 				switch (address & 0xFC0000) {
  1062 					case 0xC00000:		// Expansion slot 0
  1063 					case 0xC40000:		// Expansion slot 1
  1064 					case 0xC80000:		// Expansion slot 2
  1065 					case 0xCC0000:		// Expansion slot 3
  1066 					case 0xD00000:		// Expansion slot 4
  1067 					case 0xD40000:		// Expansion slot 5
  1068 					case 0xD80000:		// Expansion slot 6
  1069 					case 0xDC0000:		// Expansion slot 7
  1070 						fprintf(stderr, "NOTE: WR16 to expansion card space, addr=0x%08X, data=0x%04X\n", address, value);
  1071 						break;
  1073 				break;
  1074 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
  1075 			case 0xF00000:
  1076 				switch (address & 0x070000) {
  1077 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
  1078 						break;
  1079 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
  1080 						printf("WD279X: wr16 %02X ==> %02X\n", (address >> 1) & 3, value);
  1081 						wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, value);
  1082 						handled = true;
  1083 						break;
  1084 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
  1085 						break;
  1086 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
  1087 						break;
  1088 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
  1089 						switch (address & 0x077000) {
  1090 							case 0x040000:		// [ef][4c][08]xxx ==> EE
  1091 								break;
  1092 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
  1093 								state.pie = ((value & 0x8000) == 0x8000);
  1094 								handled = true;
  1095 								break;
  1096 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
  1097 								break;
  1098 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
  1099 								state.romlmap = ((value & 0x8000) == 0x8000);
  1100 								handled = true;
  1101 								break;
  1102 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
  1103 								break;
  1104 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
  1105 								break;
  1106 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
  1107 								break;
  1108 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
  1109 								break;
  1111 					case 0x050000:		// [ef][5d]xxxx ==> 8274
  1112 						break;
  1113 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
  1114 						switch (address & 0x07F000) {
  1115 							default:
  1116 								break;
  1118 						break;
  1119 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
  1120 						break;
  1125 	LOG_NOT_HANDLED_W(16);
  1128 /**
  1129  * @brief Write M68K memory, 8-bit
  1130  */
  1131 void m68k_write_memory_8(uint32_t address, uint32_t value)
  1133 	bool handled = false;
  1135 	// If ROMLMAP is set, force system to access ROM
  1136 	if (!state.romlmap)
  1137 		address |= 0x800000;
  1139 	// Check access permissions
  1140 	ACCESS_CHECK_WR(address, 8);
  1142 	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
  1143 		// ROM access (read only!)
  1144 		handled = true;
  1145 	} else if (address <= (state.ram_size - 1)) {
  1146 		// RAM access
  1147 		WR8(state.ram, mapAddr(address, false), state.ram_size - 1, value);
  1148 		handled = true;
  1149 	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
  1150 		// I/O register space, zone A
  1151 		switch (address & 0x0F0000) {
  1152 			case 0x000000:				// Map RAM access
  1153 				if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=%08X, data=%02X\n", address, value);
  1154 				WR8(state.map, address, 0x7FF, value);
  1155 				handled = true;
  1156 				break;
  1157 			case 0x010000:				// General Status Register
  1158 				handled = true;
  1159 				break;
  1160 			case 0x020000:				// Video RAM
  1161 				if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=%08X, data=0x%02X\n", address, value);
  1162 				WR8(state.vram, address, 0x7FFF, value);
  1163 				handled = true;
  1164 				break;
  1165 			case 0x030000:				// Bus Status Register 0
  1166 				handled = true;
  1167 				break;
  1168 			case 0x040000:				// Bus Status Register 1
  1169 				handled = true;
  1170 				break;
  1171 			case 0x050000:				// Phone status
  1172 				break;
  1173 			case 0x060000:				// DMA Count
  1174 				// TODO: how to handle this in 8bit mode?
  1175 				break;
  1176 			case 0x070000:				// Line Printer Status Register
  1177 				break;
  1178 			case 0x080000:				// Real Time Clock
  1179 				break;
  1180 			case 0x090000:				// Phone registers
  1181 				switch (address & 0x0FF000) {
  1182 					case 0x090000:		// Handset relay
  1183 					case 0x098000:
  1184 						break;
  1185 					case 0x091000:		// Line select 2
  1186 					case 0x099000:
  1187 						break;
  1188 					case 0x092000:		// Hook relay 1
  1189 					case 0x09A000:
  1190 						break;
  1191 					case 0x093000:		// Hook relay 2
  1192 					case 0x09B000:
  1193 						break;
  1194 					case 0x094000:		// Line 1 hold
  1195 					case 0x09C000:
  1196 						break;
  1197 					case 0x095000:		// Line 2 hold
  1198 					case 0x09D000:
  1199 						break;
  1200 					case 0x096000:		// Line 1 A-lead
  1201 					case 0x09E000:
  1202 						break;
  1203 					case 0x097000:		// Line 2 A-lead
  1204 					case 0x09F000:
  1205 						break;
  1207 				break;
  1208 			case 0x0A0000:				// Miscellaneous Control Register
  1209 				// TODO: how to handle this in 8bit mode?
  1210 /*
  1211 				// TODO: handle the ctrl bits properly
  1212 				if ((address & 1) == 0) {
  1213 					// low byte
  1214 				} else {
  1215 					// hight byte
  1216 					// TODO: &0x8000 --> dismiss 60hz intr
  1217 					state.dma_reading = (value & 0x40);
  1218 					state.leds = (~value & 0xF);
  1220 				printf("LEDs: %s %s %s %s\n",
  1221 						(state.leds & 8) ? "R" : "-",
  1222 						(state.leds & 4) ? "G" : "-",
  1223 						(state.leds & 2) ? "Y" : "-",
  1224 						(state.leds & 1) ? "R" : "-");
  1225 				handled = true;
  1226 */
  1227 				break;
  1228 			case 0x0B0000:				// TM/DIALWR
  1229 				break;
  1230 			case 0x0C0000:				// Clear Status Register
  1231 				state.genstat = 0xFFFF;
  1232 				state.bsr0 = 0xFFFF;
  1233 				state.bsr1 = 0xFFFF;
  1234 				handled = true;
  1235 				break;
  1236 			case 0x0D0000:				// DMA Address Register
  1237 				if (address & 0x004000) {
  1238 					// A14 high -- set most significant bits
  1239 					state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
  1240 				} else {
  1241 					// A14 low -- set least significant bits
  1242 					state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
  1244 				printf("WR08 DMA_ADDR %s, now %08X\n", address & 0x004000 ? "HI" : "LO", state.dma_address);
  1245 				handled = true;
  1246 				break;
  1247 			case 0x0E0000:				// Disk Control Register
  1248 				// B7 = FDD controller reset
  1249 				if ((value & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
  1250 				// B6 = drive 0 select -- TODO
  1251 				// B5 = motor enable -- TODO
  1252 				// B4 = HDD controller reset -- TODO
  1253 				// B3 = HDD0 select -- TODO
  1254 				// B2,1,0 = HDD0 head select
  1255 				handled = true;
  1256 				break;
  1257 			case 0x0F0000:				// Line Printer Data Register
  1258 				break;
  1260 	} else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
  1261 		// I/O register space, zone B
  1262 		switch (address & 0xF00000) {
  1263 			case 0xC00000:				// Expansion slots
  1264 			case 0xD00000:
  1265 				switch (address & 0xFC0000) {
  1266 					case 0xC00000:		// Expansion slot 0
  1267 					case 0xC40000:		// Expansion slot 1
  1268 					case 0xC80000:		// Expansion slot 2
  1269 					case 0xCC0000:		// Expansion slot 3
  1270 					case 0xD00000:		// Expansion slot 4
  1271 					case 0xD40000:		// Expansion slot 5
  1272 					case 0xD80000:		// Expansion slot 6
  1273 					case 0xDC0000:		// Expansion slot 7
  1274 						fprintf(stderr, "NOTE: WR8 to expansion card space, addr=0x%08X, data=0x%08X\n", address, value);
  1275 						break;
  1277 				break;
  1278 			case 0xE00000:				// HDC, FDC, MCR2 and RTC data bits
  1279 			case 0xF00000:
  1280 				switch (address & 0x070000) {
  1281 					case 0x000000:		// [ef][08]xxxx ==> WD1010 hard disc controller
  1282 						break;
  1283 					case 0x010000:		// [ef][19]xxxx ==> WD2797 floppy disc controller
  1284 						printf("WD279X: wr8 %02X ==> %02X\n", (address >> 1) & 3, value);
  1285 						wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, value);
  1286 						handled = true;
  1287 						break;
  1288 					case 0x020000:		// [ef][2a]xxxx ==> Miscellaneous Control Register 2
  1289 						break;
  1290 					case 0x030000:		// [ef][3b]xxxx ==> Real Time Clock data bits
  1291 						break;
  1292 					case 0x040000:		// [ef][4c]xxxx ==> General Control Register
  1293 						switch (address & 0x077000) {
  1294 							case 0x040000:		// [ef][4c][08]xxx ==> EE
  1295 								break;
  1296 							case 0x041000:		// [ef][4c][19]xxx ==> PIE
  1297 								if ((address & 1) == 0)
  1298 									state.pie = ((value & 0x80) == 0x80);
  1299 								handled = true;
  1300 								break;
  1301 							case 0x042000:		// [ef][4c][2A]xxx ==> BP
  1302 								break;
  1303 							case 0x043000:		// [ef][4c][3B]xxx ==> ROMLMAP
  1304 								if ((address & 1) == 0)
  1305 									state.romlmap = ((value & 0x80) == 0x80);
  1306 								handled = true;
  1307 								break;
  1308 							case 0x044000:		// [ef][4c][4C]xxx ==> L1 MODEM
  1309 								break;
  1310 							case 0x045000:		// [ef][4c][5D]xxx ==> L2 MODEM
  1311 								break;
  1312 							case 0x046000:		// [ef][4c][6E]xxx ==> D/N CONNECT
  1313 								break;
  1314 							case 0x047000:		// [ef][4c][7F]xxx ==> Whole screen reverse video
  1315 								break;
  1317 					case 0x050000:		// [ef][5d]xxxx ==> 8274
  1318 						break;
  1319 					case 0x060000:		// [ef][6e]xxxx ==> Control regs
  1320 						switch (address & 0x07F000) {
  1321 							default:
  1322 								break;
  1324 						break;
  1325 					case 0x070000:		// [ef][7f]xxxx ==> 6850 Keyboard Controller
  1326 						break;
  1327 					default:
  1328 						fprintf(stderr, "NOTE: WR8 to undefined E/F-block space, addr=0x%08X, data=0x%08X\n", address, value);
  1329 						break;
  1334 	LOG_NOT_HANDLED_W(8);
  1338 // for the disassembler
  1339 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
  1340 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
  1341 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }