TMF Hg

fixed bus error handling for real this time (save registers before every instruction and push the saved registers if a bus error occurs, since the instruction may have changed registers before the bus error, and also stop the instruction immediately with longjmp so it won't change memory after the bus error)

  • Wed, 16 Apr 2014 02:20:43 -0600
  • by andrew@localhost [Wed, 16 Apr 2014 02:20:43 -0600] rev 147
  • fixed bus error handling for real this time (save registers before every instruction and push the saved registers if a bus error occurs, since the instruction may have changed registers before the bus error, and also stop the instruction immediately with longjmp so it won't change memory after the bus error)

    This isn't actually what a real 68k does, but it is a good enough approximation. A real 68k will jump back into the middle of the faulted instruction and resume it from the memory access that faulted as opposed to restarting from the beginning like this CPU emulation does. It would be a lot harder to do that with the way this CPU library is designed. Newer versions of MESS basically do the same thing (they use a newer version of this library).

added keyboard mappings for ENTER, CANCL, and EXIT

  • Wed, 16 Apr 2014 02:07:24 -0600
  • by andrew@localhost [Wed, 16 Apr 2014 02:07:24 -0600] rev 146
  • added keyboard mappings for ENTER, CANCL, and EXIT

Code clean up experimental_memory_mapper_v2

  • Tue, 21 May 2013 22:48:32 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Tue, 21 May 2013 22:48:32 +0100] rev 145
  • Code clean up

    * Tighten optimisation and warning options to find more potential issues
    * Remove unused variable in keyboard code
    * Display error message if ROMs fail to load
    * Fix format string bugs in WD2010

Don't set PS1 if there is a level-7 interrupt or bus error experimental_memory_mapper_v2

  • Fri, 12 Apr 2013 16:26:25 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Fri, 12 Apr 2013 16:26:25 +0100] rev 144
  • Don't set PS1 if there is a level-7 interrupt or bus error

    PS1 should only be set if the page was originally present (PS1 or PS0 set). If
    PS0 and PS1 are clear (page not present) then do NOT set PS1.

    Once again the TRM is blatantly and spectacularly wrong...

Flush stderr after printing debug messages experimental_memory_mapper_v2

  • Fri, 12 Apr 2013 12:37:34 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Fri, 12 Apr 2013 12:37:34 +0100] rev 143
  • Flush stderr after printing debug messages