1.1 diff -r 976dfa068839 -r 2ef98ea1e944 src/wd279x.c 1.2 --- a/src/wd279x.c Mon Dec 06 08:27:05 2010 +0000 1.3 +++ b/src/wd279x.c Mon Dec 06 08:27:21 2010 +0000 1.4 @@ -32,19 +32,20 @@ 1.5 ctx->track = ctx->head = ctx->sector = 0; 1.6 1.7 // no IRQ pending 1.8 - ctx->irql = ctx->irqe = false; 1.9 + ctx->irq = false; 1.10 1.11 // no data available 1.12 ctx->data_pos = ctx->data_len = 0; 1.13 ctx->data = NULL; 1.14 1.15 - // Status register clear, not busy 1.16 + // Status register clear, not busy; type1 command 1.17 ctx->status = 0; 1.18 + ctx->cmd_has_drq = false; 1.19 1.20 // Clear data register 1.21 ctx->data_reg = 0; 1.22 1.23 - // Last step direction 1.24 + // Last step direction = "towards zero" 1.25 ctx->last_step_dir = -1; 1.26 1.27 // No disc image loaded 1.28 @@ -59,7 +60,7 @@ 1.29 ctx->track = ctx->head = ctx->sector = 0; 1.30 1.31 // no IRQ pending 1.32 - ctx->irql = ctx->irqe = false; 1.33 + ctx->irq = false; 1.34 1.35 // no data available 1.36 ctx->data_pos = ctx->data_len = 0; 1.37 @@ -90,13 +91,7 @@ 1.38 1.39 bool wd2797_get_irq(WD2797_CTX *ctx) 1.40 { 1.41 - // If an IRQ is pending, clear it and return true, otherwise return false 1.42 - if (ctx->irqe) { 1.43 - ctx->irqe = false; 1.44 - return true; 1.45 - } else { 1.46 - return false; 1.47 - } 1.48 + return ctx->irq; 1.49 } 1.50 1.51 1.52 @@ -164,8 +159,7 @@ 1.53 switch (addr & 0x03) { 1.54 case WD2797_REG_STATUS: // Status register 1.55 // Read from status register clears IRQ 1.56 - ctx->irql = false; 1.57 - ctx->irqe = false; 1.58 + ctx->irq = false; 1.59 1.60 // Get current status flags (set by last command) 1.61 // DRQ bit 1.62 @@ -192,9 +186,8 @@ 1.63 if (ctx->data_pos < ctx->data_len) { 1.64 // set IRQ if this is the last data byte 1.65 if (ctx->data_pos == (ctx->data_len-1)) { 1.66 - // Set IRQ only if IRQL has been cleared (no pending IRQs) 1.67 - ctx->irqe = ctx->irql ? ctx->irqe : true; 1.68 - ctx->irql = true; 1.69 + // Set IRQ 1.70 + ctx->irq = true; 1.71 } 1.72 // return data byte and increment pointer 1.73 return ctx->data[ctx->data_pos++]; 1.74 @@ -223,7 +216,7 @@ 1.75 switch (addr) { 1.76 case WD2797_REG_COMMAND: // Command register 1.77 // write to command register clears interrupt request 1.78 - ctx->irql = false; 1.79 + ctx->irq = false; 1.80 1.81 // Is the drive ready? 1.82 if (ctx->disc_image == NULL) { 1.83 @@ -314,9 +307,8 @@ 1.84 // S0 = Busy. We just exec'd the command, thus we're not busy. 1.85 // TODO: Set a timer for seeks, and ONLY clear BUSY when that timer expires. Need periodics for that. 1.86 1.87 - // Set IRQ only if IRQL has been cleared (no pending IRQs) 1.88 - ctx->irqe = ctx->irql ? ctx->irqe : true; 1.89 - ctx->irql = true; 1.90 + // Set IRQ 1.91 + ctx->irq = true; 1.92 return; 1.93 } 1.94 1.95 @@ -339,9 +331,8 @@ 1.96 // Set Write Protect bit and bail. 1.97 ctx->status = 0x40; 1.98 1.99 - // Set IRQ only if IRQL has been cleared (no pending IRQs) 1.100 - ctx->irqe = ctx->irql ? ctx->irqe : true; 1.101 - ctx->irql = true; 1.102 + // Set IRQ 1.103 + ctx->irq = true; 1.104 1.105 return; 1.106 } 1.107 @@ -463,9 +454,8 @@ 1.108 // TODO! 1.109 ctx->status = 0; 1.110 ctx->data_pos = ctx->data_len = 0; 1.111 - // Set IRQ only if IRQL has been cleared (no pending IRQs) 1.112 - ctx->irqe = ctx->irql ? ctx->irqe : true; 1.113 - ctx->irql = true; 1.114 + // Set IRQ 1.115 + ctx->irq = true; 1.116 break; 1.117 } 1.118 break; 1.119 @@ -487,9 +477,8 @@ 1.120 if (ctx->data_pos < ctx->data_len) { 1.121 // set IRQ if this is the last data byte 1.122 if (ctx->data_pos == (ctx->data_len-1)) { 1.123 - // Set IRQ only if IRQL has been cleared (no pending IRQs) 1.124 - ctx->irqe = ctx->irql ? ctx->irqe : true; 1.125 - ctx->irql = true; 1.126 + // Set IRQ 1.127 + ctx->irq = true; 1.128 } 1.129 1.130 // store data byte and increment pointer