3b1emu / files

     1.1 diff -r afe655559cc0 -r 5bbe76e71698 src/memory.c
     1.2 --- a/src/memory.c	Tue Dec 28 19:11:46 2010 +0000
     1.3 +++ b/src/memory.c	Tue Dec 28 19:23:57 2010 +0000
     1.4 @@ -128,7 +128,7 @@
     1.5  			m68k_pulse_bus_error();									\
     1.6  			return;													\
     1.7  		}															\
     1.8 -	} while (false)
     1.9 +	} while (0)
    1.10  /*}}}*/
    1.11  
    1.12  /**
    1.13 @@ -178,7 +178,7 @@
    1.14  			m68k_pulse_bus_error();									\
    1.15  			return 0xFFFFFFFF;										\
    1.16  		}															\
    1.17 -	} while (false)
    1.18 +	} while (0)
    1.19  /*}}}*/
    1.20  
    1.21  // Logging macros
    1.22 @@ -721,11 +721,10 @@
    1.23  	} else if (address <= 0x3FFFFF) {
    1.24  		// RAM access
    1.25  		uint32_t newAddr = mapAddr(address, true);
    1.26 -		if (newAddr <= 0x1fffff) {
    1.27 +		if (newAddr <= 0x1fffff)
    1.28  			WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
    1.29 -		} else {
    1.30 +		else
    1.31  			WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
    1.32 -		}
    1.33  	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
    1.34  		// I/O register space, zone A
    1.35  		switch (address & 0x0F0000) {
    1.36 @@ -762,11 +761,10 @@
    1.37  	} else if (address <= 0x3FFFFF) {
    1.38  		// RAM access
    1.39  		uint32_t newAddr = mapAddr(address, true);
    1.40 -		if (newAddr <= 0x1fffff) {
    1.41 +		if (newAddr <= 0x1fffff)
    1.42  			WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
    1.43 -		} else {
    1.44 +		else
    1.45  			WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
    1.46 -		}
    1.47  	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
    1.48  		// I/O register space, zone A
    1.49  		switch (address & 0x0F0000) {
    1.50 @@ -803,11 +801,10 @@
    1.51  	} else if (address <= 0x3FFFFF) {
    1.52  		// RAM access
    1.53  		uint32_t newAddr = mapAddr(address, true);
    1.54 -		if (newAddr <= 0x1fffff) {
    1.55 +		if (newAddr <= 0x1fffff)
    1.56  			WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
    1.57 -		} else {
    1.58 +		else
    1.59  			WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
    1.60 -		}
    1.61  	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
    1.62  		// I/O register space, zone A
    1.63  		switch (address & 0x0F0000) {

     2.1 diff -r afe655559cc0 -r 5bbe76e71698 src/memory.h
     2.2 --- a/src/memory.h	Tue Dec 28 19:11:46 2010 +0000
     2.3 +++ b/src/memory.h	Tue Dec 28 19:23:57 2010 +0000
     2.4 @@ -23,22 +23,23 @@
     2.5  	((uint32_t)array[(address + 0) & (andmask)])
     2.6  
     2.7  /// Array write, 32-bit
     2.8 -#define WR32(array, address, andmask, value) {					\
     2.9 +#define WR32(array, address, andmask, value) do {				\
    2.10  	array[(address + 0) & (andmask)] = (value >> 24) & 0xff;	\
    2.11  	array[(address + 1) & (andmask)] = (value >> 16) & 0xff;	\
    2.12  	array[(address + 2) & (andmask)] = (value >> 8)  & 0xff;	\
    2.13  	array[(address + 3) & (andmask)] =  value        & 0xff;	\
    2.14 -}
    2.15 +} while (0)
    2.16  
    2.17  /// Array write, 16-bit
    2.18 -#define WR16(array, address, andmask, value) {					\
    2.19 +#define WR16(array, address, andmask, value) do {				\
    2.20  	array[(address + 0) & (andmask)] = (value >> 8)  & 0xff;	\
    2.21  	array[(address + 1) & (andmask)] =  value        & 0xff;	\
    2.22 -}
    2.23 +} while (0)
    2.24  
    2.25  /// Array write, 8-bit
    2.26 -#define WR8(array, address, andmask, value)						\
    2.27 -	array[(address + 0) & (andmask)] =  value        & 0xff;
    2.28 +#define WR8(array, address, andmask, value) do {				\
    2.29 +	array[(address + 0) & (andmask)] =  value        & 0xff;	\
    2.30 +} while (0)
    2.31  
    2.32  /******************
    2.33   * Memory mapping