Wed, 02 Mar 2011 07:16:32 +0000
Add 60Hz timer tick patch from Andrew Warkentin <andreww591 gmail com>
... I have also attached a patch that adds the 60Hz timer interrupt (I'm not sure if it's totally correct, though, since the cursor blinks rather slowly).
Received-From: Andrew Warkentin <andreww591 gmail com>
Signed-Off-By: Philip Pemberton <philpem@philpem.me.uk>
| src/main.c | file | annotate | diff | revisions | |
| src/memory.c | file | annotate | diff | revisions | |
| src/state.c | file | annotate | diff | revisions | |
| src/state.h | file | annotate | diff | revisions |
1.1 --- a/src/main.c Tue Mar 01 21:33:32 2011 +0000 1.2 +++ b/src/main.c Wed Mar 02 07:16:32 2011 +0000 1.3 @@ -358,14 +358,19 @@ 1.4 m68k_set_irq(3); 1.5 } else { 1.6 lastirq_fdc = wd2797_get_irq(&state.fdc_ctx); 1.7 - m68k_set_irq(0); 1.8 + if (!state.timer_asserted){ 1.9 + m68k_set_irq(0); 1.10 + } 1.11 } 1.12 1.13 // Is it time to run the 60Hz periodic interrupt yet? 1.14 if (clock_cycles > CLOCKS_PER_60HZ) { 1.15 // Refresh the screen 1.16 refreshScreen(screen); 1.17 - // TODO: trigger periodic interrupt (if enabled) 1.18 + if (state.timer_enabled){ 1.19 + m68k_set_irq(6); 1.20 + state.timer_asserted = true; 1.21 + } 1.22 // scan the keyboard 1.23 keyboard_scan(&state.kbd); 1.24 // decrement clock cycle counter, we've handled the intr.
2.1 --- a/src/memory.c Tue Mar 01 21:33:32 2011 +0000 2.2 +++ b/src/memory.c Wed Mar 02 07:16:32 2011 +0000 2.3 @@ -285,6 +285,12 @@ 2.4 ENFORCE_SIZE_W(bits, address, 16, "MISCCON"); 2.5 // TODO: handle the ctrl bits properly 2.6 // TODO: &0x8000 --> dismiss 60hz intr 2.7 + if (data & 0x8000){ 2.8 + state.timer_enabled = 1; 2.9 + }else{ 2.10 + state.timer_enabled = 0; 2.11 + state.timer_asserted = 0; 2.12 + } 2.13 state.dma_reading = (data & 0x4000); 2.14 if (state.leds != ((~data & 0xF00) >> 8)) { 2.15 state.leds = (~data & 0xF00) >> 8;
3.1 --- a/src/state.c Tue Mar 01 21:33:32 2011 +0000 3.2 +++ b/src/state.c Wed Mar 02 07:16:32 2011 +0000 3.3 @@ -22,7 +22,7 @@ 3.4 state.leds = 0; 3.5 state.genstat = 0; // FIXME: check this 3.6 state.bsr0 = state.bsr1 = 0; // FIXME: check this 3.7 - 3.8 + state.timer_enabled = state.timer_asserted = false; 3.9 // Allocate Base RAM, making sure the user has specified a valid RAM amount first 3.10 // Basically: 512KiB minimum, 2MiB maximum, in increments of 512KiB. 3.11 if ((base_ram_size < 512*1024) || (base_ram_size > 2048*1024) || ((base_ram_size % (512*1024)) != 0))
4.1 --- a/src/state.h Tue Mar 01 21:33:32 2011 +0000 4.2 +++ b/src/state.h Wed Mar 02 07:16:32 2011 +0000 4.3 @@ -50,6 +50,9 @@ 4.4 bool dma_reading; ///< True if Disc DMA reads from the controller, false otherwise 4.5 uint8_t leds; ///< LED status, 1=on, in order red3/green2/yellow1/red0 from bit3 to bit0 4.6 4.7 + bool timer_enabled; 4.8 + bool timer_asserted; 4.9 + 4.10 //// GENERAL CONTROL REGISTER 4.11 /// GENCON.ROMLMAP -- false ORs the address with 0x800000, forcing the 4.12 /// 68010 to access ROM instead of RAM when booting. TRM page 2-36.