fix memory read stuff, now need to deal with memory write

Sun, 28 Nov 2010 20:52:53 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 28 Nov 2010 20:52:53 +0000
changeset 9
3e99497dca33
parent 8
e2dcbabc7e1c
child 10
dbf4ba9563c9

fix memory read stuff, now need to deal with memory write

Makefile file | annotate | diff | revisions
src/main.c file | annotate | diff | revisions
     1.1 --- a/Makefile	Sun Nov 28 20:02:45 2010 +0000
     1.2 +++ b/Makefile	Sun Nov 28 20:52:53 2010 +0000
     1.3 @@ -115,7 +115,7 @@
     1.4  TARGET		=	freebee
     1.5  
     1.6  # source files that produce object files
     1.7 -SRC			=	main.c musashi/m68kcpu.c musashi/m68kops.c musashi/m68kopac.c musashi/m68kopdm.c musashi/m68kopnz.c
     1.8 +SRC			=	main.c musashi/m68kcpu.c musashi/m68kdasm.c musashi/m68kops.c musashi/m68kopac.c musashi/m68kopdm.c musashi/m68kopnz.c
     1.9  
    1.10  # source type - either "c" or "cpp" (C or C++)
    1.11  SRC_TYPE	=	c
     2.1 --- a/src/main.c	Sun Nov 28 20:02:45 2010 +0000
     2.2 +++ b/src/main.c	Sun Nov 28 20:52:53 2010 +0000
     2.3 @@ -7,7 +7,7 @@
     2.4  #include "musashi/m68k.h"
     2.5  #include "version.h"
     2.6  
     2.7 -#define ROM_SIZE (32768/4)
     2.8 +#define ROM_SIZE (32768/2)
     2.9  
    2.10  void state_done(void);
    2.11  
    2.12 @@ -21,10 +21,10 @@
    2.13  
    2.14  struct {
    2.15  	// Boot PROM can be up to 32Kbytes total size
    2.16 -	uint32_t	rom[ROM_SIZE];
    2.17 +	uint16_t	rom[ROM_SIZE];
    2.18  
    2.19  	// Main system RAM
    2.20 -	uint32_t	*ram;
    2.21 +	uint16_t	*ram;
    2.22  	size_t		ram_size;			// number of RAM bytes allocated
    2.23  	uint32_t	ram_addr_mask;		// address mask
    2.24  
    2.25 @@ -74,12 +74,8 @@
    2.26  	fread(romdat2, 1, romlen2, r14c);
    2.27  
    2.28  	// convert the ROM data
    2.29 -	for (size_t i=0; i<romlen; i+=2) {
    2.30 -		state.rom[i/2] = (
    2.31 -				(romdat1[i+0] << 24) |
    2.32 -				(romdat2[i+0] << 16) |
    2.33 -				(romdat1[i+1] << 8)  |
    2.34 -				(romdat2[i+1]));
    2.35 +	for (size_t i=0; i<romlen; i++) {
    2.36 +		state.rom[i] = ((romdat1[i] << 8) | (romdat2[i]));
    2.37  	}
    2.38  
    2.39  	// free the data arrays and close the files
    2.40 @@ -102,48 +98,56 @@
    2.41  // TODO: find a way to make musashi use function pointers instead of hard coded callbacks, maybe use a context struct too
    2.42  uint32_t m68k_read_memory_32(uint32_t address)
    2.43  {
    2.44 +	uint32_t data = 0xFFFFFFFF;
    2.45 +
    2.46 +	printf("RD32 %08X %d", address, state.romlmap);
    2.47 +
    2.48  	// If ROMLMAP is set, force system to access ROM
    2.49  	if (!state.romlmap)
    2.50  		address |= 0x800000;
    2.51  
    2.52 -	if (address >= 0xC00000) {
    2.53 -		// I/O Registers B
    2.54 -		// TODO
    2.55 -	} else if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
    2.56 +	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
    2.57  		// ROM access
    2.58 -		return state.rom[(address & (ROM_SIZE-1)) / 4];
    2.59 -	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
    2.60 -		// I/O Registers A
    2.61 -		// TODO
    2.62 +		data = ((state.rom[(address & (ROM_SIZE-1)) / 2] << 16) | (state.rom[((address & (ROM_SIZE-1)) / 2)+1]));
    2.63  	} else if (address <= 0x3FFFFF) {
    2.64  		// RAM
    2.65 -		return state.ram[(address & state.ram_addr_mask) / 4];
    2.66 +		data = state.ram[(address & state.ram_addr_mask) / 2];
    2.67  	}
    2.68 -	return 0xffffffff;
    2.69 +
    2.70 +	printf(" ==> %04X\n", data);
    2.71 +	return data;
    2.72  }
    2.73  
    2.74  uint32_t m68k_read_memory_16(uint32_t address)
    2.75  {
    2.76 -	if (address & 2) {
    2.77 -		return m68k_read_memory_32(address) & 0xFFFF;
    2.78 -	} else {
    2.79 -		return (m68k_read_memory_32(address) >> 16) & 0xFFFF;
    2.80 -	}
    2.81 +	uint16_t data = 0xFFFF;
    2.82 +
    2.83 +	printf("RD16 %08X %d", address, state.romlmap);
    2.84 +
    2.85 +	// If ROMLMAP is set, force system to access ROM
    2.86 +	if (!state.romlmap)
    2.87 +		address |= 0x800000;
    2.88 +
    2.89 +	data = (m68k_read_memory_32(address) >> 16) & 0xFFFF;
    2.90 +
    2.91 +	printf(" ==> %04X\n", data);
    2.92 +	return data;
    2.93  }
    2.94  
    2.95  uint32_t m68k_read_memory_8(uint32_t address)
    2.96  {
    2.97 +	uint8_t data = 0xFF;
    2.98 +
    2.99 +	printf("RD 8 %08X %d ", address, state.romlmap);
   2.100 +
   2.101  	// If ROMLMAP is set, force system to access ROM
   2.102  	if (!state.romlmap)
   2.103  		address |= 0x800000;
   2.104  
   2.105 -	switch (address & 3) {
   2.106 -		case 3:		return m68k_read_memory_32(address)			& 0xFF;
   2.107 -		case 2:		return (m68k_read_memory_32(address) >> 8)	& 0xFF;
   2.108 -		case 1:		return (m68k_read_memory_32(address) >> 16)	& 0xFF;
   2.109 -		case 0:		return (m68k_read_memory_32(address) >> 24)	& 0xFF;
   2.110 -	}
   2.111 -	return 0xffffffff;
   2.112 +	data = m68k_read_memory_32(address) & 0xFF;
   2.113 +
   2.114 +	printf("==> %02X\n", data);
   2.115 +	return data;
   2.116  }
   2.117  
   2.118  // write m68k memory
   2.119 @@ -153,18 +157,19 @@
   2.120  	if (!state.romlmap)
   2.121  		address |= 0x800000;
   2.122  
   2.123 -	if (address >= 0xC00000) {
   2.124 -		// I/O Registers B
   2.125 -		// TODO
   2.126 -	} else if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   2.127 +	printf("WR32 %08X %d %02X\n", address, state.romlmap, value);
   2.128 +
   2.129 +	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   2.130  		// ROM access
   2.131  		// TODO: bus error here? can't write to rom!
   2.132 -	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   2.133 -		// I/O Registers A
   2.134 -		// TODO
   2.135  	} else if (address <= 0x3FFFFF) {
   2.136  		// RAM
   2.137 -		state.ram[(address & state.ram_addr_mask) / 4] = value;
   2.138 +		state.ram[(address & state.ram_addr_mask) / 2] = (value >> 16);
   2.139 +		state.ram[((address & state.ram_addr_mask) / 2)+1] = value & 0xffff;
   2.140 +	} else {
   2.141 +		switch (address) {
   2.142 +			case 0xE43000:	state.romlmap = ((value & 0x8000) == 0x8000);
   2.143 +		}
   2.144  	}
   2.145  }
   2.146  
   2.147 @@ -174,21 +179,18 @@
   2.148  	if (!state.romlmap)
   2.149  		address |= 0x800000;
   2.150  
   2.151 -	if (address >= 0xC00000) {
   2.152 -		// I/O Registers B
   2.153 -		// TODO
   2.154 -	} else if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   2.155 +	printf("WR16 %08X %d %02X\n", address, state.romlmap, value);
   2.156 +
   2.157 +	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   2.158  		// ROM access
   2.159  		// TODO: bus error here? can't write to rom!
   2.160 -	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   2.161 -		// I/O Registers A
   2.162 -		// TODO
   2.163  	} else if (address <= 0x3FFFFF) {
   2.164  		// RAM
   2.165 -		if (address & 2)
   2.166 -			state.ram[(address & state.ram_addr_mask) / 4] = (state.ram[(address & state.ram_addr_mask) / 4] & 0xFFFF0000) | (value & 0xFFFF);
   2.167 -		else
   2.168 -			state.ram[(address & state.ram_addr_mask) / 4] = (state.ram[(address & state.ram_addr_mask) / 4] & 0x0000FFFF) | ((value & 0xFFFF) << 16);
   2.169 +		state.ram[(address & state.ram_addr_mask) / 2] = value & 0xFFFF;
   2.170 +	} else {
   2.171 +		switch (address) {
   2.172 +			case 0xE43000:	state.romlmap = ((value & 0x8000) == 0x8000);
   2.173 +		}
   2.174  	}
   2.175  }
   2.176  
   2.177 @@ -198,26 +200,31 @@
   2.178  	if (!state.romlmap)
   2.179  		address |= 0x800000;
   2.180  
   2.181 -	if (address >= 0xC00000) {
   2.182 -		// I/O Registers B
   2.183 -		// TODO
   2.184 -	} else if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   2.185 +	printf("WR 8 %08X %d %02X\n", address, state.romlmap, value);
   2.186 +
   2.187 +	if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
   2.188  		// ROM access
   2.189  		// TODO: bus error here? can't write to rom!
   2.190 -	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
   2.191 -		// I/O Registers A
   2.192 -		// TODO
   2.193  	} else if (address <= 0x3FFFFF) {
   2.194  		// RAM
   2.195  		switch (address & 3) {
   2.196 +			// FIXME
   2.197  			case 3:		state.ram[(address & state.ram_addr_mask) / 4] = (state.ram[(address & state.ram_addr_mask) / 4] & 0xFFFFFF00) | (value & 0xFF);
   2.198  			case 2:		state.ram[(address & state.ram_addr_mask) / 4] = (state.ram[(address & state.ram_addr_mask) / 4] & 0xFFFF00FF) | ((value & 0xFF) << 8);
   2.199  			case 1:		state.ram[(address & state.ram_addr_mask) / 4] = (state.ram[(address & state.ram_addr_mask) / 4] & 0xFF00FFFF) | ((value & 0xFF) << 16);
   2.200  			case 0:		state.ram[(address & state.ram_addr_mask) / 4] = (state.ram[(address & state.ram_addr_mask) / 4] & 0x00FFFFFF) | ((value & 0xFF) << 24);
   2.201  		}
   2.202 +	} else {
   2.203 +		switch (address) {
   2.204 +			case 0xE43000:	state.romlmap = ((value & 0x80) == 0x80);
   2.205 +		}
   2.206  	}
   2.207  }
   2.208  
   2.209 +uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
   2.210 +uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
   2.211 +uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }
   2.212 +
   2.213  int main(void)
   2.214  {
   2.215  	// copyright banner
   2.216 @@ -234,6 +241,10 @@
   2.217  	m68k_set_cpu_type(M68K_CPU_TYPE_68010);
   2.218  	m68k_pulse_reset();
   2.219  
   2.220 +	char dasm[512];
   2.221 +	m68k_disassemble(dasm, 0x80001a, M68K_CPU_TYPE_68010);
   2.222 +	printf("%s\n", dasm);
   2.223 +
   2.224  	// set up SDL
   2.225  
   2.226  	// emulation loop!