3b1emu / files

     1.1 --- a/src/memory.c	Thu Dec 02 23:37:49 2010 +0000
     1.2 +++ b/src/memory.c	Fri Dec 03 00:04:01 2010 +0000
     1.3 @@ -98,12 +98,12 @@
     1.4  				break;												\
     1.5  			case MEM_PAGEFAULT:										\
     1.6  				/* Page fault */									\
     1.7 -				state.genstat = 0x8FFF;								\
     1.8 +				state.genstat = 0x8BFF | (status.pie ? 0x0400 : 0);	\
     1.9  				fault = true;										\
    1.10  				break;												\
    1.11  			case MEM_UIE:											\
    1.12  				/* User access to memory above 4MB */				\
    1.13 -				state.genstat = 0x9EFF;								\
    1.14 +				state.genstat = 0x9AFF | (status.pie ? 0x0400 : 0);	\
    1.15  				fault = true;										\
    1.16  				break;												\
    1.17  			case MEM_KERNEL:										\
    1.18 @@ -145,12 +145,12 @@
    1.19  				break;												\
    1.20  			case MEM_PAGEFAULT:										\
    1.21  				/* Page fault */									\
    1.22 -				state.genstat = 0x8FFF;								\
    1.23 +				state.genstat = 0xCBFF | (status.pie ? 0x0400 : 0);	\
    1.24  				fault = true;										\
    1.25  				break;												\
    1.26  			case MEM_UIE:											\
    1.27  				/* User access to memory above 4MB */				\
    1.28 -				state.genstat = 0x9EFF;								\
    1.29 +				state.genstat = 0xDAFF | (status.pie ? 0x0400 : 0);	\
    1.30  				fault = true;										\
    1.31  				break;												\
    1.32  			case MEM_KERNEL:										\
    1.33 @@ -275,7 +275,8 @@
    1.34  				break;
    1.35  			case 0x0B0000:				// TM/DIALWR
    1.36  				break;
    1.37 -			case 0x0C0000:				// CSR
    1.38 +			case 0x0C0000:				// Clear Status Register
    1.39 +				handled = true;
    1.40  				break;
    1.41  			case 0x0D0000:				// DMA Address Register
    1.42  				break;
    1.43 @@ -439,7 +440,8 @@
    1.44  				break;
    1.45  			case 0x0B0000:				// TM/DIALWR
    1.46  				break;
    1.47 -			case 0x0C0000:				// CSR
    1.48 +			case 0x0C0000:				// Clear Status Register
    1.49 +				handled = true;
    1.50  				break;
    1.51  			case 0x0D0000:				// DMA Address Register
    1.52  				break;
    1.53 @@ -612,7 +614,8 @@
    1.54  				break;
    1.55  			case 0x0B0000:				// TM/DIALWR
    1.56  				break;
    1.57 -			case 0x0C0000:				// CSR
    1.58 +			case 0x0C0000:				// Clear Status Register
    1.59 +				handled = true;
    1.60  				break;
    1.61  			case 0x0D0000:				// DMA Address Register
    1.62  				break;
    1.63 @@ -770,7 +773,11 @@
    1.64  				break;
    1.65  			case 0x0B0000:				// TM/DIALWR
    1.66  				break;
    1.67 -			case 0x0C0000:				// CSR
    1.68 +			case 0x0C0000:				// Clear Status Register
    1.69 +				state.genstat = 0xFFFF;
    1.70 +				state.bsr0 = 0xFFFF;
    1.71 +				state.bsr1 = 0xFFFF;
    1.72 +				handled = true;
    1.73  				break;
    1.74  			case 0x0D0000:				// DMA Address Register
    1.75  				break;
    1.76 @@ -929,7 +936,11 @@
    1.77  				break;
    1.78  			case 0x0B0000:				// TM/DIALWR
    1.79  				break;
    1.80 -			case 0x0C0000:				// CSR
    1.81 +			case 0x0C0000:				// Clear Status Register
    1.82 +				state.genstat = 0xFFFF;
    1.83 +				state.bsr0 = 0xFFFF;
    1.84 +				state.bsr1 = 0xFFFF;
    1.85 +				handled = true;
    1.86  				break;
    1.87  			case 0x0D0000:				// DMA Address Register
    1.88  				break;
    1.89 @@ -1088,7 +1099,11 @@
    1.90  				break;
    1.91  			case 0x0B0000:				// TM/DIALWR
    1.92  				break;
    1.93 -			case 0x0C0000:				// CSR
    1.94 +			case 0x0C0000:				// Clear Status Register
    1.95 +				state.genstat = 0xFFFF;
    1.96 +				state.bsr0 = 0xFFFF;
    1.97 +				state.bsr1 = 0xFFFF;
    1.98 +				handled = true;
    1.99  				break;
   1.100  			case 0x0D0000:				// DMA Address Register
   1.101  				break;