3b1emu / files

     1.1 --- a/src/memory.c	Tue Dec 28 19:11:46 2010 +0000
     1.2 +++ b/src/memory.c	Tue Dec 28 19:23:57 2010 +0000
     1.3 @@ -128,7 +128,7 @@
     1.4  			m68k_pulse_bus_error();									\
     1.5  			return;													\
     1.6  		}															\
     1.7 -	} while (false)
     1.8 +	} while (0)
     1.9  /*}}}*/
    1.10  
    1.11  /**
    1.12 @@ -178,7 +178,7 @@
    1.13  			m68k_pulse_bus_error();									\
    1.14  			return 0xFFFFFFFF;										\
    1.15  		}															\
    1.16 -	} while (false)
    1.17 +	} while (0)
    1.18  /*}}}*/
    1.19  
    1.20  // Logging macros
    1.21 @@ -721,11 +721,10 @@
    1.22  	} else if (address <= 0x3FFFFF) {
    1.23  		// RAM access
    1.24  		uint32_t newAddr = mapAddr(address, true);
    1.25 -		if (newAddr <= 0x1fffff) {
    1.26 +		if (newAddr <= 0x1fffff)
    1.27  			WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
    1.28 -		} else {
    1.29 +		else
    1.30  			WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
    1.31 -		}
    1.32  	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
    1.33  		// I/O register space, zone A
    1.34  		switch (address & 0x0F0000) {
    1.35 @@ -762,11 +761,10 @@
    1.36  	} else if (address <= 0x3FFFFF) {
    1.37  		// RAM access
    1.38  		uint32_t newAddr = mapAddr(address, true);
    1.39 -		if (newAddr <= 0x1fffff) {
    1.40 +		if (newAddr <= 0x1fffff)
    1.41  			WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
    1.42 -		} else {
    1.43 +		else
    1.44  			WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
    1.45 -		}
    1.46  	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
    1.47  		// I/O register space, zone A
    1.48  		switch (address & 0x0F0000) {
    1.49 @@ -803,11 +801,10 @@
    1.50  	} else if (address <= 0x3FFFFF) {
    1.51  		// RAM access
    1.52  		uint32_t newAddr = mapAddr(address, true);
    1.53 -		if (newAddr <= 0x1fffff) {
    1.54 +		if (newAddr <= 0x1fffff)
    1.55  			WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
    1.56 -		} else {
    1.57 +		else
    1.58  			WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
    1.59 -		}
    1.60  	} else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
    1.61  		// I/O register space, zone A
    1.62  		switch (address & 0x0F0000) {

     2.1 --- a/src/memory.h	Tue Dec 28 19:11:46 2010 +0000
     2.2 +++ b/src/memory.h	Tue Dec 28 19:23:57 2010 +0000
     2.3 @@ -23,22 +23,23 @@
     2.4  	((uint32_t)array[(address + 0) & (andmask)])
     2.5  
     2.6  /// Array write, 32-bit
     2.7 -#define WR32(array, address, andmask, value) {					\
     2.8 +#define WR32(array, address, andmask, value) do {				\
     2.9  	array[(address + 0) & (andmask)] = (value >> 24) & 0xff;	\
    2.10  	array[(address + 1) & (andmask)] = (value >> 16) & 0xff;	\
    2.11  	array[(address + 2) & (andmask)] = (value >> 8)  & 0xff;	\
    2.12  	array[(address + 3) & (andmask)] =  value        & 0xff;	\
    2.13 -}
    2.14 +} while (0)
    2.15  
    2.16  /// Array write, 16-bit
    2.17 -#define WR16(array, address, andmask, value) {					\
    2.18 +#define WR16(array, address, andmask, value) do {				\
    2.19  	array[(address + 0) & (andmask)] = (value >> 8)  & 0xff;	\
    2.20  	array[(address + 1) & (andmask)] =  value        & 0xff;	\
    2.21 -}
    2.22 +} while (0)
    2.23  
    2.24  /// Array write, 8-bit
    2.25 -#define WR8(array, address, andmask, value)						\
    2.26 -	array[(address + 0) & (andmask)] =  value        & 0xff;
    2.27 +#define WR8(array, address, andmask, value) do {				\
    2.28 +	array[(address + 0) & (andmask)] =  value        & 0xff;	\
    2.29 +} while (0)
    2.30  
    2.31  /******************
    2.32   * Memory mapping